1 # Copyright (c) 2006 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 from m5
.objects
import *
31 m5
.util
.addToPath('../configs/')
32 from common
.FSConfig
import *
33 from common
.Benchmarks
import *
35 test_sys
= makeLinuxAlphaSystem('atomic',
36 SysConfig('netperf-stream-client.rcS'))
38 # Dummy voltage domain for all test_sys clock domains
39 test_sys
.voltage_domain
= VoltageDomain()
41 # Create the system clock domain
42 test_sys
.clk_domain
= SrcClockDomain(clock
= '1GHz',
43 voltage_domain
= test_sys
.voltage_domain
)
45 test_sys
.cpu
= AtomicSimpleCPU(cpu_id
=0)
46 # create the interrupt controller
47 test_sys
.cpu
.createInterruptController()
48 test_sys
.cpu
.connectAllPorts(test_sys
.membus
)
50 # Create a seperate clock domain for components that should run at
52 test_sys
.cpu
.clk_domain
= SrcClockDomain(clock
= '2GHz',
54 test_sys
.voltage_domain
)
56 # Create a separate clock domain for Ethernet
57 test_sys
.tsunami
.ethernet
.clk_domain
= SrcClockDomain(clock
= '500MHz',
59 test_sys
.voltage_domain
)
61 # In contrast to the other (one-system) Tsunami configurations we do
62 # not have an IO cache but instead rely on an IO bridge for accesses
63 # from masters on the IO bus to the memory bus
64 test_sys
.iobridge
= Bridge(delay
='50ns', ranges
= test_sys
.mem_ranges
)
65 test_sys
.iobridge
.slave
= test_sys
.iobus
.master
66 test_sys
.iobridge
.master
= test_sys
.membus
.slave
68 test_sys
.physmem
= SimpleMemory(range = test_sys
.mem_ranges
[0])
69 test_sys
.physmem
.port
= test_sys
.membus
.master
71 drive_sys
= makeLinuxAlphaSystem('atomic',
72 SysConfig('netperf-server.rcS'))
73 # Dummy voltage domain for all drive_sys clock domains
74 drive_sys
.voltage_domain
= VoltageDomain()
75 # Create the system clock domain
76 drive_sys
.clk_domain
= SrcClockDomain(clock
= '1GHz',
78 drive_sys
.voltage_domain
)
79 drive_sys
.cpu
= AtomicSimpleCPU(cpu_id
=0)
80 # create the interrupt controller
81 drive_sys
.cpu
.createInterruptController()
82 drive_sys
.cpu
.connectAllPorts(drive_sys
.membus
)
84 # Create a seperate clock domain for components that should run at
86 drive_sys
.cpu
.clk_domain
= SrcClockDomain(clock
= '4GHz',
88 drive_sys
.voltage_domain
)
90 # Create a separate clock domain for Ethernet
91 drive_sys
.tsunami
.ethernet
.clk_domain
= SrcClockDomain(clock
= '500MHz',
93 drive_sys
.voltage_domain
)
95 drive_sys
.iobridge
= Bridge(delay
='50ns', ranges
= drive_sys
.mem_ranges
)
96 drive_sys
.iobridge
.slave
= drive_sys
.iobus
.master
97 drive_sys
.iobridge
.master
= drive_sys
.membus
.slave
99 drive_sys
.physmem
= SimpleMemory(range = drive_sys
.mem_ranges
[0])
100 drive_sys
.physmem
.port
= drive_sys
.membus
.master
102 root
= makeDualRoot(True, test_sys
, drive_sys
, "ethertrace")