tests/gem5/cpu_tests/run.py

   1 # -*- coding: utf-8 -*-
   2 # Copyright (c) 2018 The Regents of the University of California
   3 # All Rights Reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27
  28 import os
  29 import argparse
  30
  31 import m5
  32 from m5.objects import *
  33
  34 class L1Cache(Cache):
  35     """Simple L1 Cache with default values"""
  36
  37     assoc = 8
  38     tag_latency = 1
  39     data_latency = 1
  40     response_latency = 1
  41     mshrs = 16
  42     tgts_per_mshr = 20
  43
  44     def connectBus(self, bus):
  45         """Connect this cache to a memory-side bus"""
  46         self.mem_side = bus.slave
  47
  48     def connectCPU(self, cpu):
  49         """Connect this cache's port to a CPU-side port
  50            This must be defined in a subclass"""
  51         raise NotImplementedError
  52
  53 class L1ICache(L1Cache):
  54     """Simple L1 instruction cache with default values"""
  55
  56     # Set the default size
  57     size = '32kB'
  58
  59     def connectCPU(self, cpu):
  60         """Connect this cache's port to a CPU icache port"""
  61         self.cpu_side = cpu.icache_port
  62
  63 class L1DCache(L1Cache):
  64     """Simple L1 data cache with default values"""
  65
  66     # Set the default size
  67     size = '32kB'
  68
  69     def connectCPU(self, cpu):
  70         """Connect this cache's port to a CPU dcache port"""
  71         self.cpu_side = cpu.dcache_port
  72
  73 class L2Cache(Cache):
  74     """Simple L2 Cache with default values"""
  75
  76     # Default parameters
  77     size = '512kB'
  78     assoc = 16
  79     tag_latency = 10
  80     data_latency = 10
  81     response_latency = 1
  82     mshrs = 20
  83     tgts_per_mshr = 12
  84
  85     def connectCPUSideBus(self, bus):
  86         self.cpu_side = bus.master
  87
  88     def connectMemSideBus(self, bus):
  89         self.mem_side = bus.slave
  90
  91
  92 class MySimpleMemory(SimpleMemory):
  93     latency = '1ns'
  94
  95 if buildEnv['TARGET_ISA'] == 'x86':
  96   valid_cpu = {'AtomicSimpleCPU': AtomicSimpleCPU,
  97                'TimingSimpleCPU': TimingSimpleCPU,
  98                'DerivO3CPU': DerivO3CPU
  99               }
 100 else:
 101   valid_cpu = {'AtomicSimpleCPU': AtomicSimpleCPU,
 102                'TimingSimpleCPU': TimingSimpleCPU,
 103                'MinorCPU': MinorCPU,
 104                'DerivO3CPU': DerivO3CPU,
 105               }
 106
 107 valid_mem = {'SimpleMemory': MySimpleMemory,
 108              'DDR3_1600_8x8': DDR3_1600_8x8
 109             }
 110
 111 parser = argparse.ArgumentParser()
 112 parser.add_argument('binary', type = str)
 113 parser.add_argument('--cpu', choices = valid_cpu.keys(),
 114                     default = 'TimingSimpleCPU')
 115 parser.add_argument('--mem', choices = valid_mem.keys(),
 116                     default = 'SimpleMemory')
 117
 118 args = parser.parse_args()
 119
 120 system = System()
 121
 122 system.clk_domain = SrcClockDomain()
 123 system.clk_domain.clock = '1GHz'
 124 system.clk_domain.voltage_domain = VoltageDomain()
 125
 126 if args.cpu != "AtomicSimpleCPU":
 127         system.mem_mode = 'timing'
 128
 129 system.mem_ranges = [AddrRange('512MB')]
 130
 131 system.cpu = valid_cpu[args.cpu]()
 132
 133 if args.cpu == "AtomicSimpleCPU":
 134     system.membus = SystemXBar()
 135     system.cpu.icache_port = system.membus.slave
 136     system.cpu.dcache_port = system.membus.slave
 137 else:
 138     system.cpu.l1d = L1DCache()
 139     system.cpu.l1i = L1ICache()
 140     system.l1_to_l2 = L2XBar()
 141     system.l2cache = L2Cache()
 142     system.membus = SystemXBar()
 143     system.cpu.l1d.connectCPU(system.cpu)
 144     system.cpu.l1d.connectBus(system.l1_to_l2)
 145     system.cpu.l1i.connectCPU(system.cpu)
 146     system.cpu.l1i.connectBus(system.l1_to_l2)
 147     system.l2cache.connectCPUSideBus(system.l1_to_l2)
 148     system.l2cache.connectMemSideBus(system.membus)
 149
 150 system.cpu.createInterruptController()
 151 if m5.defines.buildEnv['TARGET_ISA'] == "x86":
 152     system.cpu.interrupts[0].pio = system.membus.master
 153     system.cpu.interrupts[0].int_master = system.membus.slave
 154     system.cpu.interrupts[0].int_slave = system.membus.master
 155
 156 system.mem_ctrl = valid_mem[args.mem]()
 157 system.mem_ctrl.range = system.mem_ranges[0]
 158 system.mem_ctrl.port = system.membus.master
 159 system.system_port = system.membus.slave
 160
 161 process = Process()
 162 process.cmd = [args.binary]
 163 system.cpu.workload = process
 164 system.cpu.createThreads()
 165
 166 root = Root(full_system = False, system = system)
 167 m5.instantiate()
 168
 169 exit_event = m5.simulate()
 170
 171 if exit_event.getCause() != 'exiting with last active thread context':
 172     exit(1)