Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig
[yosys.git] / tests / hana / hana_vlib.v
1 /*
2 Copyright (C) 2009-2010 Parvez Ahmad
3 Written by Parvez Ahmad <parvez_ahmad@yahoo.co.uk>.
4
5 This program is free software: you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program. If not, see <http://www.gnu.org/licenses/>. */
17
18
19 module BUF (input in, output out);
20
21 assign out = in;
22
23 endmodule
24
25 module TRIBUF(input in, enable, output out);
26
27 assign out = enable ? in : 1'bz;
28
29 endmodule
30
31 module INV(input in, output out);
32
33 assign out = ~in;
34
35 endmodule
36
37 module AND2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);
38
39 assign out = &in;
40
41 endmodule
42
43 module AND3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
44
45 assign out = &in;
46
47 endmodule
48
49 module AND4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
50
51 assign out = &in;
52
53 endmodule
54
55 module OR2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);
56
57 assign out = |in;
58
59 endmodule
60
61 module OR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
62
63 assign out = |in;
64
65 endmodule
66
67 module OR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
68
69 assign out = |in;
70
71 endmodule
72
73
74 module NAND2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);
75
76 assign out = ~&in;
77
78 endmodule
79
80 module NAND3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
81
82 assign out = ~&in;
83
84 endmodule
85
86 module NAND4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
87
88 assign out = ~&in;
89
90 endmodule
91
92 module NOR2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);
93
94 assign out = ~|in;
95
96 endmodule
97
98 module NOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
99
100 assign out = ~|in;
101
102 endmodule
103
104 module NOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
105
106 assign out = ~|in;
107
108 endmodule
109
110
111 module XOR2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);
112
113 assign out = ^in;
114
115 endmodule
116
117 module XOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
118
119 assign out = ^in;
120
121 endmodule
122
123 module XOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
124
125 assign out = ^in;
126
127 endmodule
128
129
130 module XNOR2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);
131
132 assign out = ~^in;
133
134 endmodule
135
136 module XNOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
137
138 assign out = ~^in;
139
140 endmodule
141
142 module XNOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
143
144 assign out = ~^in;
145
146 endmodule
147
148 module DEC1 (input in, enable, output reg [1:0] out);
149
150 always @(in or enable)
151 if(!enable)
152 out = 2'b00;
153 else begin
154 case (in)
155 1'b0 : out = 2'b01;
156 1'b1 : out = 2'b10;
157 endcase
158 end
159 endmodule
160
161 module DEC2 (input [1:0] in, input enable, output reg [3:0] out);
162
163 always @(in or enable)
164 if(!enable)
165 out = 4'b0000;
166 else begin
167 case (in)
168 2'b00 : out = 4'b0001;
169 2'b01 : out = 4'b0010;
170 2'b10 : out = 4'b0100;
171 2'b11 : out = 4'b1000;
172 endcase
173 end
174 endmodule
175
176 module DEC3 (input [2:0] in, input enable, output reg [7:0] out);
177
178 always @(in or enable)
179 if(!enable)
180 out = 8'b00000000;
181 else begin
182 case (in)
183 3'b000 : out = 8'b00000001;
184 3'b001 : out = 8'b00000010;
185 3'b010 : out = 8'b00000100;
186 3'b011 : out = 8'b00001000;
187 3'b100 : out = 8'b00010000;
188 3'b101 : out = 8'b00100000;
189 3'b110 : out = 8'b01000000;
190 3'b111 : out = 8'b10000000;
191 endcase
192 end
193 endmodule
194
195 module DEC4 (input [3:0] in, input enable, output reg [15:0] out);
196
197 always @(in or enable)
198 if(!enable)
199 out = 16'b0000000000000000;
200 else begin
201 case (in)
202 4'b0000 : out = 16'b0000000000000001;
203 4'b0001 : out = 16'b0000000000000010;
204 4'b0010 : out = 16'b0000000000000100;
205 4'b0011 : out = 16'b0000000000001000;
206 4'b0100 : out = 16'b0000000000010000;
207 4'b0101 : out = 16'b0000000000100000;
208 4'b0110 : out = 16'b0000000001000000;
209 4'b0111 : out = 16'b0000000010000000;
210 4'b1000 : out = 16'b0000000100000000;
211 4'b1001 : out = 16'b0000001000000000;
212 4'b1010 : out = 16'b0000010000000000;
213 4'b1011 : out = 16'b0000100000000000;
214 4'b1100 : out = 16'b0001000000000000;
215 4'b1101 : out = 16'b0010000000000000;
216 4'b1110 : out = 16'b0100000000000000;
217 4'b1111 : out = 16'b1000000000000000;
218 endcase
219 end
220 endmodule
221 module DEC5 (input [4:0] in, input enable, output reg [31:0] out);
222
223 always @(in or enable)
224 if(!enable)
225 out = 32'b00000000000000000000000000000000;
226 else begin
227 case (in)
228 5'b00000 : out = 32'b00000000000000000000000000000001;
229 5'b00001 : out = 32'b00000000000000000000000000000010;
230 5'b00010 : out = 32'b00000000000000000000000000000100;
231 5'b00011 : out = 32'b00000000000000000000000000001000;
232 5'b00100 : out = 32'b00000000000000000000000000010000;
233 5'b00101 : out = 32'b00000000000000000000000000100000;
234 5'b00110 : out = 32'b00000000000000000000000001000000;
235 5'b00111 : out = 32'b00000000000000000000000010000000;
236 5'b01000 : out = 32'b00000000000000000000000100000000;
237 5'b01001 : out = 32'b00000000000000000000001000000000;
238 5'b01010 : out = 32'b00000000000000000000010000000000;
239 5'b01011 : out = 32'b00000000000000000000100000000000;
240 5'b01100 : out = 32'b00000000000000000001000000000000;
241 5'b01101 : out = 32'b00000000000000000010000000000000;
242 5'b01110 : out = 32'b00000000000000000100000000000000;
243 5'b01111 : out = 32'b00000000000000001000000000000000;
244 5'b10000 : out = 32'b00000000000000010000000000000000;
245 5'b10001 : out = 32'b00000000000000100000000000000000;
246 5'b10010 : out = 32'b00000000000001000000000000000000;
247 5'b10011 : out = 32'b00000000000010000000000000000000;
248 5'b10100 : out = 32'b00000000000100000000000000000000;
249 5'b10101 : out = 32'b00000000001000000000000000000000;
250 5'b10110 : out = 32'b00000000010000000000000000000000;
251 5'b10111 : out = 32'b00000000100000000000000000000000;
252 5'b11000 : out = 32'b00000001000000000000000000000000;
253 5'b11001 : out = 32'b00000010000000000000000000000000;
254 5'b11010 : out = 32'b00000100000000000000000000000000;
255 5'b11011 : out = 32'b00001000000000000000000000000000;
256 5'b11100 : out = 32'b00010000000000000000000000000000;
257 5'b11101 : out = 32'b00100000000000000000000000000000;
258 5'b11110 : out = 32'b01000000000000000000000000000000;
259 5'b11111 : out = 32'b10000000000000000000000000000000;
260 endcase
261 end
262 endmodule
263
264 module DEC6 (input [5:0] in, input enable, output reg [63:0] out);
265
266 always @(in or enable)
267 if(!enable)
268 out = 64'b0000000000000000000000000000000000000000000000000000000000000000;
269 else begin
270 case (in)
271 6'b000000 : out = 64'b0000000000000000000000000000000000000000000000000000000000000001;
272 6'b000001 : out = 64'b0000000000000000000000000000000000000000000000000000000000000010;
273 6'b000010 : out = 64'b0000000000000000000000000000000000000000000000000000000000000100;
274 6'b000011 : out = 64'b0000000000000000000000000000000000000000000000000000000000001000;
275 6'b000100 : out = 64'b0000000000000000000000000000000000000000000000000000000000010000;
276 6'b000101 : out = 64'b0000000000000000000000000000000000000000000000000000000000100000;
277 6'b000110 : out = 64'b0000000000000000000000000000000000000000000000000000000001000000;
278 6'b000111 : out = 64'b0000000000000000000000000000000000000000000000000000000010000000;
279 6'b001000 : out = 64'b0000000000000000000000000000000000000000000000000000000100000000;
280 6'b001001 : out = 64'b0000000000000000000000000000000000000000000000000000001000000000;
281 6'b001010 : out = 64'b0000000000000000000000000000000000000000000000000000010000000000;
282 6'b001011 : out = 64'b0000000000000000000000000000000000000000000000000000100000000000;
283 6'b001100 : out = 64'b0000000000000000000000000000000000000000000000000001000000000000;
284 6'b001101 : out = 64'b0000000000000000000000000000000000000000000000000010000000000000;
285 6'b001110 : out = 64'b0000000000000000000000000000000000000000000000000100000000000000;
286 6'b001111 : out = 64'b0000000000000000000000000000000000000000000000001000000000000000;
287 6'b010000 : out = 64'b0000000000000000000000000000000000000000000000010000000000000000;
288 6'b010001 : out = 64'b0000000000000000000000000000000000000000000000100000000000000000;
289 6'b010010 : out = 64'b0000000000000000000000000000000000000000000001000000000000000000;
290 6'b010011 : out = 64'b0000000000000000000000000000000000000000000010000000000000000000;
291 6'b010100 : out = 64'b0000000000000000000000000000000000000000000100000000000000000000;
292 6'b010101 : out = 64'b0000000000000000000000000000000000000000001000000000000000000000;
293 6'b010110 : out = 64'b0000000000000000000000000000000000000000010000000000000000000000;
294 6'b010111 : out = 64'b0000000000000000000000000000000000000000100000000000000000000000;
295 6'b011000 : out = 64'b0000000000000000000000000000000000000001000000000000000000000000;
296 6'b011001 : out = 64'b0000000000000000000000000000000000000010000000000000000000000000;
297 6'b011010 : out = 64'b0000000000000000000000000000000000000100000000000000000000000000;
298 6'b011011 : out = 64'b0000000000000000000000000000000000001000000000000000000000000000;
299 6'b011100 : out = 64'b0000000000000000000000000000000000010000000000000000000000000000;
300 6'b011101 : out = 64'b0000000000000000000000000000000000100000000000000000000000000000;
301 6'b011110 : out = 64'b0000000000000000000000000000000001000000000000000000000000000000;
302 6'b011111 : out = 64'b0000000000000000000000000000000010000000000000000000000000000000;
303
304 6'b100000 : out = 64'b0000000000000000000000000000000100000000000000000000000000000000;
305 6'b100001 : out = 64'b0000000000000000000000000000001000000000000000000000000000000000;
306 6'b100010 : out = 64'b0000000000000000000000000000010000000000000000000000000000000000;
307 6'b100011 : out = 64'b0000000000000000000000000000100000000000000000000000000000000000;
308 6'b100100 : out = 64'b0000000000000000000000000001000000000000000000000000000000000000;
309 6'b100101 : out = 64'b0000000000000000000000000010000000000000000000000000000000000000;
310 6'b100110 : out = 64'b0000000000000000000000000100000000000000000000000000000000000000;
311 6'b100111 : out = 64'b0000000000000000000000001000000000000000000000000000000000000000;
312 6'b101000 : out = 64'b0000000000000000000000010000000000000000000000000000000000000000;
313 6'b101001 : out = 64'b0000000000000000000000100000000000000000000000000000000000000000;
314 6'b101010 : out = 64'b0000000000000000000001000000000000000000000000000000000000000000;
315 6'b101011 : out = 64'b0000000000000000000010000000000000000000000000000000000000000000;
316 6'b101100 : out = 64'b0000000000000000000100000000000000000000000000000000000000000000;
317 6'b101101 : out = 64'b0000000000000000001000000000000000000000000000000000000000000000;
318 6'b101110 : out = 64'b0000000000000000010000000000000000000000000000000000000000000000;
319 6'b101111 : out = 64'b0000000000000000100000000000000000000000000000000000000000000000;
320 6'b110000 : out = 64'b0000000000000001000000000000000000000000000000000000000000000000;
321 6'b110001 : out = 64'b0000000000000010000000000000000000000000000000000000000000000000;
322 6'b110010 : out = 64'b0000000000000100000000000000000000000000000000000000000000000000;
323 6'b110011 : out = 64'b0000000000001000000000000000000000000000000000000000000000000000;
324 6'b110100 : out = 64'b0000000000010000000000000000000000000000000000000000000000000000;
325 6'b110101 : out = 64'b0000000000100000000000000000000000000000000000000000000000000000;
326 6'b110110 : out = 64'b0000000001000000000000000000000000000000000000000000000000000000;
327 6'b110111 : out = 64'b0000000010000000000000000000000000000000000000000000000000000000;
328 6'b111000 : out = 64'b0000000100000000000000000000000000000000000000000000000000000000;
329 6'b111001 : out = 64'b0000001000000000000000000000000000000000000000000000000000000000;
330 6'b111010 : out = 64'b0000010000000000000000000000000000000000000000000000000000000000;
331 6'b111011 : out = 64'b0000100000000000000000000000000000000000000000000000000000000000;
332 6'b111100 : out = 64'b0001000000000000000000000000000000000000000000000000000000000000;
333 6'b111101 : out = 64'b0010000000000000000000000000000000000000000000000000000000000000;
334 6'b111110 : out = 64'b0100000000000000000000000000000000000000000000000000000000000000;
335 6'b111111 : out = 64'b1000000000000000000000000000000000000000000000000000000000000000;
336 endcase
337 end
338 endmodule
339
340
341 module MUX2(input [1:0] in, input select, output reg out);
342
343 always @( in or select)
344 case (select)
345 0: out = in[0];
346 1: out = in[1];
347 endcase
348 endmodule
349
350
351 module MUX4(input [3:0] in, input [1:0] select, output reg out);
352
353 always @( in or select)
354 case (select)
355 0: out = in[0];
356 1: out = in[1];
357 2: out = in[2];
358 3: out = in[3];
359 endcase
360 endmodule
361
362
363 module MUX8(input [7:0] in, input [2:0] select, output reg out);
364
365 always @( in or select)
366 case (select)
367 0: out = in[0];
368 1: out = in[1];
369 2: out = in[2];
370 3: out = in[3];
371 4: out = in[4];
372 5: out = in[5];
373 6: out = in[6];
374 7: out = in[7];
375 endcase
376 endmodule
377
378 module MUX16(input [15:0] in, input [3:0] select, output reg out);
379
380 always @( in or select)
381 case (select)
382 0: out = in[0];
383 1: out = in[1];
384 2: out = in[2];
385 3: out = in[3];
386 4: out = in[4];
387 5: out = in[5];
388 6: out = in[6];
389 7: out = in[7];
390 8: out = in[8];
391 9: out = in[9];
392 10: out = in[10];
393 11: out = in[11];
394 12: out = in[12];
395 13: out = in[13];
396 14: out = in[14];
397 15: out = in[15];
398 endcase
399 endmodule
400
401 module MUX32(input [31:0] in, input [4:0] select, output reg out);
402
403 always @( in or select)
404 case (select)
405 0: out = in[0];
406 1: out = in[1];
407 2: out = in[2];
408 3: out = in[3];
409 4: out = in[4];
410 5: out = in[5];
411 6: out = in[6];
412 7: out = in[7];
413 8: out = in[8];
414 9: out = in[9];
415 10: out = in[10];
416 11: out = in[11];
417 12: out = in[12];
418 13: out = in[13];
419 14: out = in[14];
420 15: out = in[15];
421 16: out = in[16];
422 17: out = in[17];
423 18: out = in[18];
424 19: out = in[19];
425 20: out = in[20];
426 21: out = in[21];
427 22: out = in[22];
428 23: out = in[23];
429 24: out = in[24];
430 25: out = in[25];
431 26: out = in[26];
432 27: out = in[27];
433 28: out = in[28];
434 29: out = in[29];
435 30: out = in[30];
436 31: out = in[31];
437 endcase
438 endmodule
439
440 module MUX64(input [63:0] in, input [5:0] select, output reg out);
441
442 always @( in or select)
443 case (select)
444 0: out = in[0];
445 1: out = in[1];
446 2: out = in[2];
447 3: out = in[3];
448 4: out = in[4];
449 5: out = in[5];
450 6: out = in[6];
451 7: out = in[7];
452 8: out = in[8];
453 9: out = in[9];
454 10: out = in[10];
455 11: out = in[11];
456 12: out = in[12];
457 13: out = in[13];
458 14: out = in[14];
459 15: out = in[15];
460 16: out = in[16];
461 17: out = in[17];
462 18: out = in[18];
463 19: out = in[19];
464 20: out = in[20];
465 21: out = in[21];
466 22: out = in[22];
467 23: out = in[23];
468 24: out = in[24];
469 25: out = in[25];
470 26: out = in[26];
471 27: out = in[27];
472 28: out = in[28];
473 29: out = in[29];
474 30: out = in[30];
475 31: out = in[31];
476 32: out = in[32];
477 33: out = in[33];
478 34: out = in[34];
479 35: out = in[35];
480 36: out = in[36];
481 37: out = in[37];
482 38: out = in[38];
483 39: out = in[39];
484 40: out = in[40];
485 41: out = in[41];
486 42: out = in[42];
487 43: out = in[43];
488 44: out = in[44];
489 45: out = in[45];
490 46: out = in[46];
491 47: out = in[47];
492 48: out = in[48];
493 49: out = in[49];
494 50: out = in[50];
495 51: out = in[51];
496 52: out = in[52];
497 53: out = in[53];
498 54: out = in[54];
499 55: out = in[55];
500 56: out = in[56];
501 57: out = in[57];
502 58: out = in[58];
503 59: out = in[59];
504 60: out = in[60];
505 61: out = in[61];
506 62: out = in[62];
507 63: out = in[63];
508 endcase
509 endmodule
510
511 module ADD1(input in1, in2, cin, output out, cout);
512
513 assign {cout, out} = in1 + in2 + cin;
514
515 endmodule
516
517 module ADD2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2,
518 input cin, output [SIZE-1:0] out, output cout);
519
520 assign {cout, out} = in1 + in2 + cin;
521
522 endmodule
523
524 module ADD4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2,
525 input cin, output [SIZE-1:0] out, output cout);
526
527 assign {cout, out} = in1 + in2 + cin;
528
529 endmodule
530
531 module ADD8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2,
532 input cin, output [SIZE-1:0] out, output cout);
533
534 assign {cout, out} = in1 + in2 + cin;
535
536 endmodule
537
538 module ADD16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2,
539 input cin, output [SIZE-1:0] out, output cout);
540
541 assign {cout, out} = in1 + in2 + cin;
542
543 endmodule
544
545 module ADD32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2,
546 input cin, output [SIZE-1:0] out, output cout);
547
548 assign {cout, out} = in1 + in2 + cin;
549
550 endmodule
551 module ADD64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2,
552 input cin, output [SIZE-1:0] out, output cout);
553
554 assign {cout, out} = in1 + in2 + cin;
555
556 endmodule
557
558 module SUB1(input in1, in2, cin, output out, cout);
559
560 assign {cout, out} = in1 - in2 - cin;
561
562 endmodule
563
564 module SUB2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2,
565 input cin, output [SIZE-1:0] out, output cout);
566
567 assign {cout, out} = in1 - in2 - cin;
568
569 endmodule
570
571 module SUB4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2,
572 input cin, output [SIZE-1:0] out, output cout);
573
574 assign {cout, out} = in1 - in2 - cin;
575
576 endmodule
577
578 module SUB8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2,
579 input cin, output [SIZE-1:0] out, output cout);
580
581 assign {cout, out} = in1 - in2 - cin;
582
583 endmodule
584
585 module SUB16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2,
586 input cin, output [SIZE-1:0] out, output cout);
587
588 assign {cout, out} = in1 - in2 - cin;
589
590 endmodule
591
592 module SUB32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2,
593 input cin, output [SIZE-1:0] out, output cout);
594
595 assign {cout, out} = in1 - in2 - cin;
596
597 endmodule
598 module SUB64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2,
599 input cin, output [SIZE-1:0] out, output cout);
600
601 assign {cout, out} = in1 - in2 - cin;
602
603 endmodule
604
605 module MUL1 #(parameter SIZE = 1)(input in1, in2, output [2*SIZE-1:0] out);
606
607 assign out = in1*in2;
608
609 endmodule
610
611 module MUL2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);
612
613 assign out = in1*in2;
614
615 endmodule
616
617 module MUL4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);
618
619 assign out = in1*in2;
620
621 endmodule
622
623 module MUL8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);
624
625 assign out = in1*in2;
626
627 endmodule
628
629 module MUL16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);
630
631 assign out = in1*in2;
632
633 endmodule
634
635 module MUL32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);
636
637 assign out = in1*in2;
638
639 endmodule
640
641 module MUL64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);
642
643 assign out = in1*in2;
644
645 endmodule
646
647 module DIV1 #(parameter SIZE = 1)(input in1, in2, output out, rem);
648
649 assign out = in1/in2;
650 assign rem = in1%in2;
651
652 endmodule
653
654 module DIV2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2,
655 output [SIZE-1:0] out, rem);
656
657 assign out = in1/in2;
658 assign rem = in1%in2;
659
660 endmodule
661
662 module DIV4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2,
663 output [SIZE-1:0] out, rem);
664
665 assign out = in1/in2;
666 assign rem = in1%in2;
667
668 endmodule
669
670 module DIV8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2,
671 output [SIZE-1:0] out, rem);
672
673 assign out = in1/in2;
674 assign rem = in1%in2;
675
676 endmodule
677
678 module DIV16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2,
679 output [SIZE-1:0] out, rem);
680
681 assign out = in1/in2;
682 assign rem = in1%in2;
683
684 endmodule
685
686 module DIV32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2,
687 output [SIZE-1:0] out, rem);
688
689 assign out = in1/in2;
690 assign rem = in1%in2;
691
692 endmodule
693
694 module DIV64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2,
695 output [SIZE-1:0] out, rem);
696
697 assign out = in1/in2;
698 assign rem = in1%in2;
699
700 endmodule
701
702 module FF (input d, clk, output reg q);
703 always @( posedge clk)
704 q <= d;
705 endmodule
706
707
708 module RFF(input d, clk, reset, output reg q);
709 always @(posedge clk or posedge reset)
710 if(reset)
711 q <= 0;
712 else
713 q <= d;
714 endmodule
715
716 module SFF(input d, clk, set, output reg q);
717 always @(posedge clk or posedge set)
718 if(set)
719 q <= 1;
720 else
721 q <= d;
722 endmodule
723
724 module RSFF(input d, clk, set, reset, output reg q);
725 always @(posedge clk or posedge reset or posedge set)
726 if(reset)
727 q <= 0;
728 else if(set)
729 q <= 1;
730 else
731 q <= d;
732 endmodule
733
734 module SRFF(input d, clk, set, reset, output reg q);
735 always @(posedge clk or posedge set or posedge reset)
736 if(set)
737 q <= 1;
738 else if(reset)
739 q <= 0;
740 else
741 q <= d;
742 endmodule
743
744 module LATCH(input d, enable, output reg q);
745 always @( d or enable)
746 if(enable)
747 q <= d;
748 endmodule
749
750 module RLATCH(input d, reset, enable, output reg q);
751 always @( d or enable or reset)
752 if(enable)
753 if(reset)
754 q <= 0;
755 else
756 q <= d;
757 endmodule
758
759 module LSHIFT1 #(parameter SIZE = 1)(input in, shift, val, output reg out);
760
761 always @ (in, shift, val) begin
762 if(shift)
763 out = val;
764 else
765 out = in;
766 end
767
768 endmodule
769
770
771 module LSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in,
772 input [SIZE-1:0] shift, input val,
773 output reg [SIZE-1:0] out);
774
775 always @(in or shift or val) begin
776 out = in << shift;
777 if(val)
778 out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
779 end
780 endmodule
781
782 module LSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in,
783 input [2:0] shift, input val, output reg [SIZE-1:0] out);
784
785 always @(in or shift or val) begin
786 out = in << shift;
787 if(val)
788 out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
789 end
790 endmodule
791
792
793 module LSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in,
794 input [3:0] shift, input val, output reg [SIZE-1:0] out);
795
796 always @(in or shift or val) begin
797 out = in << shift;
798 if(val)
799 out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
800 end
801 endmodule
802
803 module LSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in,
804 input [4:0] shift, input val, output reg [SIZE-1:0] out);
805
806 always @(in or shift or val) begin
807 out = in << shift;
808 if(val)
809 out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
810 end
811 endmodule
812
813 module LSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in,
814 input [5:0] shift, input val, output reg [SIZE-1:0] out);
815
816 always @(in or shift or val) begin
817 out = in << shift;
818 if(val)
819 out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
820 end
821 endmodule
822
823 module LSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in,
824 input [6:0] shift, input val, output reg [SIZE-1:0] out);
825
826 always @(in or shift or val) begin
827 out = in << shift;
828 if(val)
829 out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
830 end
831 endmodule
832
833 module RSHIFT1 #(parameter SIZE = 1)(input in, shift, val, output reg out);
834
835 always @ (in, shift, val) begin
836 if(shift)
837 out = val;
838 else
839 out = in;
840 end
841
842 endmodule
843
844 module RSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in,
845 input [SIZE-1:0] shift, input val,
846 output reg [SIZE-1:0] out);
847
848 always @(in or shift or val) begin
849 out = in >> shift;
850 if(val)
851 out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
852 end
853
854 endmodule
855
856
857 module RSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in,
858 input [2:0] shift, input val,
859 output reg [SIZE-1:0] out);
860
861 always @(in or shift or val) begin
862 out = in >> shift;
863 if(val)
864 out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
865 end
866 endmodule
867
868 module RSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in,
869 input [3:0] shift, input val,
870 output reg [SIZE-1:0] out);
871
872 always @(in or shift or val) begin
873 out = in >> shift;
874 if(val)
875 out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
876 end
877
878 endmodule
879
880 module RSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in,
881 input [4:0] shift, input val,
882 output reg [SIZE-1:0] out);
883
884 always @(in or shift or val) begin
885 out = in >> shift;
886 if(val)
887 out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
888 end
889 endmodule
890
891
892 module RSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in,
893 input [5:0] shift, input val,
894 output reg [SIZE-1:0] out);
895
896 always @(in or shift or val) begin
897 out = in >> shift;
898 if(val)
899 out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
900 end
901 endmodule
902
903 module RSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in,
904 input [6:0] shift, input val,
905 output reg [SIZE-1:0] out);
906
907 always @(in or shift or val) begin
908 out = in >> shift;
909 if(val)
910 out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
911 end
912 endmodule
913
914 module CMP1 #(parameter SIZE = 1) (input in1, in2,
915 output reg equal, unequal, greater, lesser);
916
917 always @ (in1 or in2) begin
918 if(in1 == in2) begin
919 equal = 1;
920 unequal = 0;
921 greater = 0;
922 lesser = 0;
923 end
924 else begin
925 equal = 0;
926 unequal = 1;
927
928 if(in1 < in2) begin
929 greater = 0;
930 lesser = 1;
931 end
932 else begin
933 greater = 1;
934 lesser = 0;
935 end
936 end
937 end
938 endmodule
939
940
941 module CMP2 #(parameter SIZE = 2) (input [SIZE-1:0] in1, in2,
942 output reg equal, unequal, greater, lesser);
943
944 always @ (in1 or in2) begin
945 if(in1 == in2) begin
946 equal = 1;
947 unequal = 0;
948 greater = 0;
949 lesser = 0;
950 end
951 else begin
952 equal = 0;
953 unequal = 1;
954
955 if(in1 < in2) begin
956 greater = 0;
957 lesser = 1;
958 end
959 else begin
960 greater = 1;
961 lesser = 0;
962 end
963 end
964 end
965 endmodule
966
967 module CMP4 #(parameter SIZE = 4) (input [SIZE-1:0] in1, in2,
968 output reg equal, unequal, greater, lesser);
969
970 always @ (in1 or in2) begin
971 if(in1 == in2) begin
972 equal = 1;
973 unequal = 0;
974 greater = 0;
975 lesser = 0;
976 end
977 else begin
978 equal = 0;
979 unequal = 1;
980
981 if(in1 < in2) begin
982 greater = 0;
983 lesser = 1;
984 end
985 else begin
986 greater = 1;
987 lesser = 0;
988 end
989 end
990 end
991 endmodule
992
993 module CMP8 #(parameter SIZE = 8) (input [SIZE-1:0] in1, in2,
994 output reg equal, unequal, greater, lesser);
995
996 always @ (in1 or in2) begin
997 if(in1 == in2) begin
998 equal = 1;
999 unequal = 0;
1000 greater = 0;
1001 lesser = 0;
1002 end
1003 else begin
1004 equal = 0;
1005 unequal = 1;
1006
1007 if(in1 < in2) begin
1008 greater = 0;
1009 lesser = 1;
1010 end
1011 else begin
1012 greater = 1;
1013 lesser = 0;
1014 end
1015 end
1016 end
1017 endmodule
1018
1019 module CMP16 #(parameter SIZE = 16) (input [SIZE-1:0] in1, in2,
1020 output reg equal, unequal, greater, lesser);
1021
1022 always @ (in1 or in2) begin
1023 if(in1 == in2) begin
1024 equal = 1;
1025 unequal = 0;
1026 greater = 0;
1027 lesser = 0;
1028 end
1029 else begin
1030 equal = 0;
1031 unequal = 1;
1032
1033 if(in1 < in2) begin
1034 greater = 0;
1035 lesser = 1;
1036 end
1037 else begin
1038 greater = 1;
1039 lesser = 0;
1040 end
1041 end
1042 end
1043 endmodule
1044
1045 module CMP32 #(parameter SIZE = 32) (input [SIZE-1:0] in1, in2,
1046 output reg equal, unequal, greater, lesser);
1047
1048 always @ (in1 or in2) begin
1049 if(in1 == in2) begin
1050 equal = 1;
1051 unequal = 0;
1052 greater = 0;
1053 lesser = 0;
1054 end
1055 else begin
1056 equal = 0;
1057 unequal = 1;
1058
1059 if(in1 < in2) begin
1060 greater = 0;
1061 lesser = 1;
1062 end
1063 else begin
1064 greater = 1;
1065 lesser = 0;
1066 end
1067 end
1068 end
1069 endmodule
1070
1071 module CMP64 #(parameter SIZE = 64) (input [SIZE-1:0] in1, in2,
1072 output reg equal, unequal, greater, lesser);
1073
1074 always @ (in1 or in2) begin
1075 if(in1 == in2) begin
1076 equal = 1;
1077 unequal = 0;
1078 greater = 0;
1079 lesser = 0;
1080 end
1081 else begin
1082 equal = 0;
1083 unequal = 1;
1084
1085 if(in1 < in2) begin
1086 greater = 0;
1087 lesser = 1;
1088 end
1089 else begin
1090 greater = 1;
1091 lesser = 0;
1092 end
1093 end
1094 end
1095 endmodule
1096
1097 module VCC (output supply1 out);
1098 endmodule
1099
1100 module GND (output supply0 out);
1101 endmodule
1102
1103
1104 module INC1 #(parameter SIZE = 1) (input in, output [SIZE:0] out);
1105
1106 assign out = in + 1;
1107
1108 endmodule
1109
1110 module INC2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output [SIZE:0] out);
1111
1112 assign out = in + 1;
1113
1114 endmodule
1115
1116 module INC4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output [SIZE:0] out);
1117 assign out = in + 1;
1118
1119 endmodule
1120
1121 module INC8 #(parameter SIZE = 8) (input [SIZE-1:0] in, output [SIZE:0] out);
1122 assign out = in + 1;
1123
1124 endmodule
1125
1126 module INC16 #(parameter SIZE = 16) (input [SIZE-1:0] in, output [SIZE:0] out);
1127 assign out = in + 1;
1128
1129 endmodule
1130
1131 module INC32 #(parameter SIZE = 32) (input [SIZE-1:0] in, output [SIZE:0] out);
1132 assign out = in + 1;
1133
1134 endmodule
1135 module INC64 #(parameter SIZE = 64) (input [SIZE-1:0] in, output [SIZE:0] out);
1136 assign out = in + 1;
1137
1138 endmodule
1139