tests/hana/test_intermout.v

   1
   2 // test_intermout_always_comb_1_test.v
   3 module f1_test(a, b, c, d, z);
   4 input a, b, c, d;
   5 output z;
   6 reg z, temp1, temp2;
   7
   8 always @(a or b or c or d)
   9 begin
  10     temp1 = a ^ b;
  11         temp2 = c ^ d;
  12         z = temp1 ^ temp2;
  13 end
  14
  15 endmodule
  16
  17 // test_intermout_always_comb_3_test.v
  18 module f2_test (in1, in2, out);
  19 input  in1, in2;
  20 output  reg out;
  21
  22 always @ ( in1 or in2)
  23         if(in1 > in2)
  24                 out = in1;
  25         else
  26                 out = in2;
  27 endmodule
  28
  29 // test_intermout_always_comb_4_test.v
  30 module f3_test(a, b, c);
  31 input b, c;
  32 output reg a;
  33
  34 always @(b or c) begin
  35 a = b;
  36 a = c;
  37 end
  38 endmodule
  39
  40 // test_intermout_always_comb_5_test.v
  41 module f4_test(ctrl, in1,  in2, out);
  42 input ctrl;
  43 input  in1, in2;
  44 output  reg out;
  45
  46 always @ (ctrl or in1 or in2)
  47         if(ctrl)
  48                 out = in1 & in2;
  49         else
  50                 out = in1 | in2;
  51 endmodule
  52
  53 // test_intermout_always_ff_3_test.v
  54 module f5_NonBlockingEx(clk, merge, er, xmit, fddi, claim);
  55 input clk, merge, er, xmit, fddi;
  56 output reg claim;
  57 reg fcr;
  58
  59 always @(posedge clk)
  60 begin
  61     fcr = er | xmit;
  62
  63         if(merge)
  64             claim = fcr & fddi;
  65         else
  66             claim = fddi;
  67 end
  68 endmodule
  69
  70 // test_intermout_always_ff_4_test.v
  71 module f6_FlipFlop(clk, cs, ns);
  72 input clk;
  73 input [31:0] cs;
  74 output [31:0] ns;
  75 integer is;
  76
  77 always @(posedge clk)
  78     is <= cs;
  79
  80 assign ns = is;
  81 endmodule
  82
  83 // test_intermout_always_ff_5_test.v
  84 module f7_FlipFlop(clock, cs, ns);
  85 input clock;
  86 input [3:0] cs;
  87 output reg [3:0] ns;
  88 reg [3:0] temp;
  89
  90 always @(posedge clock)
  91 begin
  92     temp = cs;
  93         ns = temp;
  94 end
  95
  96 endmodule
  97
  98 // test_intermout_always_ff_6_test.v
  99 module f8_inc(clock, counter);
 100
 101 input clock;
 102 output reg [3:0] counter;
 103 always @(posedge clock)
 104         counter <= counter + 1;
 105 endmodule
 106
 107 // test_intermout_always_ff_8_test.v
 108 module f9_NegEdgeClock(q, d, clk, reset);
 109 input d, clk, reset;
 110 output reg q;
 111
 112 always @(negedge clk or negedge reset)
 113     if(!reset)
 114             q <= 1'b0;
 115         else
 116         q <= d;
 117
 118 endmodule
 119
 120 // test_intermout_always_ff_9_test.v
 121 module f10_MyCounter (clock, preset, updown, presetdata, counter);
 122 input clock, preset, updown;
 123 input [1: 0] presetdata;
 124 output reg [1:0] counter;
 125
 126 always @(posedge clock)
 127     if(preset)
 128             counter <= presetdata;
 129         else
 130             if(updown)
 131                     counter <= counter + 1;
 132                 else
 133                     counter <= counter - 1;
 134 endmodule
 135
 136 // test_intermout_always_latch_1_test.v
 137 module f11_test(en, in, out);
 138 input en;
 139 input [1:0] in;
 140 output reg [2:0] out;
 141
 142 always @ (en or in)
 143         if(en)
 144                 out = in + 1;
 145 endmodule
 146
 147 // test_intermout_bufrm_1_test.v
 148 module f12_test(input in, output out);
 149 //no buffer removal
 150 assign out = in;
 151 endmodule
 152
 153 // test_intermout_bufrm_2_test.v
 154 module f13_test(input in, output out);
 155 //intermediate buffers should be removed
 156 wire w1, w2;
 157 assign w1 = in;
 158 assign w2 = w1;
 159 assign out = w2;
 160 endmodule
 161
 162 // test_intermout_bufrm_6_test.v
 163 module f14_test(in, out);
 164 input in;
 165 output out;
 166
 167 wire w1, w2, w3, w4;
 168 assign w1 = in;
 169 assign w2 = w1;
 170 assign w4 = w3;
 171 assign out = w4;
 172 f14_mybuf _f14_mybuf(w2, w3);
 173 endmodule
 174
 175 module f14_mybuf(in, out);
 176 input in;
 177 output out;
 178 wire w1, w2, w3, w4;
 179
 180 assign w1 = in;
 181 assign w2 = w1;
 182 assign out = w2;
 183 endmodule
 184
 185
 186 // test_intermout_bufrm_7_test.v
 187 module f15_test(in1, in2, out);
 188 input in1, in2;
 189 output out;
 190 // Y with cluster of f15_mybuf instances at the junction
 191
 192 wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10;
 193 assign w1 = in1;
 194 assign w2 = w1;
 195 assign w5 = in2;
 196 assign w6 = w5;
 197 assign w10 = w9;
 198 assign out = w10;
 199
 200 f15_mybuf _f15_mybuf0(w2, w3);
 201 f15_mybuf _f15_mybuf1(w3, w4);
 202
 203 f15_mybuf _f15_mybuf2(w6, w7);
 204 f15_mybuf _f15_mybuf3(w7, w4);
 205
 206 f15_mybuf _f15_mybuf4(w4, w8);
 207 f15_mybuf _f15_mybuf5(w8, w9);
 208 endmodule
 209
 210 module f15_mybuf(in, out);
 211 input in;
 212 output out;
 213 wire w1, w2, w3, w4;
 214
 215 assign w1 = in;
 216 assign w2 = w1;
 217 assign out = w2;
 218 endmodule
 219
 220
 221 // test_intermout_exprs_add_test.v
 222 module f16_test(out, in1, in2, vin1, vin2, vout1);
 223 output out;
 224 input in1, in2;
 225 input [1:0] vin1;
 226 input [2:0] vin2;
 227 output [3:0] vout1;
 228
 229 assign out = in1 + in2;
 230 assign vout1 = vin1 + vin2;
 231 endmodule
 232
 233 // test_intermout_exprs_binlogic_test.v
 234 module f17_test(in1, in2, vin1, vin2, out, vout, vin3, vin4, vout1 );
 235 input in1, in2;
 236 input [1:0] vin1;
 237 input [3:0] vin2;
 238 input [1:0] vin3;
 239 input [3:0] vin4;
 240 output vout, vout1;
 241 output out;
 242
 243 assign out = in1 && in2;
 244 assign vout = vin1 && vin2;
 245 assign vout1 = vin3 || vin4;
 246 endmodule
 247
 248 // test_intermout_exprs_bitwiseneg_test.v
 249 module f18_test(output out, input in, output [1:0] vout, input [1:0] vin);
 250
 251 assign out = ~in;
 252 assign vout = ~vin;
 253 endmodule
 254
 255 // test_intermout_exprs_buffer_test.v
 256 module f19_buffer(in, out, vin, vout);
 257 input  in;
 258 output out;
 259 input [1:0] vin;
 260 output [1:0] vout;
 261
 262 assign out = in;
 263 assign vout = vin;
 264 endmodule
 265
 266 // test_intermout_exprs_condexpr_mux_test.v
 267 module f20_test(in1, in2, out,  vin1, vin2, vin3, vin4, vout1, vout2, en1, ven1, ven2);
 268 input in1, in2, en1, ven1;
 269 input [1:0] ven2;
 270 output out;
 271 input [1:0] vin1,  vin2, vin3, vin4;
 272 output [1:0] vout1, vout2;
 273
 274 assign out = en1 ? in1 : in2;
 275 assign vout1 = ven1 ? vin1 : vin2;
 276 assign vout2 = ven2 ? vin3 : vin4;
 277 endmodule
 278
 279 // test_intermout_exprs_condexpr_tribuf_test.v
 280 module f21_test(in, out, en, vin1, vout1, en1);
 281 input in, en, en1;
 282 output out;
 283 input [1:0] vin1;
 284 output [1:0] vout1;
 285
 286 assign out = en ? in : 1'bz;
 287 assign vout1 = en1 ? vin1 : 2'bzz;
 288 endmodule
 289
 290 // test_intermout_exprs_constshift_test.v
 291 module f22_test(in, out, vin, vout, vin1, vout1, vin2, vout2);
 292
 293 input in;
 294 input [3:0] vin, vin1, vin2;
 295 output [3:0] vout, vout1, vout2;
 296 output out;
 297
 298 assign out = in << 1;
 299 assign vout = vin << 2;
 300 assign vout1 = vin1 >> 2;
 301 assign vout2 = vin2 >>> 2;
 302 endmodule
 303
 304 // test_intermout_exprs_const_test.v
 305 module f23_test (out, vout);
 306 output out;
 307 output [7:0] vout;
 308
 309 assign out = 1'b1;
 310 assign vout = 9;
 311 endmodule
 312
 313 // test_intermout_exprs_div_test.v
 314 module f24_test(out, in1, in2, vin1, vin2, vout1);
 315 output out;
 316 input in1, in2;
 317 input [1:0] vin1;
 318 input [2:0] vin2;
 319 output [3:0] vout1;
 320
 321 assign out = in1 / in2;
 322 assign vout1 = vin1 / vin2;
 323 endmodule
 324
 325 // test_intermout_exprs_logicneg_test.v
 326 module f25_test(out, vout, in, vin);
 327 output out, vout;
 328 input in;
 329 input [3:0] vin;
 330 assign out = !in;
 331 assign vout = !vin;
 332 endmodule
 333
 334 // test_intermout_exprs_mod_test.v
 335 module f26_test(out, in1, in2, vin1, vin2, vout1);
 336 output out;
 337 input in1, in2;
 338 input [1:0] vin1;
 339 input [2:0] vin2;
 340 output [3:0] vout1;
 341
 342 assign out = in1 % in2;
 343 assign vout1 = vin1 % vin2;
 344 endmodule
 345
 346 // test_intermout_exprs_mul_test.v
 347 module f27_test(out, in1, in2, vin1, vin2, vout1);
 348 output out;
 349 input in1, in2;
 350 input [1:0] vin1;
 351 input [2:0] vin2;
 352 output [3:0] vout1;
 353
 354 assign out = in1 * in2;
 355 assign vout1 = vin1 * vin2;
 356 endmodule
 357
 358 // test_intermout_exprs_redand_test.v
 359 module f28_test(output out, input [1:0] vin, output out1, input [3:0] vin1);
 360
 361 assign out = &vin;
 362 assign out1 = &vin1;
 363 endmodule
 364
 365 // test_intermout_exprs_redop_test.v
 366 module f29_Reduction (A1, A2, A3, A4, A5, A6, Y1, Y2, Y3, Y4, Y5, Y6);
 367 input [1:0] A1;
 368 input [1:0] A2;
 369 input [1:0] A3;
 370 input [1:0] A4;
 371 input [1:0] A5;
 372 input [1:0] A6;
 373 output Y1, Y2, Y3, Y4, Y5, Y6;
 374 //reg Y1, Y2, Y3, Y4, Y5, Y6;
 375 assign Y1=&A1; //reduction AND
 376 assign Y2=|A2; //reduction OR
 377 assign Y3=~&A3; //reduction NAND
 378 assign Y4=~|A4; //reduction NOR
 379 assign Y5=^A5; //reduction XOR
 380 assign Y6=~^A6; //reduction XNOR
 381 endmodule
 382
 383 // test_intermout_exprs_sub_test.v
 384 module f30_test(out, in1, in2, vin1, vin2, vout1);
 385 output out;
 386 input in1, in2;
 387 input [1:0] vin1;
 388 input [2:0] vin2;
 389 output [3:0] vout1;
 390
 391 assign out = in1 - in2;
 392 assign vout1 = vin1 - vin2;
 393 endmodule
 394
 395 // test_intermout_exprs_unaryminus_test.v
 396 module f31_test(output out, input in, output [31:0] vout, input [31:0] vin);
 397
 398 assign out = -in;
 399 assign vout = -vin;
 400 endmodule
 401
 402 // test_intermout_exprs_unaryplus_test.v
 403 module f32_test(output out, input in);
 404
 405 assign out = +in;
 406 endmodule
 407
 408 // test_intermout_exprs_varshift_test.v
 409 module f33_test(vin0, vout0);
 410 input [2:0] vin0;
 411 output reg [7:0] vout0;
 412
 413 wire [7:0] myreg0, myreg1, myreg2;
 414 integer i;
 415 assign myreg0 = vout0 << vin0;
 416
 417 assign myreg1 = myreg2 >> i;
 418 endmodule