2 // test_parse2synthtrans_behavopt_1_test.v
3 module f1_test(in, out, clk, reset);
13 always @(clk or reset) begin
26 // test_parse2synthtrans_case_1_test.v
27 module f2_demultiplexer1_to_4 (out0, out1, out2, out3, in, s1, s0);
28 output out0, out1, out2, out3;
29 reg out0, out1, out2, out3;
34 always @(encoding) begin
46 always @(encoding) begin
54 // test_parse2synthtrans_contassign_1_test.v
55 module f3_test(in, out);
63 // test_parse2synthtrans_module_basic0_test.v
67 // test_parse2synthtrans_operators_1_test.v
68 module f5_test(in, out);
80 // test_parse2synthtrans_param_1_test.v
81 module f6_test(in, out);
89 // test_parse2synthtrans_port_scalar_1_test.v
90 module f7_test(in, out, io);
97 // test_parse2synthtrans_port_vector_1_test.v
98 module f8_test(in1, in2, out1, out2, io1, io2);
108 // test_parse2synthtrans_v2k_comb_logic_sens_list_test.v
109 module f9_test(q, d, clk, reset);
113 always @ (posedge clk, negedge reset)