tests/hana/test_parse2synthtrans.v

   1
   2 // test_parse2synthtrans_behavopt_1_test.v
   3 module f1_test(in, out, clk, reset);
   4 input in, reset;
   5 output reg out;
   6 input clk;
   7 reg signed [3:0] a;
   8 reg signed [3:0] b;
   9 reg signed [3:0] c;
  10 reg [5:0] d;
  11 reg [5:0] e;
  12
  13 always @(clk or reset) begin
  14     a = -4;
  15     b = 2;
  16     c = a + b;
  17     d = a + b + c;
  18     d = d*d;
  19     if(b)
  20         e = d*d;
  21     else
  22         e = d + d;
  23 end
  24 endmodule
  25
  26 // test_parse2synthtrans_case_1_test.v
  27 module f2_demultiplexer1_to_4 (out0, out1, out2, out3, in, s1, s0);
  28 output out0, out1, out2, out3;
  29 reg out0, out1, out2, out3;
  30 input in;
  31 input s1, s0;
  32 reg [3:0] encoding;
  33 reg [1:0] state;
  34    always @(encoding) begin
  35         case (encoding)
  36         4'bxx11: state = 1;
  37         4'bx0xx: state = 3;
  38         4'b11xx: state = 4;
  39         4'bx1xx: state = 2;
  40         4'bxx1x: state = 1;
  41         4'bxxx1: state = 0;
  42         default: state = 0;
  43         endcase
  44    end
  45
  46    always @(encoding) begin
  47         case (encoding)
  48         4'b0000: state = 1;
  49         default: state = 0;
  50         endcase
  51    end
  52 endmodule
  53
  54 // test_parse2synthtrans_contassign_1_test.v
  55 module f3_test(in, out);
  56
  57 input wire in;
  58 output  out;
  59 assign out = (in+in);
  60 assign out = 74;
  61 endmodule
  62
  63 // test_parse2synthtrans_module_basic0_test.v
  64 module f4_test;
  65 endmodule
  66
  67 // test_parse2synthtrans_operators_1_test.v
  68 module f5_test(in, out);
  69 input in;
  70 output out;
  71 parameter p1 = 10;
  72 parameter p2 = 5;
  73
  74 assign out = +p1;
  75 assign out = -p2;
  76 assign out = p1 + p2;
  77 assign out = p1 - p2;
  78 endmodule
  79
  80 // test_parse2synthtrans_param_1_test.v
  81 module f6_test(in, out);
  82 input in;
  83 output out;
  84 parameter p = 10;
  85
  86 assign out = p;
  87 endmodule
  88
  89 // test_parse2synthtrans_port_scalar_1_test.v
  90 module f7_test(in, out, io);
  91 inout io;
  92 output out;
  93 input in;
  94
  95 endmodule
  96
  97 // test_parse2synthtrans_port_vector_1_test.v
  98 module f8_test(in1, in2, out1, out2, io1, io2);
  99 inout [1:0] io1;
 100 inout [0:1] io2;
 101 output [1:0] out1;
 102 output [0:1] out2;
 103 input [1:0] in1;
 104 input [0:1] in2;
 105
 106 endmodule
 107
 108 // test_parse2synthtrans_v2k_comb_logic_sens_list_test.v
 109 module f9_test(q, d, clk, reset);
 110 output reg q;
 111 input d, clk, reset;
 112
 113 always @ (posedge clk, negedge reset)
 114         if(!reset) q <= 0;
 115         else q <= d;
 116
 117 endmodule