tests/hana/test_parser.v

   1
   2 // test_parser_constructs_module_basic1_test.v
   3 module f1_test;
   4 endmodule
   5
   6 // test_parser_constructs_param_basic0_test.v
   7 module f2_test #( parameter v2kparam = 5)
   8 (in, out, io, vin, vout, vio);
   9 input in;
  10 output out;
  11 inout io;
  12 input [3:0] vin;
  13 output [v2kparam:0] vout;
  14 inout [0:3] vio;
  15 parameter myparam = 10;
  16 endmodule
  17
  18 // test_parser_constructs_port_basic0_test.v
  19 module f3_test(in, out, io, vin, vout, vio);
  20 input in;
  21 output out;
  22 inout io;
  23 input [3:0] vin;
  24 output [3:0] vout;
  25 inout [0:3] vio;
  26 endmodule
  27
  28 // test_parser_directives_define_simpledef_test.v
  29 `define parvez ahmad
  30 `define  WIRE wire
  31 `define TEN 10
  32
  33 module f4_`parvez();
  34 parameter param = `TEN;
  35 `WIRE w;
  36 assign w = `TEN;
  37 endmodule
  38
  39 // test_parser_misc_operators_test.v
  40 module f5_test(out, i0, i1, i2, i3, s1, s0);
  41 output out;
  42 input i0, i1, i2, i3;
  43 input s1, s0;
  44
  45 assign out = (~s1 & s0 & i0) |
  46                          (~s1 & s0 & i1) |
  47                          (s1 & ~s0 & i2) |
  48                          (s1 & s0 & i3);
  49
  50 endmodule
  51
  52 module f5_ternaryop(out, i0, i1, i2, i3, s1, s0);
  53 output out;
  54 input i0, i1, i2, i3;
  55 input s1, s0;
  56
  57 assign out = s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0);
  58
  59 endmodule
  60
  61 module f5_fulladd4(sum, c_out, a, b, c_in);
  62 output [3:0] sum;
  63 output c_out;
  64 input [3:0] a, b;
  65 input c_in;
  66
  67 assign {c_out, sum} = a + b + c_in;
  68 endmodule
  69
  70 // test_parser_v2k_comb_port_data_type_test.v
  71 module f6_adder(sum , co, a, b, ci);
  72 output  reg             [31:0]  sum;
  73 output  reg                             co;
  74 input   wire    [31:0]  a, b;
  75 input wire                              ci;
  76 endmodule
  77
  78 // test_parser_v2k_comma_sep_sens_list_test.v
  79 module f7_test(q, d, clk, reset);
  80 output reg q;
  81 input d, clk, reset;
  82
  83 always @ (posedge clk, negedge reset)
  84         if(!reset) q <= 0;
  85         else q <= d;
  86
  87 endmodule