tests/hana/test_simulation_always.v

   1
   2 // test_simulation_always_15_test.v
   3 module f1_test(input [1:0] in, output reg [1:0] out);
   4
   5 always @(in)
   6     out = in;
   7 endmodule
   8
   9 // test_simulation_always_17_test.v
  10 module f2_test(a, b, c, d, z);
  11 input a, b, c, d;
  12 output z;
  13 reg z, temp1, temp2;
  14
  15 always @(a or b or c or d)
  16 begin
  17     temp1 = a ^ b;
  18         temp2 = c ^ d;
  19         z = temp1 ^ temp2;
  20 end
  21
  22 endmodule
  23
  24 // test_simulation_always_18_test.v
  25 module f3_test (in1, in2, out);
  26 input  in1, in2;
  27 output  reg out;
  28
  29 always @ ( in1 or in2)
  30         if(in1 > in2)
  31                 out = in1;
  32         else
  33                 out = in2;
  34 endmodule
  35
  36 // test_simulation_always_19_test.v
  37 module f4_test(ctrl, in1,  in2, out);
  38 input ctrl;
  39 input  in1, in2;
  40 output  reg out;
  41
  42 always @ (ctrl or in1 or in2)
  43         if(ctrl)
  44                 out = in1 & in2;
  45         else
  46                 out = in1 | in2;
  47 endmodule
  48
  49 // test_simulation_always_1_test.v
  50 module f5_test(input in, output reg out);
  51
  52 always @(in)
  53     out = in;
  54 endmodule
  55
  56 // test_simulation_always_20_test.v
  57 module f6_NonBlockingEx(clk, merge, er, xmit, fddi, claim);
  58 input clk, merge, er, xmit, fddi;
  59 output reg claim;
  60 reg fcr;
  61
  62 always @(posedge clk)
  63 begin
  64     fcr <= er | xmit;
  65
  66         if(merge)
  67             claim <= fcr & fddi;
  68         else
  69             claim <= fddi;
  70 end
  71 endmodule
  72
  73 // test_simulation_always_21_test.v
  74 module f7_FlipFlop(clk, cs, ns);
  75 input clk;
  76 input [7:0] cs;
  77 output [7:0] ns;
  78 integer is;
  79
  80 always @(posedge clk)
  81     is <= cs;
  82
  83 assign ns = is;
  84 endmodule
  85
  86 // test_simulation_always_22_test.v
  87 module f8_inc(clock, counter);
  88
  89 input clock;
  90 output reg [7:0] counter;
  91 always @(posedge clock)
  92         counter <= counter + 1;
  93 endmodule
  94
  95 // test_simulation_always_23_test.v
  96 module f9_MyCounter (clock, preset, updown, presetdata, counter);
  97 input clock, preset, updown;
  98 input [1: 0] presetdata;
  99 output reg [1:0] counter;
 100
 101 always @(posedge clock)
 102     if(preset)
 103             counter <= presetdata;
 104         else
 105             if(updown)
 106                     counter <= counter + 1;
 107                 else
 108                     counter <= counter - 1;
 109 endmodule
 110
 111 // test_simulation_always_27_test.v
 112 module f10_FlipFlop(clock, cs, ns);
 113 input clock;
 114 input cs;
 115 output reg ns;
 116 reg temp;
 117
 118 always @(posedge clock)
 119 begin
 120     temp <= cs;
 121         ns <= temp;
 122 end
 123
 124 endmodule
 125
 126 // test_simulation_always_29_test.v
 127 module f11_test(input in, output reg [1:0] out);
 128
 129     always @(in)
 130     begin
 131         out = in;
 132         out = out + in;
 133     end
 134
 135 endmodule