Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig
[yosys.git] / tests / hana / test_simulation_inc.v
1
2 // test_simulation_inc_16_test.v
3 module f1_test(input [15:0] in, output [15:0] out);
4
5 assign out = -in;
6
7 endmodule
8
9 // test_simulation_inc_1_test.v
10 module f2_test(input in, output out);
11
12 assign out = -in;
13
14 endmodule
15
16 // test_simulation_inc_2_test.v
17 module f3_test(input [1:0] in, output [1:0] out);
18
19 assign out = -in;
20
21 endmodule
22
23 // test_simulation_inc_32_test.v
24 module f4_test(input [31:0] in, output [31:0] out);
25
26 assign out = -in;
27
28 endmodule
29
30 // test_simulation_inc_4_test.v
31 module f5_test(input [3:0] in, output [3:0] out);
32
33 assign out = -in;
34
35 endmodule
36
37 // test_simulation_inc_8_test.v
38 module f6_test(input [7:0] in, output [7:0] out);
39
40 assign out = -in;
41
42 endmodule