tests/hana/test_simulation_seq.v

   1
   2 // test_simulation_seq_ff_1_test.v
   3 module f1_test(input in,  input clk, output reg out);
   4 always @(posedge clk)
   5     out <= in;
   6 endmodule
   7
   8 // test_simulation_seq_ff_2_test.v
   9 module f2_test(input  in,  input clk,  output reg out);
  10 always @(negedge clk)
  11    out <= in;
  12 endmodule