Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig
[yosys.git] / tests / hana / test_simulation_shifter.v
1
2 // test_simulation_shifter_left_16_test.v
3 module f1_test(input [15:0] IN, input [4:0] SHIFT, output [15:0] OUT);
4
5 assign OUT = IN << SHIFT;
6 endmodule
7
8 // test_simulation_shifter_left_32_test.v
9 module f2_test(input [31:0] IN, input [5:0] SHIFT, output [31:0] OUT);
10
11 assign OUT = IN << SHIFT;
12 endmodule
13
14 // test_simulation_shifter_left_4_test.v
15 module f3_test(input [3:0] IN, input [2:0] SHIFT, output [3:0] OUT);
16
17 assign OUT = IN << SHIFT;
18 endmodule
19
20 // test_simulation_shifter_left_64_test.v
21 module f4_test(input [63:0] IN, input [6:0] SHIFT, output [63:0] OUT);
22
23 assign OUT = IN << SHIFT;
24 endmodule
25
26 // test_simulation_shifter_left_8_test.v
27 module f5_test(input [7:0] IN, input [3:0] SHIFT, output [7:0] OUT);
28
29 assign OUT = IN << SHIFT;
30 endmodule
31
32 // test_simulation_shifter_right_16_test.v
33 module f6_test(input [15:0] IN, input [4:0] SHIFT, output [15:0] OUT);
34
35 assign OUT = IN >> SHIFT;
36 endmodule
37
38 // test_simulation_shifter_right_32_test.v
39 module f7_test(input [31:0] IN, input [5:0] SHIFT, output [31:0] OUT);
40
41 assign OUT = IN >> SHIFT;
42 endmodule
43
44 // test_simulation_shifter_right_4_test.v
45 module f8_test(input [3:0] IN, input [2:0] SHIFT, output [3:0] OUT);
46
47 assign OUT = IN >> SHIFT;
48 endmodule
49
50 // test_simulation_shifter_right_64_test.v
51 module f9_test(input [63:0] IN, input [6:0] SHIFT, output [63:0] OUT);
52
53 assign OUT = IN >> SHIFT;
54 endmodule
55
56 // test_simulation_shifter_right_8_test.v
57 module f10_test(input [7:0] IN, input [3:0] SHIFT, output [7:0] OUT);
58
59 assign OUT = IN >> SHIFT;
60 endmodule