Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig
[yosys.git] / tests / hana / test_simulation_sop.v
1
2 // test_simulation_sop_basic_10_test.v
3 module f1_test(input [1:0] in, input select, output reg out);
4
5 always @( in or select)
6 case (select)
7 0: out = in[0];
8 1: out = in[1];
9 endcase
10 endmodule
11
12 // test_simulation_sop_basic_11_test.v
13 module f2_test(input [3:0] in, input [1:0] select, output reg out);
14
15 always @( in or select)
16 case (select)
17 0: out = in[0];
18 1: out = in[1];
19 2: out = in[2];
20 3: out = in[3];
21 endcase
22 endmodule
23
24 // test_simulation_sop_basic_12_test.v
25 module f3_test(input [7:0] in, input [2:0] select, output reg out);
26
27 always @( in or select)
28 case (select)
29 0: out = in[0];
30 1: out = in[1];
31 2: out = in[2];
32 3: out = in[3];
33 4: out = in[4];
34 5: out = in[5];
35 6: out = in[6];
36 7: out = in[7];
37 endcase
38 endmodule
39
40 // test_simulation_sop_basic_18_test.v
41 module f4_test(input [7:0] in, output out);
42
43 assign out = ~^in;
44
45 endmodule
46
47 // test_simulation_sop_basic_3_test.v
48 module f5_test(input in, output out);
49 assign out = ~in;
50 endmodule
51
52 // test_simulation_sop_basic_7_test.v
53 module f6_test(input in, output out);
54 assign out = in;
55 endmodule
56
57 // test_simulation_sop_basic_8_test.v
58 module f7_test(output out);
59 assign out = 1'b0;
60 endmodule
61
62 // test_simulation_sop_basic_9_test.v
63 module f8_test(input in, output out);
64 assign out = ~in;
65 endmodule