tests/hana/test_simulation_techmap_tech.v

   1
   2 // test_simulation_techmap_and_19_tech.v
   3 module f1_TECH_AND18(input [17:0] in, output out);
   4 assign out = &in;
   5 endmodule
   6
   7 module f1_TECH_AND4(input [3:0] in, output out);
   8 assign out = &in;
   9 endmodule
  10
  11 // test_simulation_techmap_and_5_tech.v
  12 module f2_TECH_AND5(input [4:0] in, output out);
  13 assign out = &in;
  14 endmodule
  15
  16 // test_simulation_techmap_nand_19_tech.v
  17 module f3_TECH_NAND18(input [17:0] in, output out);
  18 assign out = ~(&in);
  19 endmodule
  20
  21 module f3_TECH_NAND4(input [3:0] in, output out);
  22 assign out = ~(&in);
  23 endmodule
  24
  25 module f3_TECH_NAND2(input [1:0] in, output out);
  26 assign out = ~(&in);
  27 endmodule
  28
  29 // test_simulation_techmap_nand_2_tech.v
  30 module f4_TECH_NAND18(input [17:0] in, output out);
  31 assign out = ~(&in);
  32 endmodule
  33
  34 module f4_TECH_NAND4(input [3:0] in, output out);
  35 assign out = ~(&in);
  36 endmodule
  37
  38 module f4_TECH_NAND2(input [1:0] in, output out);
  39 assign out = ~(&in);
  40 endmodule
  41
  42 // test_simulation_techmap_nand_5_tech.v
  43 module f5_TECH_NAND18(input [17:0] in, output out);
  44 assign out = ~(&in);
  45 endmodule
  46
  47 module f5_TECH_NAND4(input [3:0] in, output out);
  48 assign out = ~(&in);
  49 endmodule
  50
  51 module f5_TECH_NAND2(input [1:0] in, output out);
  52 assign out = ~(&in);
  53 endmodule
  54
  55 // test_simulation_techmap_nor_19_tech.v
  56 module f6_TECH_NOR18(input [17:0] in, output out);
  57 assign out = ~(|in);
  58 endmodule
  59
  60 module f6_TECH_NOR4(input [3:0] in, output out);
  61 assign out = ~(|in);
  62 endmodule
  63
  64 module f6_TECH_NOR2(input [1:0] in, output out);
  65 assign out = ~(|in);
  66 endmodule
  67
  68 // test_simulation_techmap_nor_2_tech.v
  69 module f7_TECH_NOR18(input [17:0] in, output out);
  70 assign out = ~(|in);
  71 endmodule
  72
  73 module f7_TECH_NOR4(input [3:0] in, output out);
  74 assign out = ~(|in);
  75 endmodule
  76
  77 module f7_TECH_NOR2(input [1:0] in, output out);
  78 assign out = ~(|in);
  79 endmodule
  80
  81 // test_simulation_techmap_nor_5_tech.v
  82 module f8_TECH_NOR18(input [17:0] in, output out);
  83 assign out = ~(|in);
  84 endmodule
  85
  86 module f8_TECH_NOR4(input [3:0] in, output out);
  87 assign out = ~(|in);
  88 endmodule
  89
  90 module f8_TECH_NOR2(input [1:0] in, output out);
  91 assign out = ~(|in);
  92 endmodule
  93
  94 // test_simulation_techmap_or_19_tech.v
  95 module f9_TECH_OR18(input [17:0] in, output out);
  96 assign out = |in;
  97 endmodule
  98
  99 module f9_TECH_OR4(input [3:0] in, output out);
 100 assign out = |in;
 101 endmodule
 102
 103 // test_simulation_techmap_or_5_tech.v
 104 module f10_TECH_OR5(input [4:0] in, output out);
 105 assign out = |in;
 106 endmodule
 107
 108 // test_simulation_techmap_xnor_2_tech.v
 109 module f11_TECH_XOR5(input [4:0] in, output out);
 110 assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
 111 endmodule
 112 module f11_TECH_XOR2(input [1:0] in, output out);
 113 assign out = in[0] ^ in[1];
 114 endmodule
 115
 116 // test_simulation_techmap_xnor_5_tech.v
 117 module f12_TECH_XOR5(input [4:0] in, output out);
 118 assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
 119 endmodule
 120 module f12_TECH_XOR2(input [1:0] in, output out);
 121 assign out = in[0] ^ in[1];
 122 endmodule
 123
 124 // test_simulation_techmap_xor_19_tech.v
 125 module f13_TECH_XOR2(input [1:0] in, output out);
 126 assign out = in[0] ^ in[1];
 127 endmodule
 128
 129 // test_simulation_techmap_xor_2_tech.v
 130 module f14_TECH_XOR5(input [4:0] in, output out);
 131 assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
 132 endmodule
 133 module f14_TECH_XOR2(input [1:0] in, output out);
 134 assign out = in[0] ^ in[1];
 135 endmodule
 136
 137 // test_simulation_techmap_xor_5_tech.v
 138 module f15_TECH_XOR5(input [4:0] in, output out);
 139 assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
 140 endmodule
 141 module f15_TECH_XOR2(input [1:0] in, output out);
 142 assign out = in[0] ^ in[1];
 143 endmodule