tests/hana/test_simulation_vlib.v

   1 // test_simulation_mod_1_xx.v
   2 module f1_test(in1, in2, out);
   3 input in1;
   4 input in2;
   5 output out;
   6
   7 wire  synth_net_0;
   8 wire  synth_net_1;
   9 BUF synth_BUF_0(.in(synth_net_1), .out(out
  10     ));
  11 DIV1 synth_DIV(.in1(in1), .in2(in2), .rem(synth_net_0), .out(synth_net_1
  12     ));
  13 endmodule
  14
  15 // test_simulation_always_31_tt.v
  16 module f2_test(clk, cond, data);
  17 input cond;
  18 input clk;
  19 output data;
  20
  21 wire  synth_net;
  22 wire  synth_net_0;
  23 wire  synth_net_1;
  24 wire  synth_net_2;
  25
  26 wire  synth_net_3;
  27 wire  synth_net_4;
  28 wire  synth_net_5;
  29 wire  synth_net_6;
  30
  31 wire  synth_net_7;
  32 wire  synth_net_8;
  33 wire  synth_net_9;
  34 wire  synth_net_10;
  35
  36 wire  synth_net_11;
  37 wire  tmp;
  38 AND2 synth_AND(.in({synth_net_0, synth_net_1}), .
  39     out(synth_net_2));
  40 AND2 synth_AND_0(.in({synth_net_3, synth_net_4}), .out(
  41     synth_net_5));
  42 AND2 synth_AND_1(.in({synth_net_6, synth_net_7}), .out(
  43     synth_net_8));
  44 AND2 synth_AND_2(.in({synth_net_9, synth_net_10}), .out(
  45     synth_net_11));
  46 BUF synth_BUF(.in(synth_net), .out(synth_net_0));
  47 BUF
  48     synth_BUF_0(.in(data), .out(synth_net_3));
  49 BUF synth_BUF_1(.in(synth_net_8)
  50     , .out(tmp));
  51 BUF synth_BUF_2(.in(tmp), .out(synth_net_9));
  52 MUX2 synth_MUX(.
  53     in({synth_net_2, synth_net_5}), .select(cond), .out(synth_net_6));
  54 MUX2
  55     synth_MUX_0(.in({synth_net_1, synth_net_4}), .select(cond), .out(synth_net_7
  56     ));
  57 FF synth_FF(.d(synth_net_11), .clk(clk), .q(data));
  58 VCC synth_VCC(.out(
  59     synth_net));
  60 VCC synth_VCC_0(.out(synth_net_1));
  61 VCC synth_VCC_1(.out(
  62     synth_net_4));
  63 VCC synth_VCC_2(.out(synth_net_10));
  64 endmodule
  65