tests/ice40/dpram_tb.v

   1 module testbench;
   2     reg clk;
   3
   4     initial begin
   5        //  $dumpfile("testbench.vcd");
   6        //  $dumpvars(0, testbench);
   7
   8         #5 clk = 0;
   9         repeat (10000) begin
  10             #5 clk = 1;
  11             #5 clk = 0;
  12         end
  13     end
  14
  15
  16     reg [7:0] data_a = 0;
  17         reg [7:0] addr_a = 0;
  18         reg [7:0] addr_b = 0;
  19     reg we_a = 0;
  20     reg re_a = 1;
  21         wire [7:0] q_a;
  22         reg mem_init = 0;
  23
  24         reg [7:0] pq_a;
  25
  26     always @(posedge clk) begin
  27     #3;
  28     data_a <= data_a + 17;
  29
  30     addr_a <= addr_a + 1;
  31     addr_b <= addr_b + 1;
  32     end
  33
  34     always @(posedge addr_a) begin
  35     #10;
  36         if(addr_a > 6'h3E)
  37             mem_init <= 1;
  38     end
  39
  40         always @(posedge clk) begin
  41     //#3;
  42     we_a <= !we_a;
  43     end
  44
  45     reg [7:0] mem [(1<<8)-1:0];
  46
  47     always @(posedge clk) // Write memory.
  48         begin
  49         if (we_a)
  50         mem[addr_a] <= data_a; // Using write address bus.
  51         end
  52         always @(posedge clk) // Read memory.
  53         begin
  54         pq_a <= mem[addr_b]; // Using read address bus.
  55         end
  56
  57         top uut (
  58                 .din(data_a),
  59                 .write_en(we_a),
  60                 .waddr(addr_a),
  61                 .wclk(clk),
  62                 .raddr(addr_b),
  63                 .rclk(clk),
  64                 .dout(q_a)
  65                 );
  66
  67         uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a));
  68
  69 endmodule
  70
  71 module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B);
  72     always @(posedge clk)
  73     begin
  74         #1;
  75         if (en == 1 & init == 1 & A !== B)
  76         begin
  77             $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
  78             $stop;
  79         end
  80     end
  81 endmodule