tests/ice40/memory.ys

   1 read_verilog memory.v
   2 hierarchy -top top
   3 proc
   4 memory -nomap
   5 equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
   6 memory
   7 opt -full
   8
   9 miter -equiv -flatten -make_assert -make_outputs gold gate miter
  10 sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
  11
  12 design -load postopt
  13 cd top
  14 select -assert-count 1 t:SB_RAM40_4K
  15 select -assert-none t:SB_RAM40_4K %% t:* %D