tests/liberty/busdef.lib

   1 /********************************************/
   2 /*                                          */
   3 /* Supergate cell library for Bench marking */
   4 /*                                          */
   5 /* Symbiotic EDA GmbH / Moseley Instruments */
   6 /* Niels A. Moseley                         */
   7 /*                                          */
   8 /* Process: none                            */
   9 /*                                          */
  10 /* Date   : 02-11-2018                      */
  11 /* Version: 1.0                             */
  12 /*                                          */
  13 /********************************************/
  14
  15 library(supergate) {
  16   technology (cmos);
  17   revision : 1.0;
  18
  19   time_unit                     : "1ps";
  20   pulling_resistance_unit       : "1kohm";
  21   voltage_unit                  : "1V";
  22   current_unit                  : "1uA";
  23
  24   capacitive_load_unit(1,ff);
  25
  26   default_inout_pin_cap         :  7.0;
  27   default_input_pin_cap         :  7.0;
  28   default_output_pin_cap        :  0.0;
  29   default_fanout_load           :  1.0;
  30
  31   default_wire_load_capacitance : 0.1;
  32   default_wire_load_resistance  : 1.0e-3;
  33   default_wire_load_area        : 0.0;
  34
  35   nom_process                   :  1.0;
  36   nom_temperature               : 25.0;
  37   nom_voltage                   :  1.2;
  38
  39   delay_model                   : generic_cmos;
  40
  41     type( IO_bus_3_to_0 ) {
  42         base_type : array ;
  43         data_type : bit ;
  44         bit_width : 4;
  45         bit_from : 3 ;
  46         bit_to : 0 ;
  47         downto : true ;
  48     }
  49
  50     cell (SRAM) {
  51         area : 1 ;
  52         memory() {
  53             type : ram;
  54             address_width : 4;
  55             word_width : 4;
  56         }
  57         pin(CE1) {
  58             direction : input;
  59             capacitance : 0.021;
  60             max_transition : 1.024;
  61             switch_pin : true;
  62         }
  63         bus(I1)  {
  64             bus_type : IO_bus_3_to_0 ;
  65             direction : input;
  66             pin (I1[3:0]) {
  67                 timing() {
  68                     related_pin :   "CE1" ;
  69                     timing_type : setup_rising ;
  70                     rise_constraint (scalar) {
  71                         values("0.0507786");
  72                     }
  73                     fall_constraint (scalar) {
  74                         values("0.0507786");
  75                     }
  76                 }
  77             }
  78         }
  79     }
  80
  81 } /* end */