1 /********************************************/
3 /* Supergate cell library for Bench marking */
5 /* Symbiotic EDA GmbH / Moseley Instruments */
10 /* Date : 02-11-2018 */
13 /********************************************/
20 pulling_resistance_unit : "1kohm";
24 capacitive_load_unit(1,ff);
26 default_inout_pin_cap : 7.0;
27 default_input_pin_cap : 7.0;
28 default_output_pin_cap : 0.0;
29 default_fanout_load : 1.0;
31 default_wire_load_capacitance : 0.1;
32 default_wire_load_resistance : 1.0e-3;
33 default_wire_load_area : 0.0;
36 nom_temperature : 25.0;
39 delay_model : generic_cmos;
54 /* tri-state inverter */
81 /* 2-input NAND gate */
92 function : "(A * B)'";
96 /* 2-input NOR gate */
107 function : "(A + B)'";
122 function : "(A *B') + (A' * B)";
126 /* 2-input inverting MUX */
140 function : "( (A * S) + (B * S') )'";
144 /* D-type flip-flop with asynchronous reset and preset */
152 clear_preset_var1 : L;
153 clear_preset_var2 : L;
171 timing_type : rising_edge;
180 timing_sense : positive_unate;
182 related_pin : "RESET";
185 timing_type : preset;
186 timing_sense : negative_unate;
188 related_pin : "PRESET";
195 timing_type : rising_edge;
203 timing_type : preset;
204 timing_sense : negative_unate;
206 related_pin : "RESET";
210 timing_sense : positive_unate;
212 related_pin : "PRESET";
238 timing_type : rising_edge;
247 timing_sense : positive_unate;
259 internal_node : "QN";
262 timing_type : rising_edge;
271 timing_sense : negative_unate;
281 /* 3 input AND-OR-INVERT gate */
295 function : "((A * B) + C)'";
300 /* 3 input OR-AND-INVERT gate */
314 function : "((A + B) * C)'";
329 function : "(A * B)";
333 function : "(A *B') + (A' * B)";
351 function : "(((A * B)+(B * CI))+(CI * A))";
355 function : "((A^B)^CI)";