Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys
[yosys.git] / tests / liberty / processdefs.lib
1 /********************************************/
2 /* */
3 /* Supergate cell library for Bench marking */
4 /* */
5 /* Symbiotic EDA GmbH / Moseley Instruments */
6 /* Niels A. Moseley */
7 /* */
8 /* Process: none */
9 /* */
10 /* Date : 25-03-2019 */
11 /* Version: 1.0 */
12 /* */
13 /********************************************/
14
15 library(processdefs) {
16 technology (cmos);
17 revision : 1.0;
18
19 time_unit : "1ps";
20 pulling_resistance_unit : "1kohm";
21 voltage_unit : "1V";
22 current_unit : "1uA";
23
24 capacitive_load_unit(1,ff);
25
26 default_inout_pin_cap : 7.0;
27 default_input_pin_cap : 7.0;
28 default_output_pin_cap : 0.0;
29 default_fanout_load : 1.0;
30
31 default_wire_load_capacitance : 0.1;
32 default_wire_load_resistance : 1.0e-3;
33 default_wire_load_area : 0.0;
34
35 nom_process : 1.0;
36 nom_temperature : 25.0;
37 nom_voltage : 1.2;
38
39 delay_model : generic_cmos;
40
41 define_cell_area(bond_pads,pad_slots)
42 input_voltage(cmos) {
43 vil : 0.3 * VDD ;
44 vih : 0.7 * VDD ;
45 vimin : -0.5 ;
46 vimax : VDD + 0.5 ;
47 }
48 }