Add ability to override verilog mode for verific -f command
[yosys.git] / tests / liberty / semicolmissing.lib
1 /********************************************/
2 /* */
3 /* Supergate cell library for Bench marking */
4 /* */
5 /* Symbiotic EDA GmbH / Moseley Instruments */
6 /* Niels A. Moseley */
7 /* */
8 /* Process: none */
9 /* */
10 /* Date : 24-03-2019 */
11 /* Version: 1.0 */
12 /* Version: 1.1 - Removed semicolons in */
13 /* full adder */
14 /* */
15 /********************************************/
16
17 /*
18 semi colon is missing in full-adder specification
19 some TSMC liberty files are formatted this way..
20 */
21
22 library(supergate) {
23 technology (cmos);
24 revision : 1.0;
25
26 time_unit : "1ps";
27 pulling_resistance_unit : "1kohm";
28 voltage_unit : "1V";
29 current_unit : "1uA";
30
31 capacitive_load_unit(1,ff);
32
33 default_inout_pin_cap : 7.0;
34 default_input_pin_cap : 7.0;
35 default_output_pin_cap : 0.0;
36 default_fanout_load : 1.0;
37
38 default_wire_load_capacitance : 0.1;
39 default_wire_load_resistance : 1.0e-3;
40 default_wire_load_area : 0.0;
41
42 nom_process : 1.0;
43 nom_temperature : 25.0;
44 nom_voltage : 1.2;
45
46 delay_model : generic_cmos;
47
48 /* full adder */
49 cell (fulladder) {
50 area : 8
51 pin(A) {
52 direction : input
53 }
54 pin(B) {
55 direction : input
56 }
57 pin(CI) {
58 direction : input
59 }
60 pin(CO) {
61 direction : output
62 function : "(((A * B)+(B * CI))+(CI * A))"
63 }
64 pin(Y) {
65 direction: output
66 function : "((A^B)^CI)"
67 }
68 }
69
70 } /* end */
71
72