1 /********************************************/
3 /* Supergate cell library for Bench marking */
5 /* Symbiotic EDA GmbH / Moseley Instruments */
10 /* Date : 24-03-2019 */
12 /* Version: 1.1 - Removed semicolons in */
15 /********************************************/
18 semi colon is missing in full-adder specification
19 some TSMC liberty files are formatted this way..
27 pulling_resistance_unit : "1kohm";
31 capacitive_load_unit(1,ff);
33 default_inout_pin_cap : 7.0;
34 default_input_pin_cap : 7.0;
35 default_output_pin_cap : 0.0;
36 default_fanout_load : 1.0;
38 default_wire_load_capacitance : 0.1;
39 default_wire_load_resistance : 1.0e-3;
40 default_wire_load_area : 0.0;
43 nom_temperature : 25.0;
46 delay_model : generic_cmos;
62 function : "(((A * B)+(B * CI))+(CI * A))"
66 function : "((A^B)^CI)"