tests/liberty/small.v

   1 /** small, meaningless design to test loading of liberty files */
   2
   3 module small
   4 (
   5     input clk,
   6     output reg[7:0] count
   7 );
   8
   9 initial count = 0;
  10
  11 always @ (posedge clk)
  12 begin
  13     count <= count + 1'b1;
  14 end
  15
  16 endmodule