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Merge zizzer:/bk/newmem
[gem5.git] / tests / long / 00.gzip / ref / alpha / linux / simple-timing / m5stats.txt
1
2 ---------- Begin Simulation Statistics ----------
3 global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
4 global.BPredUnit.BTBHits 542 # Number of BTB hits
5 global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
6 global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
7 global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
8 global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
9 global.BPredUnit.lookups 2256 # Number of BP lookups
10 global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
11 host_inst_rate 41797 # Simulator instruction rate (inst/s)
12 host_mem_usage 160344 # Number of bytes of host memory used
13 host_seconds 0.13 # Real time elapsed on the host
14 host_tick_rate 50948 # Simulator tick rate (ticks/s)
15 memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
16 memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
17 memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
18 memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
19 sim_freq 1000000000000 # Frequency of simulated ticks
20 sim_insts 5623 # Number of instructions simulated
21 sim_seconds 0.000000 # Number of seconds simulated
22 sim_ticks 6870 # Number of ticks simulated
23 system.cpu.commit.COM:branches 862 # Number of branches committed
24 system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
25 system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
26 system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
27 system.cpu.commit.COM:committed_per_cycle.samples 6116
28 system.cpu.commit.COM:committed_per_cycle.min_value 0
29 0 3908 6389.80%
30 1 1064 1739.70%
31 2 389 636.04%
32 3 210 343.36%
33 4 153 250.16%
34 5 93 152.06%
35 6 76 124.26%
36 7 149 243.62%
37 8 74 120.99%
38 system.cpu.commit.COM:committed_per_cycle.max_value 8
39 system.cpu.commit.COM:committed_per_cycle.end_dist
40
41 system.cpu.commit.COM:count 5640 # Number of instructions committed
42 system.cpu.commit.COM:loads 979 # Number of loads committed
43 system.cpu.commit.COM:membars 0 # Number of memory barriers committed
44 system.cpu.commit.COM:refs 1791 # Number of memory references committed
45 system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
46 system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
47 system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
48 system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
49 system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
50 system.cpu.committedInsts 5623 # Number of Instructions Simulated
51 system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
52 system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
53 system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
54 system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
55 system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
56 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
57 system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
58 system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
59 system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
60 system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
61 system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
62 system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
63 system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
64 system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
65 system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
66 system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
67 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
68 system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
69 system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
70 system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
71 system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
72 system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
73 system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
74 system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
75 system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
76 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
77 system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
78 system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
79 system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
80 system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
81 system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
82 system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
83 system.cpu.dcache.cache_copies 0 # number of cache copies performed
84 system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
85 system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
86 system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
87 system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
88 system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
89 system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
90 system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
91 system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
92 system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
93 system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
94 system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
95 system.cpu.dcache.fast_writes 0 # number of fast writes performed
96 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
97 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
98 system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
99 system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
100 system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
101 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
102 system.cpu.dcache.overall_hits 2048 # number of overall hits
103 system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
104 system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
105 system.cpu.dcache.overall_misses 311 # number of overall misses
106 system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
107 system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
108 system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
109 system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
110 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
111 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
112 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
113 system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
114 system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
115 system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
116 system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
117 system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
118 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
119 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
120 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
121 system.cpu.dcache.replacements 0 # number of replacements
122 system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
123 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
124 system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
125 system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
126 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
127 system.cpu.dcache.writebacks 0 # number of writebacks
128 system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
129 system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
130 system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
131 system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
132 system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
133 system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
134 system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
135 system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
136 system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
137 system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
138 system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
139 system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
140 system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
141 system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
142 system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
143 system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
144 system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
145 system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
146 system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
147 system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
148 system.cpu.fetch.rateDist.samples 6871
149 system.cpu.fetch.rateDist.min_value 0
150 0 4549 6620.58%
151 1 174 253.24%
152 2 186 270.70%
153 3 157 228.50%
154 4 211 307.09%
155 5 153 222.68%
156 6 171 248.87%
157 7 105 152.82%
158 8 1165 1695.53%
159 system.cpu.fetch.rateDist.max_value 8
160 system.cpu.fetch.rateDist.end_dist
161
162 system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
163 system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
164 system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
165 system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
166 system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
167 system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
168 system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
169 system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
170 system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
171 system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
172 system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
173 system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
174 system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
175 system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
176 system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
177 system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
178 system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
179 system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
180 system.cpu.icache.cache_copies 0 # number of cache copies performed
181 system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
182 system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
183 system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
184 system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
185 system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
186 system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
187 system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
188 system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
189 system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
190 system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
191 system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
192 system.cpu.icache.fast_writes 0 # number of fast writes performed
193 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
194 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
195 system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
196 system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
197 system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
198 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
199 system.cpu.icache.overall_hits 1255 # number of overall hits
200 system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
201 system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
202 system.cpu.icache.overall_misses 327 # number of overall misses
203 system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
204 system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
205 system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
206 system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
207 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
208 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
209 system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
210 system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
211 system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
212 system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
213 system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
214 system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
215 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
216 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
217 system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
218 system.cpu.icache.replacements 0 # number of replacements
219 system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
220 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
221 system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
222 system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
223 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
224 system.cpu.icache.writebacks 0 # number of writebacks
225 system.cpu.iew.EXEC:branches 1206 # Number of branches executed
226 system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
227 system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
228 system.cpu.iew.EXEC:nop 37 # number of nop insts executed
229 system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
230 system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
231 system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
232 system.cpu.iew.EXEC:stores 989 # Number of stores executed
233 system.cpu.iew.EXEC:swp 0 # number of swp insts executed
234 system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
235 system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
236 system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
237 system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
238 system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
239 system.cpu.iew.WB:producers 4049 # num instructions producing a value
240 system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
241 system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
242 system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
243 system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
244 system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
245 system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
246 system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
247 system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
248 system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
249 system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
250 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
251 system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
252 system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
253 system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
254 system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
255 system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
256 system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
257 system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
258 system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
259 system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
260 system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
261 system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
262 system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
263 system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
264 system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
265 system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
266 system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
267 system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
268 system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
269 system.cpu.iq.IQ:residence:(null).samples 0
270 system.cpu.iq.IQ:residence:(null).min_value 0
271 0 0
272 2 0
273 4 0
274 6 0
275 8 0
276 10 0
277 12 0
278 14 0
279 16 0
280 18 0
281 20 0
282 22 0
283 24 0
284 26 0
285 28 0
286 30 0
287 32 0
288 34 0
289 36 0
290 38 0
291 40 0
292 42 0
293 44 0
294 46 0
295 48 0
296 50 0
297 52 0
298 54 0
299 56 0
300 58 0
301 60 0
302 62 0
303 64 0
304 66 0
305 68 0
306 70 0
307 72 0
308 74 0
309 76 0
310 78 0
311 80 0
312 82 0
313 84 0
314 86 0
315 88 0
316 90 0
317 92 0
318 94 0
319 96 0
320 98 0
321 system.cpu.iq.IQ:residence:(null).max_value 0
322 system.cpu.iq.IQ:residence:(null).end_dist
323
324 system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
325 system.cpu.iq.IQ:residence:IntAlu.samples 0
326 system.cpu.iq.IQ:residence:IntAlu.min_value 0
327 0 0
328 2 0
329 4 0
330 6 0
331 8 0
332 10 0
333 12 0
334 14 0
335 16 0
336 18 0
337 20 0
338 22 0
339 24 0
340 26 0
341 28 0
342 30 0
343 32 0
344 34 0
345 36 0
346 38 0
347 40 0
348 42 0
349 44 0
350 46 0
351 48 0
352 50 0
353 52 0
354 54 0
355 56 0
356 58 0
357 60 0
358 62 0
359 64 0
360 66 0
361 68 0
362 70 0
363 72 0
364 74 0
365 76 0
366 78 0
367 80 0
368 82 0
369 84 0
370 86 0
371 88 0
372 90 0
373 92 0
374 94 0
375 96 0
376 98 0
377 system.cpu.iq.IQ:residence:IntAlu.max_value 0
378 system.cpu.iq.IQ:residence:IntAlu.end_dist
379
380 system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
381 system.cpu.iq.IQ:residence:IntMult.samples 0
382 system.cpu.iq.IQ:residence:IntMult.min_value 0
383 0 0
384 2 0
385 4 0
386 6 0
387 8 0
388 10 0
389 12 0
390 14 0
391 16 0
392 18 0
393 20 0
394 22 0
395 24 0
396 26 0
397 28 0
398 30 0
399 32 0
400 34 0
401 36 0
402 38 0
403 40 0
404 42 0
405 44 0
406 46 0
407 48 0
408 50 0
409 52 0
410 54 0
411 56 0
412 58 0
413 60 0
414 62 0
415 64 0
416 66 0
417 68 0
418 70 0
419 72 0
420 74 0
421 76 0
422 78 0
423 80 0
424 82 0
425 84 0
426 86 0
427 88 0
428 90 0
429 92 0
430 94 0
431 96 0
432 98 0
433 system.cpu.iq.IQ:residence:IntMult.max_value 0
434 system.cpu.iq.IQ:residence:IntMult.end_dist
435
436 system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
437 system.cpu.iq.IQ:residence:IntDiv.samples 0
438 system.cpu.iq.IQ:residence:IntDiv.min_value 0
439 0 0
440 2 0
441 4 0
442 6 0
443 8 0
444 10 0
445 12 0
446 14 0
447 16 0
448 18 0
449 20 0
450 22 0
451 24 0
452 26 0
453 28 0
454 30 0
455 32 0
456 34 0
457 36 0
458 38 0
459 40 0
460 42 0
461 44 0
462 46 0
463 48 0
464 50 0
465 52 0
466 54 0
467 56 0
468 58 0
469 60 0
470 62 0
471 64 0
472 66 0
473 68 0
474 70 0
475 72 0
476 74 0
477 76 0
478 78 0
479 80 0
480 82 0
481 84 0
482 86 0
483 88 0
484 90 0
485 92 0
486 94 0
487 96 0
488 98 0
489 system.cpu.iq.IQ:residence:IntDiv.max_value 0
490 system.cpu.iq.IQ:residence:IntDiv.end_dist
491
492 system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
493 system.cpu.iq.IQ:residence:FloatAdd.samples 0
494 system.cpu.iq.IQ:residence:FloatAdd.min_value 0
495 0 0
496 2 0
497 4 0
498 6 0
499 8 0
500 10 0
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502 14 0
503 16 0
504 18 0
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540 90 0
541 92 0
542 94 0
543 96 0
544 98 0
545 system.cpu.iq.IQ:residence:FloatAdd.max_value 0
546 system.cpu.iq.IQ:residence:FloatAdd.end_dist
547
548 system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
549 system.cpu.iq.IQ:residence:FloatCmp.samples 0
550 system.cpu.iq.IQ:residence:FloatCmp.min_value 0
551 0 0
552 2 0
553 4 0
554 6 0
555 8 0
556 10 0
557 12 0
558 14 0
559 16 0
560 18 0
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562 22 0
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596 90 0
597 92 0
598 94 0
599 96 0
600 98 0
601 system.cpu.iq.IQ:residence:FloatCmp.max_value 0
602 system.cpu.iq.IQ:residence:FloatCmp.end_dist
603
604 system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
605 system.cpu.iq.IQ:residence:FloatCvt.samples 0
606 system.cpu.iq.IQ:residence:FloatCvt.min_value 0
607 0 0
608 2 0
609 4 0
610 6 0
611 8 0
612 10 0
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614 14 0
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652 90 0
653 92 0
654 94 0
655 96 0
656 98 0
657 system.cpu.iq.IQ:residence:FloatCvt.max_value 0
658 system.cpu.iq.IQ:residence:FloatCvt.end_dist
659
660 system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
661 system.cpu.iq.IQ:residence:FloatMult.samples 0
662 system.cpu.iq.IQ:residence:FloatMult.min_value 0
663 0 0
664 2 0
665 4 0
666 6 0
667 8 0
668 10 0
669 12 0
670 14 0
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708 90 0
709 92 0
710 94 0
711 96 0
712 98 0
713 system.cpu.iq.IQ:residence:FloatMult.max_value 0
714 system.cpu.iq.IQ:residence:FloatMult.end_dist
715
716 system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
717 system.cpu.iq.IQ:residence:FloatDiv.samples 0
718 system.cpu.iq.IQ:residence:FloatDiv.min_value 0
719 0 0
720 2 0
721 4 0
722 6 0
723 8 0
724 10 0
725 12 0
726 14 0
727 16 0
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765 92 0
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767 96 0
768 98 0
769 system.cpu.iq.IQ:residence:FloatDiv.max_value 0
770 system.cpu.iq.IQ:residence:FloatDiv.end_dist
771
772 system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
773 system.cpu.iq.IQ:residence:FloatSqrt.samples 0
774 system.cpu.iq.IQ:residence:FloatSqrt.min_value 0
775 0 0
776 2 0
777 4 0
778 6 0
779 8 0
780 10 0
781 12 0
782 14 0
783 16 0
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820 90 0
821 92 0
822 94 0
823 96 0
824 98 0
825 system.cpu.iq.IQ:residence:FloatSqrt.max_value 0
826 system.cpu.iq.IQ:residence:FloatSqrt.end_dist
827
828 system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
829 system.cpu.iq.IQ:residence:MemRead.samples 0
830 system.cpu.iq.IQ:residence:MemRead.min_value 0
831 0 0
832 2 0
833 4 0
834 6 0
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840 18 0
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876 90 0
877 92 0
878 94 0
879 96 0
880 98 0
881 system.cpu.iq.IQ:residence:MemRead.max_value 0
882 system.cpu.iq.IQ:residence:MemRead.end_dist
883
884 system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
885 system.cpu.iq.IQ:residence:MemWrite.samples 0
886 system.cpu.iq.IQ:residence:MemWrite.min_value 0
887 0 0
888 2 0
889 4 0
890 6 0
891 8 0
892 10 0
893 12 0
894 14 0
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896 18 0
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933 92 0
934 94 0
935 96 0
936 98 0
937 system.cpu.iq.IQ:residence:MemWrite.max_value 0
938 system.cpu.iq.IQ:residence:MemWrite.end_dist
939
940 system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
941 system.cpu.iq.IQ:residence:IprAccess.samples 0
942 system.cpu.iq.IQ:residence:IprAccess.min_value 0
943 0 0
944 2 0
945 4 0
946 6 0
947 8 0
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990 94 0
991 96 0
992 98 0
993 system.cpu.iq.IQ:residence:IprAccess.max_value 0
994 system.cpu.iq.IQ:residence:IprAccess.end_dist
995
996 system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
997 system.cpu.iq.IQ:residence:InstPrefetch.samples 0
998 system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
999 0 0
1000 2 0
1001 4 0
1002 6 0
1003 8 0
1004 10 0
1005 12 0
1006 14 0
1007 16 0
1008 18 0
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1016 34 0
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1021 44 0
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1044 90 0
1045 92 0
1046 94 0
1047 96 0
1048 98 0
1049 system.cpu.iq.IQ:residence:InstPrefetch.max_value 0
1050 system.cpu.iq.IQ:residence:InstPrefetch.end_dist
1051
1052 system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
1053 system.cpu.iq.ISSUE:(null)_delay.samples 0
1054 system.cpu.iq.ISSUE:(null)_delay.min_value 0
1055 0 0
1056 2 0
1057 4 0
1058 6 0
1059 8 0
1060 10 0
1061 12 0
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1100 90 0
1101 92 0
1102 94 0
1103 96 0
1104 98 0
1105 system.cpu.iq.ISSUE:(null)_delay.max_value 0
1106 system.cpu.iq.ISSUE:(null)_delay.end_dist
1107
1108 system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
1109 system.cpu.iq.ISSUE:IntAlu_delay.samples 0
1110 system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
1111 0 0
1112 2 0
1113 4 0
1114 6 0
1115 8 0
1116 10 0
1117 12 0
1118 14 0
1119 16 0
1120 18 0
1121 20 0
1122 22 0
1123 24 0
1124 26 0
1125 28 0
1126 30 0
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1128 34 0
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1156 90 0
1157 92 0
1158 94 0
1159 96 0
1160 98 0
1161 system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
1162 system.cpu.iq.ISSUE:IntAlu_delay.end_dist
1163
1164 system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
1165 system.cpu.iq.ISSUE:IntMult_delay.samples 0
1166 system.cpu.iq.ISSUE:IntMult_delay.min_value 0
1167 0 0
1168 2 0
1169 4 0
1170 6 0
1171 8 0
1172 10 0
1173 12 0
1174 14 0
1175 16 0
1176 18 0
1177 20 0
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1190 46 0
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1213 92 0
1214 94 0
1215 96 0
1216 98 0
1217 system.cpu.iq.ISSUE:IntMult_delay.max_value 0
1218 system.cpu.iq.ISSUE:IntMult_delay.end_dist
1219
1220 system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
1221 system.cpu.iq.ISSUE:IntDiv_delay.samples 0
1222 system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
1223 0 0
1224 2 0
1225 4 0
1226 6 0
1227 8 0
1228 10 0
1229 12 0
1230 14 0
1231 16 0
1232 18 0
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1234 22 0
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1269 92 0
1270 94 0
1271 96 0
1272 98 0
1273 system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
1274 system.cpu.iq.ISSUE:IntDiv_delay.end_dist
1275
1276 system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
1277 system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
1278 system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
1279 0 0
1280 2 0
1281 4 0
1282 6 0
1283 8 0
1284 10 0
1285 12 0
1286 14 0
1287 16 0
1288 18 0
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1321 84 0
1322 86 0
1323 88 0
1324 90 0
1325 92 0
1326 94 0
1327 96 0
1328 98 0
1329 system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
1330 system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
1331
1332 system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
1333 system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
1334 system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
1335 0 0
1336 2 0
1337 4 0
1338 6 0
1339 8 0
1340 10 0
1341 12 0
1342 14 0
1343 16 0
1344 18 0
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1377 84 0
1378 86 0
1379 88 0
1380 90 0
1381 92 0
1382 94 0
1383 96 0
1384 98 0
1385 system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
1386 system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
1387
1388 system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
1389 system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
1390 system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
1391 0 0
1392 2 0
1393 4 0
1394 6 0
1395 8 0
1396 10 0
1397 12 0
1398 14 0
1399 16 0
1400 18 0
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1434 86 0
1435 88 0
1436 90 0
1437 92 0
1438 94 0
1439 96 0
1440 98 0
1441 system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
1442 system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
1443
1444 system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
1445 system.cpu.iq.ISSUE:FloatMult_delay.samples 0
1446 system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
1447 0 0
1448 2 0
1449 4 0
1450 6 0
1451 8 0
1452 10 0
1453 12 0
1454 14 0
1455 16 0
1456 18 0
1457 20 0
1458 22 0
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1462 30 0
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1471 48 0
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1490 86 0
1491 88 0
1492 90 0
1493 92 0
1494 94 0
1495 96 0
1496 98 0
1497 system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
1498 system.cpu.iq.ISSUE:FloatMult_delay.end_dist
1499
1500 system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
1501 system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
1502 system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
1503 0 0
1504 2 0
1505 4 0
1506 6 0
1507 8 0
1508 10 0
1509 12 0
1510 14 0
1511 16 0
1512 18 0
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1545 84 0
1546 86 0
1547 88 0
1548 90 0
1549 92 0
1550 94 0
1551 96 0
1552 98 0
1553 system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
1554 system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
1555
1556 system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
1557 system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
1558 system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
1559 0 0
1560 2 0
1561 4 0
1562 6 0
1563 8 0
1564 10 0
1565 12 0
1566 14 0
1567 16 0
1568 18 0
1569 20 0
1570 22 0
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1592 66 0
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1599 80 0
1600 82 0
1601 84 0
1602 86 0
1603 88 0
1604 90 0
1605 92 0
1606 94 0
1607 96 0
1608 98 0
1609 system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
1610 system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
1611
1612 system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
1613 system.cpu.iq.ISSUE:MemRead_delay.samples 0
1614 system.cpu.iq.ISSUE:MemRead_delay.min_value 0
1615 0 0
1616 2 0
1617 4 0
1618 6 0
1619 8 0
1620 10 0
1621 12 0
1622 14 0
1623 16 0
1624 18 0
1625 20 0
1626 22 0
1627 24 0
1628 26 0
1629 28 0
1630 30 0
1631 32 0
1632 34 0
1633 36 0
1634 38 0
1635 40 0
1636 42 0
1637 44 0
1638 46 0
1639 48 0
1640 50 0
1641 52 0
1642 54 0
1643 56 0
1644 58 0
1645 60 0
1646 62 0
1647 64 0
1648 66 0
1649 68 0
1650 70 0
1651 72 0
1652 74 0
1653 76 0
1654 78 0
1655 80 0
1656 82 0
1657 84 0
1658 86 0
1659 88 0
1660 90 0
1661 92 0
1662 94 0
1663 96 0
1664 98 0
1665 system.cpu.iq.ISSUE:MemRead_delay.max_value 0
1666 system.cpu.iq.ISSUE:MemRead_delay.end_dist
1667
1668 system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
1669 system.cpu.iq.ISSUE:MemWrite_delay.samples 0
1670 system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
1671 0 0
1672 2 0
1673 4 0
1674 6 0
1675 8 0
1676 10 0
1677 12 0
1678 14 0
1679 16 0
1680 18 0
1681 20 0
1682 22 0
1683 24 0
1684 26 0
1685 28 0
1686 30 0
1687 32 0
1688 34 0
1689 36 0
1690 38 0
1691 40 0
1692 42 0
1693 44 0
1694 46 0
1695 48 0
1696 50 0
1697 52 0
1698 54 0
1699 56 0
1700 58 0
1701 60 0
1702 62 0
1703 64 0
1704 66 0
1705 68 0
1706 70 0
1707 72 0
1708 74 0
1709 76 0
1710 78 0
1711 80 0
1712 82 0
1713 84 0
1714 86 0
1715 88 0
1716 90 0
1717 92 0
1718 94 0
1719 96 0
1720 98 0
1721 system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
1722 system.cpu.iq.ISSUE:MemWrite_delay.end_dist
1723
1724 system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
1725 system.cpu.iq.ISSUE:IprAccess_delay.samples 0
1726 system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
1727 0 0
1728 2 0
1729 4 0
1730 6 0
1731 8 0
1732 10 0
1733 12 0
1734 14 0
1735 16 0
1736 18 0
1737 20 0
1738 22 0
1739 24 0
1740 26 0
1741 28 0
1742 30 0
1743 32 0
1744 34 0
1745 36 0
1746 38 0
1747 40 0
1748 42 0
1749 44 0
1750 46 0
1751 48 0
1752 50 0
1753 52 0
1754 54 0
1755 56 0
1756 58 0
1757 60 0
1758 62 0
1759 64 0
1760 66 0
1761 68 0
1762 70 0
1763 72 0
1764 74 0
1765 76 0
1766 78 0
1767 80 0
1768 82 0
1769 84 0
1770 86 0
1771 88 0
1772 90 0
1773 92 0
1774 94 0
1775 96 0
1776 98 0
1777 system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
1778 system.cpu.iq.ISSUE:IprAccess_delay.end_dist
1779
1780 system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
1781 system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
1782 system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
1783 0 0
1784 2 0
1785 4 0
1786 6 0
1787 8 0
1788 10 0
1789 12 0
1790 14 0
1791 16 0
1792 18 0
1793 20 0
1794 22 0
1795 24 0
1796 26 0
1797 28 0
1798 30 0
1799 32 0
1800 34 0
1801 36 0
1802 38 0
1803 40 0
1804 42 0
1805 44 0
1806 46 0
1807 48 0
1808 50 0
1809 52 0
1810 54 0
1811 56 0
1812 58 0
1813 60 0
1814 62 0
1815 64 0
1816 66 0
1817 68 0
1818 70 0
1819 72 0
1820 74 0
1821 76 0
1822 78 0
1823 80 0
1824 82 0
1825 84 0
1826 86 0
1827 88 0
1828 90 0
1829 92 0
1830 94 0
1831 96 0
1832 98 0
1833 system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
1834 system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
1835
1836 system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
1837 system.cpu.iq.ISSUE:FU_type_0.start_dist
1838 (null) 2 0.02% # Type of FU issued
1839 IntAlu 5594 66.69% # Type of FU issued
1840 IntMult 1 0.01% # Type of FU issued
1841 IntDiv 0 0.00% # Type of FU issued
1842 FloatAdd 2 0.02% # Type of FU issued
1843 FloatCmp 0 0.00% # Type of FU issued
1844 FloatCvt 0 0.00% # Type of FU issued
1845 FloatMult 0 0.00% # Type of FU issued
1846 FloatDiv 0 0.00% # Type of FU issued
1847 FloatSqrt 0 0.00% # Type of FU issued
1848 MemRead 1757 20.95% # Type of FU issued
1849 MemWrite 1032 12.30% # Type of FU issued
1850 IprAccess 0 0.00% # Type of FU issued
1851 InstPrefetch 0 0.00% # Type of FU issued
1852 system.cpu.iq.ISSUE:FU_type_0.end_dist
1853 system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
1854 system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
1855 system.cpu.iq.ISSUE:fu_full.start_dist
1856 (null) 0 0.00% # attempts to use FU when none available
1857 IntAlu 1 0.87% # attempts to use FU when none available
1858 IntMult 0 0.00% # attempts to use FU when none available
1859 IntDiv 0 0.00% # attempts to use FU when none available
1860 FloatAdd 0 0.00% # attempts to use FU when none available
1861 FloatCmp 0 0.00% # attempts to use FU when none available
1862 FloatCvt 0 0.00% # attempts to use FU when none available
1863 FloatMult 0 0.00% # attempts to use FU when none available
1864 FloatDiv 0 0.00% # attempts to use FU when none available
1865 FloatSqrt 0 0.00% # attempts to use FU when none available
1866 MemRead 76 66.09% # attempts to use FU when none available
1867 MemWrite 38 33.04% # attempts to use FU when none available
1868 IprAccess 0 0.00% # attempts to use FU when none available
1869 InstPrefetch 0 0.00% # attempts to use FU when none available
1870 system.cpu.iq.ISSUE:fu_full.end_dist
1871 system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
1872 system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
1873 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
1874 0 3753 5462.09%
1875 1 894 1301.12%
1876 2 723 1052.25%
1877 3 614 893.61%
1878 4 451 656.38%
1879 5 279 406.05%
1880 6 104 151.36%
1881 7 41 59.67%
1882 8 12 17.46%
1883 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
1884 system.cpu.iq.ISSUE:issued_per_cycle.end_dist
1885
1886 system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
1887 system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
1888 system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
1889 system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
1890 system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
1891 system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
1892 system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
1893 system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
1894 system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
1895 system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
1896 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
1897 system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
1898 system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
1899 system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
1900 system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
1901 system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
1902 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
1903 system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
1904 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
1905 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
1906 system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
1907 system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
1908 system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
1909 system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
1910 system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
1911 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1912 system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
1913 system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
1914 system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
1915 system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
1916 system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
1917 system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
1918 system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
1919 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
1920 system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
1921 system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
1922 system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
1923 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1924 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
1925 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1926 system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
1927 system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
1928 system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
1929 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
1930 system.cpu.l2cache.overall_hits 2 # number of overall hits
1931 system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
1932 system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
1933 system.cpu.l2cache.overall_misses 497 # number of overall misses
1934 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
1935 system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
1936 system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
1937 system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
1938 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
1939 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
1940 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
1941 system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
1942 system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
1943 system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
1944 system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
1945 system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
1946 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
1947 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
1948 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
1949 system.cpu.l2cache.replacements 0 # number of replacements
1950 system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
1951 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
1952 system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
1953 system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
1954 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1955 system.cpu.l2cache.writebacks 0 # number of writebacks
1956 system.cpu.numCycles 6871 # number of cpu cycles simulated
1957 system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
1958 system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
1959 system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
1960 system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
1961 system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
1962 system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
1963 system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
1964 system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
1965 system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
1966 system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
1967 system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
1968 system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
1969 system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
1970 system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
1971 system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
1972 system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
1973
1974 ---------- End Simulation Statistics ----------