tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 time_sync_enable=false
   5 time_sync_period=100000000000
   6 time_sync_spin_threshold=100000000
   7
   8 [system]
   9 type=System
  10 children=cpu membus physmem
  11 mem_mode=atomic
  12 physmem=system.physmem
  13 work_begin_ckpt_count=0
  14 work_begin_cpu_id_exit=-1
  15 work_begin_exit_count=0
  16 work_cpus_ckpt_count=0
  17 work_end_ckpt_count=0
  18 work_end_exit_count=0
  19 work_item_id=-1
  20
  21 [system.cpu]
  22 type=DerivO3CPU
  23 children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
  24 BTBEntries=4096
  25 BTBTagSize=16
  26 LFSTSize=1024
  27 LQEntries=32
  28 RASSize=16
  29 SQEntries=32
  30 SSITSize=1024
  31 activity=0
  32 backComSize=5
  33 cachePorts=200
  34 checker=Null
  35 choiceCtrBits=2
  36 choicePredictorSize=8192
  37 clock=500
  38 commitToDecodeDelay=1
  39 commitToFetchDelay=1
  40 commitToIEWDelay=1
  41 commitToRenameDelay=1
  42 commitWidth=8
  43 cpu_id=0
  44 decodeToFetchDelay=1
  45 decodeToRenameDelay=1
  46 decodeWidth=8
  47 defer_registration=false
  48 dispatchWidth=8
  49 do_checkpoint_insts=true
  50 do_statistics_insts=true
  51 dtb=system.cpu.dtb
  52 fetchToDecodeDelay=1
  53 fetchTrapLatency=1
  54 fetchWidth=8
  55 forwardComSize=5
  56 fuPool=system.cpu.fuPool
  57 function_trace=false
  58 function_trace_start=0
  59 globalCtrBits=2
  60 globalHistoryBits=13
  61 globalPredictorSize=8192
  62 iewToCommitDelay=1
  63 iewToDecodeDelay=1
  64 iewToFetchDelay=1
  65 iewToRenameDelay=1
  66 instShiftAmt=2
  67 issueToExecuteDelay=1
  68 issueWidth=8
  69 itb=system.cpu.itb
  70 localCtrBits=2
  71 localHistoryBits=11
  72 localHistoryTableSize=2048
  73 localPredictorSize=2048
  74 max_insts_all_threads=0
  75 max_insts_any_thread=0
  76 max_loads_all_threads=0
  77 max_loads_any_thread=0
  78 numIQEntries=64
  79 numPhysFloatRegs=256
  80 numPhysIntRegs=256
  81 numROBEntries=192
  82 numRobs=1
  83 numThreads=1
  84 phase=0
  85 predType=tournament
  86 progress_interval=0
  87 renameToDecodeDelay=1
  88 renameToFetchDelay=1
  89 renameToIEWDelay=2
  90 renameToROBDelay=1
  91 renameWidth=8
  92 smtCommitPolicy=RoundRobin
  93 smtFetchPolicy=SingleThread
  94 smtIQPolicy=Partitioned
  95 smtIQThreshold=100
  96 smtLSQPolicy=Partitioned
  97 smtLSQThreshold=100
  98 smtNumFetchingThreads=1
  99 smtROBPolicy=Partitioned
 100 smtROBThreshold=100
 101 squashWidth=8
 102 system=system
 103 tracer=system.cpu.tracer
 104 trapLatency=13
 105 wbDepth=1
 106 wbWidth=8
 107 workload=system.cpu.workload
 108 dcache_port=system.cpu.dcache.cpu_side
 109 icache_port=system.cpu.icache.cpu_side
 110
 111 [system.cpu.dcache]
 112 type=BaseCache
 113 addr_range=0:18446744073709551615
 114 assoc=2
 115 block_size=64
 116 forward_snoops=true
 117 hash_delay=1
 118 latency=1000
 119 max_miss_count=0
 120 mshrs=10
 121 num_cpus=1
 122 prefetch_data_accesses_only=false
 123 prefetch_degree=1
 124 prefetch_latency=10000
 125 prefetch_on_access=false
 126 prefetch_past_page=false
 127 prefetch_policy=none
 128 prefetch_serial_squash=false
 129 prefetch_use_cpu_id=true
 130 prefetcher_size=100
 131 prioritizeRequests=false
 132 repl=Null
 133 size=262144
 134 subblock_size=0
 135 tgts_per_mshr=20
 136 trace_addr=0
 137 two_queue=false
 138 write_buffers=8
 139 cpu_side=system.cpu.dcache_port
 140 mem_side=system.cpu.toL2Bus.port[1]
 141
 142 [system.cpu.dtb]
 143 type=AlphaTLB
 144 size=64
 145
 146 [system.cpu.fuPool]
 147 type=FUPool
 148 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 149 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 150
 151 [system.cpu.fuPool.FUList0]
 152 type=FUDesc
 153 children=opList
 154 count=6
 155 opList=system.cpu.fuPool.FUList0.opList
 156
 157 [system.cpu.fuPool.FUList0.opList]
 158 type=OpDesc
 159 issueLat=1
 160 opClass=IntAlu
 161 opLat=1
 162
 163 [system.cpu.fuPool.FUList1]
 164 type=FUDesc
 165 children=opList0 opList1
 166 count=2
 167 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 168
 169 [system.cpu.fuPool.FUList1.opList0]
 170 type=OpDesc
 171 issueLat=1
 172 opClass=IntMult
 173 opLat=3
 174
 175 [system.cpu.fuPool.FUList1.opList1]
 176 type=OpDesc
 177 issueLat=19
 178 opClass=IntDiv
 179 opLat=20
 180
 181 [system.cpu.fuPool.FUList2]
 182 type=FUDesc
 183 children=opList0 opList1 opList2
 184 count=4
 185 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 186
 187 [system.cpu.fuPool.FUList2.opList0]
 188 type=OpDesc
 189 issueLat=1
 190 opClass=FloatAdd
 191 opLat=2
 192
 193 [system.cpu.fuPool.FUList2.opList1]
 194 type=OpDesc
 195 issueLat=1
 196 opClass=FloatCmp
 197 opLat=2
 198
 199 [system.cpu.fuPool.FUList2.opList2]
 200 type=OpDesc
 201 issueLat=1
 202 opClass=FloatCvt
 203 opLat=2
 204
 205 [system.cpu.fuPool.FUList3]
 206 type=FUDesc
 207 children=opList0 opList1 opList2
 208 count=2
 209 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 210
 211 [system.cpu.fuPool.FUList3.opList0]
 212 type=OpDesc
 213 issueLat=1
 214 opClass=FloatMult
 215 opLat=4
 216
 217 [system.cpu.fuPool.FUList3.opList1]
 218 type=OpDesc
 219 issueLat=12
 220 opClass=FloatDiv
 221 opLat=12
 222
 223 [system.cpu.fuPool.FUList3.opList2]
 224 type=OpDesc
 225 issueLat=24
 226 opClass=FloatSqrt
 227 opLat=24
 228
 229 [system.cpu.fuPool.FUList4]
 230 type=FUDesc
 231 children=opList
 232 count=0
 233 opList=system.cpu.fuPool.FUList4.opList
 234
 235 [system.cpu.fuPool.FUList4.opList]
 236 type=OpDesc
 237 issueLat=1
 238 opClass=MemRead
 239 opLat=1
 240
 241 [system.cpu.fuPool.FUList5]
 242 type=FUDesc
 243 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 244 count=4
 245 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 246
 247 [system.cpu.fuPool.FUList5.opList00]
 248 type=OpDesc
 249 issueLat=1
 250 opClass=SimdAdd
 251 opLat=1
 252
 253 [system.cpu.fuPool.FUList5.opList01]
 254 type=OpDesc
 255 issueLat=1
 256 opClass=SimdAddAcc
 257 opLat=1
 258
 259 [system.cpu.fuPool.FUList5.opList02]
 260 type=OpDesc
 261 issueLat=1
 262 opClass=SimdAlu
 263 opLat=1
 264
 265 [system.cpu.fuPool.FUList5.opList03]
 266 type=OpDesc
 267 issueLat=1
 268 opClass=SimdCmp
 269 opLat=1
 270
 271 [system.cpu.fuPool.FUList5.opList04]
 272 type=OpDesc
 273 issueLat=1
 274 opClass=SimdCvt
 275 opLat=1
 276
 277 [system.cpu.fuPool.FUList5.opList05]
 278 type=OpDesc
 279 issueLat=1
 280 opClass=SimdMisc
 281 opLat=1
 282
 283 [system.cpu.fuPool.FUList5.opList06]
 284 type=OpDesc
 285 issueLat=1
 286 opClass=SimdMult
 287 opLat=1
 288
 289 [system.cpu.fuPool.FUList5.opList07]
 290 type=OpDesc
 291 issueLat=1
 292 opClass=SimdMultAcc
 293 opLat=1
 294
 295 [system.cpu.fuPool.FUList5.opList08]
 296 type=OpDesc
 297 issueLat=1
 298 opClass=SimdShift
 299 opLat=1
 300
 301 [system.cpu.fuPool.FUList5.opList09]
 302 type=OpDesc
 303 issueLat=1
 304 opClass=SimdShiftAcc
 305 opLat=1
 306
 307 [system.cpu.fuPool.FUList5.opList10]
 308 type=OpDesc
 309 issueLat=1
 310 opClass=SimdSqrt
 311 opLat=1
 312
 313 [system.cpu.fuPool.FUList5.opList11]
 314 type=OpDesc
 315 issueLat=1
 316 opClass=SimdFloatAdd
 317 opLat=1
 318
 319 [system.cpu.fuPool.FUList5.opList12]
 320 type=OpDesc
 321 issueLat=1
 322 opClass=SimdFloatAlu
 323 opLat=1
 324
 325 [system.cpu.fuPool.FUList5.opList13]
 326 type=OpDesc
 327 issueLat=1
 328 opClass=SimdFloatCmp
 329 opLat=1
 330
 331 [system.cpu.fuPool.FUList5.opList14]
 332 type=OpDesc
 333 issueLat=1
 334 opClass=SimdFloatCvt
 335 opLat=1
 336
 337 [system.cpu.fuPool.FUList5.opList15]
 338 type=OpDesc
 339 issueLat=1
 340 opClass=SimdFloatDiv
 341 opLat=1
 342
 343 [system.cpu.fuPool.FUList5.opList16]
 344 type=OpDesc
 345 issueLat=1
 346 opClass=SimdFloatMisc
 347 opLat=1
 348
 349 [system.cpu.fuPool.FUList5.opList17]
 350 type=OpDesc
 351 issueLat=1
 352 opClass=SimdFloatMult
 353 opLat=1
 354
 355 [system.cpu.fuPool.FUList5.opList18]
 356 type=OpDesc
 357 issueLat=1
 358 opClass=SimdFloatMultAcc
 359 opLat=1
 360
 361 [system.cpu.fuPool.FUList5.opList19]
 362 type=OpDesc
 363 issueLat=1
 364 opClass=SimdFloatSqrt
 365 opLat=1
 366
 367 [system.cpu.fuPool.FUList6]
 368 type=FUDesc
 369 children=opList
 370 count=0
 371 opList=system.cpu.fuPool.FUList6.opList
 372
 373 [system.cpu.fuPool.FUList6.opList]
 374 type=OpDesc
 375 issueLat=1
 376 opClass=MemWrite
 377 opLat=1
 378
 379 [system.cpu.fuPool.FUList7]
 380 type=FUDesc
 381 children=opList0 opList1
 382 count=4
 383 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 384
 385 [system.cpu.fuPool.FUList7.opList0]
 386 type=OpDesc
 387 issueLat=1
 388 opClass=MemRead
 389 opLat=1
 390
 391 [system.cpu.fuPool.FUList7.opList1]
 392 type=OpDesc
 393 issueLat=1
 394 opClass=MemWrite
 395 opLat=1
 396
 397 [system.cpu.fuPool.FUList8]
 398 type=FUDesc
 399 children=opList
 400 count=1
 401 opList=system.cpu.fuPool.FUList8.opList
 402
 403 [system.cpu.fuPool.FUList8.opList]
 404 type=OpDesc
 405 issueLat=3
 406 opClass=IprAccess
 407 opLat=3
 408
 409 [system.cpu.icache]
 410 type=BaseCache
 411 addr_range=0:18446744073709551615
 412 assoc=2
 413 block_size=64
 414 forward_snoops=true
 415 hash_delay=1
 416 latency=1000
 417 max_miss_count=0
 418 mshrs=10
 419 num_cpus=1
 420 prefetch_data_accesses_only=false
 421 prefetch_degree=1
 422 prefetch_latency=10000
 423 prefetch_on_access=false
 424 prefetch_past_page=false
 425 prefetch_policy=none
 426 prefetch_serial_squash=false
 427 prefetch_use_cpu_id=true
 428 prefetcher_size=100
 429 prioritizeRequests=false
 430 repl=Null
 431 size=131072
 432 subblock_size=0
 433 tgts_per_mshr=20
 434 trace_addr=0
 435 two_queue=false
 436 write_buffers=8
 437 cpu_side=system.cpu.icache_port
 438 mem_side=system.cpu.toL2Bus.port[0]
 439
 440 [system.cpu.itb]
 441 type=AlphaTLB
 442 size=48
 443
 444 [system.cpu.l2cache]
 445 type=BaseCache
 446 addr_range=0:18446744073709551615
 447 assoc=2
 448 block_size=64
 449 forward_snoops=true
 450 hash_delay=1
 451 latency=1000
 452 max_miss_count=0
 453 mshrs=10
 454 num_cpus=1
 455 prefetch_data_accesses_only=false
 456 prefetch_degree=1
 457 prefetch_latency=10000
 458 prefetch_on_access=false
 459 prefetch_past_page=false
 460 prefetch_policy=none
 461 prefetch_serial_squash=false
 462 prefetch_use_cpu_id=true
 463 prefetcher_size=100
 464 prioritizeRequests=false
 465 repl=Null
 466 size=2097152
 467 subblock_size=0
 468 tgts_per_mshr=5
 469 trace_addr=0
 470 two_queue=false
 471 write_buffers=8
 472 cpu_side=system.cpu.toL2Bus.port[2]
 473 mem_side=system.membus.port[1]
 474
 475 [system.cpu.toL2Bus]
 476 type=Bus
 477 block_size=64
 478 bus_id=0
 479 clock=1000
 480 header_cycles=1
 481 use_default_range=false
 482 width=64
 483 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 484
 485 [system.cpu.tracer]
 486 type=ExeTracer
 487
 488 [system.cpu.workload]
 489 type=LiveProcess
 490 cmd=gzip input.log 1
 491 cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
 492 egid=100
 493 env=
 494 errout=cerr
 495 euid=100
 496 executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
 497 gid=100
 498 input=cin
 499 max_stack_size=67108864
 500 output=cout
 501 pid=100
 502 ppid=99
 503 simpoint=0
 504 system=system
 505 uid=100
 506
 507 [system.membus]
 508 type=Bus
 509 block_size=64
 510 bus_id=0
 511 clock=1000
 512 header_cycles=1
 513 use_default_range=false
 514 width=64
 515 port=system.physmem.port[0] system.cpu.l2cache.mem_side
 516
 517 [system.physmem]
 518 type=PhysicalMemory
 519 file=
 520 latency=30000
 521 latency_var=0
 522 null=false
 523 range=0:134217727
 524 zero=false
 525 port=system.membus.port[0]
 526