tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 dummy=0
   5
   6 [system]
   7 type=System
   8 children=cpu membus physmem
   9 mem_mode=atomic
  10 physmem=system.physmem
  11
  12 [system.cpu]
  13 type=DerivO3CPU
  14 children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
  15 BTBEntries=4096
  16 BTBTagSize=16
  17 LFSTSize=1024
  18 LQEntries=32
  19 RASSize=16
  20 SQEntries=32
  21 SSITSize=1024
  22 activity=0
  23 backComSize=5
  24 cachePorts=200
  25 choiceCtrBits=2
  26 choicePredictorSize=8192
  27 clock=500
  28 commitToDecodeDelay=1
  29 commitToFetchDelay=1
  30 commitToIEWDelay=1
  31 commitToRenameDelay=1
  32 commitWidth=8
  33 cpu_id=0
  34 decodeToFetchDelay=1
  35 decodeToRenameDelay=1
  36 decodeWidth=8
  37 defer_registration=false
  38 dispatchWidth=8
  39 dtb=system.cpu.dtb
  40 fetchToDecodeDelay=1
  41 fetchTrapLatency=1
  42 fetchWidth=8
  43 forwardComSize=5
  44 fuPool=system.cpu.fuPool
  45 function_trace=false
  46 function_trace_start=0
  47 globalCtrBits=2
  48 globalHistoryBits=13
  49 globalPredictorSize=8192
  50 iewToCommitDelay=1
  51 iewToDecodeDelay=1
  52 iewToFetchDelay=1
  53 iewToRenameDelay=1
  54 instShiftAmt=2
  55 issueToExecuteDelay=1
  56 issueWidth=8
  57 itb=system.cpu.itb
  58 localCtrBits=2
  59 localHistoryBits=11
  60 localHistoryTableSize=2048
  61 localPredictorSize=2048
  62 max_insts_all_threads=0
  63 max_insts_any_thread=0
  64 max_loads_all_threads=0
  65 max_loads_any_thread=0
  66 numIQEntries=64
  67 numPhysFloatRegs=256
  68 numPhysIntRegs=256
  69 numROBEntries=192
  70 numRobs=1
  71 numThreads=1
  72 phase=0
  73 predType=tournament
  74 progress_interval=0
  75 renameToDecodeDelay=1
  76 renameToFetchDelay=1
  77 renameToIEWDelay=2
  78 renameToROBDelay=1
  79 renameWidth=8
  80 smtCommitPolicy=RoundRobin
  81 smtFetchPolicy=SingleThread
  82 smtIQPolicy=Partitioned
  83 smtIQThreshold=100
  84 smtLSQPolicy=Partitioned
  85 smtLSQThreshold=100
  86 smtNumFetchingThreads=1
  87 smtROBPolicy=Partitioned
  88 smtROBThreshold=100
  89 squashWidth=8
  90 system=system
  91 tracer=system.cpu.tracer
  92 trapLatency=13
  93 wbDepth=1
  94 wbWidth=8
  95 workload=system.cpu.workload
  96 dcache_port=system.cpu.dcache.cpu_side
  97 icache_port=system.cpu.icache.cpu_side
  98
  99 [system.cpu.dcache]
 100 type=BaseCache
 101 addr_range=0:18446744073709551615
 102 assoc=2
 103 block_size=64
 104 cpu_side_filter_ranges=
 105 hash_delay=1
 106 latency=1000
 107 max_miss_count=0
 108 mem_side_filter_ranges=
 109 mshrs=10
 110 prefetch_access=false
 111 prefetch_cache_check_push=true
 112 prefetch_data_accesses_only=false
 113 prefetch_degree=1
 114 prefetch_latency=10000
 115 prefetch_miss=false
 116 prefetch_past_page=false
 117 prefetch_policy=none
 118 prefetch_serial_squash=false
 119 prefetch_use_cpu_id=true
 120 prefetcher_size=100
 121 prioritizeRequests=false
 122 repl=Null
 123 size=262144
 124 subblock_size=0
 125 tgts_per_mshr=20
 126 trace_addr=0
 127 two_queue=false
 128 write_buffers=8
 129 cpu_side=system.cpu.dcache_port
 130 mem_side=system.cpu.toL2Bus.port[1]
 131
 132 [system.cpu.dtb]
 133 type=AlphaDTB
 134 size=64
 135
 136 [system.cpu.fuPool]
 137 type=FUPool
 138 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
 139 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
 140
 141 [system.cpu.fuPool.FUList0]
 142 type=FUDesc
 143 children=opList
 144 count=6
 145 opList=system.cpu.fuPool.FUList0.opList
 146
 147 [system.cpu.fuPool.FUList0.opList]
 148 type=OpDesc
 149 issueLat=1
 150 opClass=IntAlu
 151 opLat=1
 152
 153 [system.cpu.fuPool.FUList1]
 154 type=FUDesc
 155 children=opList0 opList1
 156 count=2
 157 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 158
 159 [system.cpu.fuPool.FUList1.opList0]
 160 type=OpDesc
 161 issueLat=1
 162 opClass=IntMult
 163 opLat=3
 164
 165 [system.cpu.fuPool.FUList1.opList1]
 166 type=OpDesc
 167 issueLat=19
 168 opClass=IntDiv
 169 opLat=20
 170
 171 [system.cpu.fuPool.FUList2]
 172 type=FUDesc
 173 children=opList0 opList1 opList2
 174 count=4
 175 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 176
 177 [system.cpu.fuPool.FUList2.opList0]
 178 type=OpDesc
 179 issueLat=1
 180 opClass=FloatAdd
 181 opLat=2
 182
 183 [system.cpu.fuPool.FUList2.opList1]
 184 type=OpDesc
 185 issueLat=1
 186 opClass=FloatCmp
 187 opLat=2
 188
 189 [system.cpu.fuPool.FUList2.opList2]
 190 type=OpDesc
 191 issueLat=1
 192 opClass=FloatCvt
 193 opLat=2
 194
 195 [system.cpu.fuPool.FUList3]
 196 type=FUDesc
 197 children=opList0 opList1 opList2
 198 count=2
 199 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 200
 201 [system.cpu.fuPool.FUList3.opList0]
 202 type=OpDesc
 203 issueLat=1
 204 opClass=FloatMult
 205 opLat=4
 206
 207 [system.cpu.fuPool.FUList3.opList1]
 208 type=OpDesc
 209 issueLat=12
 210 opClass=FloatDiv
 211 opLat=12
 212
 213 [system.cpu.fuPool.FUList3.opList2]
 214 type=OpDesc
 215 issueLat=24
 216 opClass=FloatSqrt
 217 opLat=24
 218
 219 [system.cpu.fuPool.FUList4]
 220 type=FUDesc
 221 children=opList
 222 count=0
 223 opList=system.cpu.fuPool.FUList4.opList
 224
 225 [system.cpu.fuPool.FUList4.opList]
 226 type=OpDesc
 227 issueLat=1
 228 opClass=MemRead
 229 opLat=1
 230
 231 [system.cpu.fuPool.FUList5]
 232 type=FUDesc
 233 children=opList
 234 count=0
 235 opList=system.cpu.fuPool.FUList5.opList
 236
 237 [system.cpu.fuPool.FUList5.opList]
 238 type=OpDesc
 239 issueLat=1
 240 opClass=MemWrite
 241 opLat=1
 242
 243 [system.cpu.fuPool.FUList6]
 244 type=FUDesc
 245 children=opList0 opList1
 246 count=4
 247 opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
 248
 249 [system.cpu.fuPool.FUList6.opList0]
 250 type=OpDesc
 251 issueLat=1
 252 opClass=MemRead
 253 opLat=1
 254
 255 [system.cpu.fuPool.FUList6.opList1]
 256 type=OpDesc
 257 issueLat=1
 258 opClass=MemWrite
 259 opLat=1
 260
 261 [system.cpu.fuPool.FUList7]
 262 type=FUDesc
 263 children=opList
 264 count=1
 265 opList=system.cpu.fuPool.FUList7.opList
 266
 267 [system.cpu.fuPool.FUList7.opList]
 268 type=OpDesc
 269 issueLat=3
 270 opClass=IprAccess
 271 opLat=3
 272
 273 [system.cpu.icache]
 274 type=BaseCache
 275 addr_range=0:18446744073709551615
 276 assoc=2
 277 block_size=64
 278 cpu_side_filter_ranges=
 279 hash_delay=1
 280 latency=1000
 281 max_miss_count=0
 282 mem_side_filter_ranges=
 283 mshrs=10
 284 prefetch_access=false
 285 prefetch_cache_check_push=true
 286 prefetch_data_accesses_only=false
 287 prefetch_degree=1
 288 prefetch_latency=10000
 289 prefetch_miss=false
 290 prefetch_past_page=false
 291 prefetch_policy=none
 292 prefetch_serial_squash=false
 293 prefetch_use_cpu_id=true
 294 prefetcher_size=100
 295 prioritizeRequests=false
 296 repl=Null
 297 size=131072
 298 subblock_size=0
 299 tgts_per_mshr=20
 300 trace_addr=0
 301 two_queue=false
 302 write_buffers=8
 303 cpu_side=system.cpu.icache_port
 304 mem_side=system.cpu.toL2Bus.port[0]
 305
 306 [system.cpu.itb]
 307 type=AlphaITB
 308 size=48
 309
 310 [system.cpu.l2cache]
 311 type=BaseCache
 312 addr_range=0:18446744073709551615
 313 assoc=2
 314 block_size=64
 315 cpu_side_filter_ranges=
 316 hash_delay=1
 317 latency=1000
 318 max_miss_count=0
 319 mem_side_filter_ranges=
 320 mshrs=10
 321 prefetch_access=false
 322 prefetch_cache_check_push=true
 323 prefetch_data_accesses_only=false
 324 prefetch_degree=1
 325 prefetch_latency=10000
 326 prefetch_miss=false
 327 prefetch_past_page=false
 328 prefetch_policy=none
 329 prefetch_serial_squash=false
 330 prefetch_use_cpu_id=true
 331 prefetcher_size=100
 332 prioritizeRequests=false
 333 repl=Null
 334 size=2097152
 335 subblock_size=0
 336 tgts_per_mshr=5
 337 trace_addr=0
 338 two_queue=false
 339 write_buffers=8
 340 cpu_side=system.cpu.toL2Bus.port[2]
 341 mem_side=system.membus.port[1]
 342
 343 [system.cpu.toL2Bus]
 344 type=Bus
 345 block_size=64
 346 bus_id=0
 347 clock=1000
 348 header_cycles=1
 349 responder_set=false
 350 width=64
 351 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 352
 353 [system.cpu.tracer]
 354 type=ExeTracer
 355
 356 [system.cpu.workload]
 357 type=LiveProcess
 358 cmd=gzip input.log 1
 359 cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
 360 egid=100
 361 env=
 362 errout=cerr
 363 euid=100
 364 executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
 365 gid=100
 366 input=cin
 367 max_stack_size=67108864
 368 output=cout
 369 pid=100
 370 ppid=99
 371 simpoint=0
 372 system=system
 373 uid=100
 374
 375 [system.membus]
 376 type=Bus
 377 block_size=64
 378 bus_id=0
 379 clock=1000
 380 header_cycles=1
 381 responder_set=false
 382 width=64
 383 port=system.physmem.port[0] system.cpu.l2cache.mem_side
 384
 385 [system.physmem]
 386 type=PhysicalMemory
 387 file=
 388 latency=30000
 389 latency_var=0
 390 null=false
 391 range=0:134217727
 392 zero=false
 393 port=system.membus.port[0]
 394