tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 dummy=0
   5
   6 [system]
   7 type=System
   8 children=cpu membus physmem
   9 mem_mode=atomic
  10 physmem=system.physmem
  11
  12 [system.cpu]
  13 type=DerivO3CPU
  14 children=dcache fuPool icache l2cache toL2Bus workload
  15 BTBEntries=4096
  16 BTBTagSize=16
  17 LFSTSize=1024
  18 LQEntries=32
  19 RASSize=16
  20 SQEntries=32
  21 SSITSize=1024
  22 activity=0
  23 backComSize=5
  24 choiceCtrBits=2
  25 choicePredictorSize=8192
  26 clock=500
  27 commitToDecodeDelay=1
  28 commitToFetchDelay=1
  29 commitToIEWDelay=1
  30 commitToRenameDelay=1
  31 commitWidth=8
  32 cpu_id=0
  33 decodeToFetchDelay=1
  34 decodeToRenameDelay=1
  35 decodeWidth=8
  36 defer_registration=false
  37 dispatchWidth=8
  38 fetchToDecodeDelay=1
  39 fetchTrapLatency=1
  40 fetchWidth=8
  41 forwardComSize=5
  42 fuPool=system.cpu.fuPool
  43 function_trace=false
  44 function_trace_start=0
  45 globalCtrBits=2
  46 globalHistoryBits=13
  47 globalPredictorSize=8192
  48 iewToCommitDelay=1
  49 iewToDecodeDelay=1
  50 iewToFetchDelay=1
  51 iewToRenameDelay=1
  52 instShiftAmt=2
  53 issueToExecuteDelay=1
  54 issueWidth=8
  55 localCtrBits=2
  56 localHistoryBits=11
  57 localHistoryTableSize=2048
  58 localPredictorSize=2048
  59 max_insts_all_threads=0
  60 max_insts_any_thread=0
  61 max_loads_all_threads=0
  62 max_loads_any_thread=0
  63 numIQEntries=64
  64 numPhysFloatRegs=256
  65 numPhysIntRegs=256
  66 numROBEntries=192
  67 numRobs=1
  68 numThreads=1
  69 phase=0
  70 predType=tournament
  71 progress_interval=0
  72 renameToDecodeDelay=1
  73 renameToFetchDelay=1
  74 renameToIEWDelay=2
  75 renameToROBDelay=1
  76 renameWidth=8
  77 squashWidth=8
  78 system=system
  79 trapLatency=13
  80 wbDepth=1
  81 wbWidth=8
  82 workload=system.cpu.workload
  83 dcache_port=system.cpu.dcache.cpu_side
  84 icache_port=system.cpu.icache.cpu_side
  85
  86 [system.cpu.dcache]
  87 type=BaseCache
  88 adaptive_compression=false
  89 assoc=2
  90 block_size=64
  91 compressed_bus=false
  92 compression_latency=0
  93 hash_delay=1
  94 latency=1000
  95 lifo=false
  96 max_miss_count=0
  97 mshrs=10
  98 prefetch_access=false
  99 prefetch_cache_check_push=true
 100 prefetch_data_accesses_only=false
 101 prefetch_degree=1
 102 prefetch_latency=10
 103 prefetch_miss=false
 104 prefetch_past_page=false
 105 prefetch_policy=none
 106 prefetch_serial_squash=false
 107 prefetch_use_cpu_id=true
 108 prefetcher_size=100
 109 prioritizeRequests=false
 110 protocol=Null
 111 repl=Null
 112 size=262144
 113 split=false
 114 split_size=0
 115 store_compressed=false
 116 subblock_size=0
 117 tgts_per_mshr=20
 118 trace_addr=0
 119 two_queue=false
 120 write_buffers=8
 121 cpu_side=system.cpu.dcache_port
 122 mem_side=system.cpu.toL2Bus.port[1]
 123
 124 [system.cpu.fuPool]
 125 type=FUPool
 126 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
 127 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
 128
 129 [system.cpu.fuPool.FUList0]
 130 type=FUDesc
 131 children=opList0
 132 count=6
 133 opList=system.cpu.fuPool.FUList0.opList0
 134
 135 [system.cpu.fuPool.FUList0.opList0]
 136 type=OpDesc
 137 issueLat=1
 138 opClass=IntAlu
 139 opLat=1
 140
 141 [system.cpu.fuPool.FUList1]
 142 type=FUDesc
 143 children=opList0 opList1
 144 count=2
 145 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 146
 147 [system.cpu.fuPool.FUList1.opList0]
 148 type=OpDesc
 149 issueLat=1
 150 opClass=IntMult
 151 opLat=3
 152
 153 [system.cpu.fuPool.FUList1.opList1]
 154 type=OpDesc
 155 issueLat=19
 156 opClass=IntDiv
 157 opLat=20
 158
 159 [system.cpu.fuPool.FUList2]
 160 type=FUDesc
 161 children=opList0 opList1 opList2
 162 count=4
 163 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 164
 165 [system.cpu.fuPool.FUList2.opList0]
 166 type=OpDesc
 167 issueLat=1
 168 opClass=FloatAdd
 169 opLat=2
 170
 171 [system.cpu.fuPool.FUList2.opList1]
 172 type=OpDesc
 173 issueLat=1
 174 opClass=FloatCmp
 175 opLat=2
 176
 177 [system.cpu.fuPool.FUList2.opList2]
 178 type=OpDesc
 179 issueLat=1
 180 opClass=FloatCvt
 181 opLat=2
 182
 183 [system.cpu.fuPool.FUList3]
 184 type=FUDesc
 185 children=opList0 opList1 opList2
 186 count=2
 187 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 188
 189 [system.cpu.fuPool.FUList3.opList0]
 190 type=OpDesc
 191 issueLat=1
 192 opClass=FloatMult
 193 opLat=4
 194
 195 [system.cpu.fuPool.FUList3.opList1]
 196 type=OpDesc
 197 issueLat=12
 198 opClass=FloatDiv
 199 opLat=12
 200
 201 [system.cpu.fuPool.FUList3.opList2]
 202 type=OpDesc
 203 issueLat=24
 204 opClass=FloatSqrt
 205 opLat=24
 206
 207 [system.cpu.fuPool.FUList4]
 208 type=FUDesc
 209 children=opList0
 210 count=0
 211 opList=system.cpu.fuPool.FUList4.opList0
 212
 213 [system.cpu.fuPool.FUList4.opList0]
 214 type=OpDesc
 215 issueLat=1
 216 opClass=MemRead
 217 opLat=1
 218
 219 [system.cpu.fuPool.FUList5]
 220 type=FUDesc
 221 children=opList0
 222 count=0
 223 opList=system.cpu.fuPool.FUList5.opList0
 224
 225 [system.cpu.fuPool.FUList5.opList0]
 226 type=OpDesc
 227 issueLat=1
 228 opClass=MemWrite
 229 opLat=1
 230
 231 [system.cpu.fuPool.FUList6]
 232 type=FUDesc
 233 children=opList0 opList1
 234 count=4
 235 opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
 236
 237 [system.cpu.fuPool.FUList6.opList0]
 238 type=OpDesc
 239 issueLat=1
 240 opClass=MemRead
 241 opLat=1
 242
 243 [system.cpu.fuPool.FUList6.opList1]
 244 type=OpDesc
 245 issueLat=1
 246 opClass=MemWrite
 247 opLat=1
 248
 249 [system.cpu.fuPool.FUList7]
 250 type=FUDesc
 251 children=opList0
 252 count=1
 253 opList=system.cpu.fuPool.FUList7.opList0
 254
 255 [system.cpu.fuPool.FUList7.opList0]
 256 type=OpDesc
 257 issueLat=3
 258 opClass=IprAccess
 259 opLat=3
 260
 261 [system.cpu.icache]
 262 type=BaseCache
 263 adaptive_compression=false
 264 assoc=2
 265 block_size=64
 266 compressed_bus=false
 267 compression_latency=0
 268 hash_delay=1
 269 latency=1000
 270 lifo=false
 271 max_miss_count=0
 272 mshrs=10
 273 prefetch_access=false
 274 prefetch_cache_check_push=true
 275 prefetch_data_accesses_only=false
 276 prefetch_degree=1
 277 prefetch_latency=10
 278 prefetch_miss=false
 279 prefetch_past_page=false
 280 prefetch_policy=none
 281 prefetch_serial_squash=false
 282 prefetch_use_cpu_id=true
 283 prefetcher_size=100
 284 prioritizeRequests=false
 285 protocol=Null
 286 repl=Null
 287 size=131072
 288 split=false
 289 split_size=0
 290 store_compressed=false
 291 subblock_size=0
 292 tgts_per_mshr=20
 293 trace_addr=0
 294 two_queue=false
 295 write_buffers=8
 296 cpu_side=system.cpu.icache_port
 297 mem_side=system.cpu.toL2Bus.port[0]
 298
 299 [system.cpu.l2cache]
 300 type=BaseCache
 301 adaptive_compression=false
 302 assoc=2
 303 block_size=64
 304 compressed_bus=false
 305 compression_latency=0
 306 hash_delay=1
 307 latency=1000
 308 lifo=false
 309 max_miss_count=0
 310 mshrs=10
 311 prefetch_access=false
 312 prefetch_cache_check_push=true
 313 prefetch_data_accesses_only=false
 314 prefetch_degree=1
 315 prefetch_latency=10
 316 prefetch_miss=false
 317 prefetch_past_page=false
 318 prefetch_policy=none
 319 prefetch_serial_squash=false
 320 prefetch_use_cpu_id=true
 321 prefetcher_size=100
 322 prioritizeRequests=false
 323 protocol=Null
 324 repl=Null
 325 size=2097152
 326 split=false
 327 split_size=0
 328 store_compressed=false
 329 subblock_size=0
 330 tgts_per_mshr=5
 331 trace_addr=0
 332 two_queue=false
 333 write_buffers=8
 334 cpu_side=system.cpu.toL2Bus.port[2]
 335 mem_side=system.membus.port[1]
 336
 337 [system.cpu.toL2Bus]
 338 type=Bus
 339 block_size=64
 340 bus_id=0
 341 clock=1000
 342 responder_set=false
 343 width=64
 344 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 345
 346 [system.cpu.workload]
 347 type=LiveProcess
 348 cmd=gzip input.log 1
 349 cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
 350 egid=100
 351 env=
 352 euid=100
 353 executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
 354 gid=100
 355 input=cin
 356 output=cout
 357 pid=100
 358 ppid=99
 359 system=system
 360 uid=100
 361
 362 [system.membus]
 363 type=Bus
 364 block_size=64
 365 bus_id=0
 366 clock=1000
 367 responder_set=false
 368 width=64
 369 port=system.physmem.port system.cpu.l2cache.mem_side
 370
 371 [system.physmem]
 372 type=PhysicalMemory
 373 file=
 374 latency=1
 375 range=0:134217727
 376 zero=false
 377 port=system.membus.port[0]
 378