tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 dummy=0
   5
   6 [system]
   7 type=System
   8 children=cpu membus physmem
   9 mem_mode=atomic
  10 physmem=system.physmem
  11
  12 [system.cpu]
  13 type=DerivO3CPU
  14 children=dcache fuPool icache l2cache toL2Bus workload
  15 BTBEntries=4096
  16 BTBTagSize=16
  17 LFSTSize=1024
  18 LQEntries=32
  19 RASSize=16
  20 SQEntries=32
  21 SSITSize=1024
  22 activity=0
  23 backComSize=5
  24 choiceCtrBits=2
  25 choicePredictorSize=8192
  26 clock=1
  27 commitToDecodeDelay=1
  28 commitToFetchDelay=1
  29 commitToIEWDelay=1
  30 commitToRenameDelay=1
  31 commitWidth=8
  32 cpu_id=0
  33 decodeToFetchDelay=1
  34 decodeToRenameDelay=1
  35 decodeWidth=8
  36 defer_registration=false
  37 dispatchWidth=8
  38 fetchToDecodeDelay=1
  39 fetchTrapLatency=1
  40 fetchWidth=8
  41 forwardComSize=5
  42 fuPool=system.cpu.fuPool
  43 function_trace=false
  44 function_trace_start=0
  45 globalCtrBits=2
  46 globalHistoryBits=13
  47 globalPredictorSize=8192
  48 iewToCommitDelay=1
  49 iewToDecodeDelay=1
  50 iewToFetchDelay=1
  51 iewToRenameDelay=1
  52 instShiftAmt=2
  53 issueToExecuteDelay=1
  54 issueWidth=8
  55 localCtrBits=2
  56 localHistoryBits=11
  57 localHistoryTableSize=2048
  58 localPredictorSize=2048
  59 max_insts_all_threads=0
  60 max_insts_any_thread=0
  61 max_loads_all_threads=0
  62 max_loads_any_thread=0
  63 numIQEntries=64
  64 numPhysFloatRegs=256
  65 numPhysIntRegs=256
  66 numROBEntries=192
  67 numRobs=1
  68 numThreads=1
  69 phase=0
  70 predType=tournament
  71 progress_interval=0
  72 renameToDecodeDelay=1
  73 renameToFetchDelay=1
  74 renameToIEWDelay=2
  75 renameToROBDelay=1
  76 renameWidth=8
  77 squashWidth=8
  78 system=system
  79 trapLatency=13
  80 wbDepth=1
  81 wbWidth=8
  82 workload=system.cpu.workload
  83 dcache_port=system.cpu.dcache.cpu_side
  84 icache_port=system.cpu.icache.cpu_side
  85
  86 [system.cpu.dcache]
  87 type=BaseCache
  88 adaptive_compression=false
  89 assoc=2
  90 block_size=64
  91 compressed_bus=false
  92 compression_latency=0
  93 hash_delay=1
  94 hit_latency=1
  95 latency=1
  96 lifo=false
  97 max_miss_count=0
  98 mshrs=10
  99 prefetch_access=false
 100 prefetch_cache_check_push=true
 101 prefetch_data_accesses_only=false
 102 prefetch_degree=1
 103 prefetch_latency=10
 104 prefetch_miss=false
 105 prefetch_past_page=false
 106 prefetch_policy=none
 107 prefetch_serial_squash=false
 108 prefetch_use_cpu_id=true
 109 prefetcher_size=100
 110 prioritizeRequests=false
 111 protocol=Null
 112 repl=Null
 113 size=262144
 114 split=false
 115 split_size=0
 116 store_compressed=false
 117 subblock_size=0
 118 tgts_per_mshr=20
 119 trace_addr=0
 120 two_queue=false
 121 write_buffers=8
 122 cpu_side=system.cpu.dcache_port
 123 mem_side=system.cpu.toL2Bus.port[1]
 124
 125 [system.cpu.fuPool]
 126 type=FUPool
 127 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
 128 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
 129
 130 [system.cpu.fuPool.FUList0]
 131 type=FUDesc
 132 children=opList0
 133 count=6
 134 opList=system.cpu.fuPool.FUList0.opList0
 135
 136 [system.cpu.fuPool.FUList0.opList0]
 137 type=OpDesc
 138 issueLat=1
 139 opClass=IntAlu
 140 opLat=1
 141
 142 [system.cpu.fuPool.FUList1]
 143 type=FUDesc
 144 children=opList0 opList1
 145 count=2
 146 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 147
 148 [system.cpu.fuPool.FUList1.opList0]
 149 type=OpDesc
 150 issueLat=1
 151 opClass=IntMult
 152 opLat=3
 153
 154 [system.cpu.fuPool.FUList1.opList1]
 155 type=OpDesc
 156 issueLat=19
 157 opClass=IntDiv
 158 opLat=20
 159
 160 [system.cpu.fuPool.FUList2]
 161 type=FUDesc
 162 children=opList0 opList1 opList2
 163 count=4
 164 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 165
 166 [system.cpu.fuPool.FUList2.opList0]
 167 type=OpDesc
 168 issueLat=1
 169 opClass=FloatAdd
 170 opLat=2
 171
 172 [system.cpu.fuPool.FUList2.opList1]
 173 type=OpDesc
 174 issueLat=1
 175 opClass=FloatCmp
 176 opLat=2
 177
 178 [system.cpu.fuPool.FUList2.opList2]
 179 type=OpDesc
 180 issueLat=1
 181 opClass=FloatCvt
 182 opLat=2
 183
 184 [system.cpu.fuPool.FUList3]
 185 type=FUDesc
 186 children=opList0 opList1 opList2
 187 count=2
 188 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 189
 190 [system.cpu.fuPool.FUList3.opList0]
 191 type=OpDesc
 192 issueLat=1
 193 opClass=FloatMult
 194 opLat=4
 195
 196 [system.cpu.fuPool.FUList3.opList1]
 197 type=OpDesc
 198 issueLat=12
 199 opClass=FloatDiv
 200 opLat=12
 201
 202 [system.cpu.fuPool.FUList3.opList2]
 203 type=OpDesc
 204 issueLat=24
 205 opClass=FloatSqrt
 206 opLat=24
 207
 208 [system.cpu.fuPool.FUList4]
 209 type=FUDesc
 210 children=opList0
 211 count=0
 212 opList=system.cpu.fuPool.FUList4.opList0
 213
 214 [system.cpu.fuPool.FUList4.opList0]
 215 type=OpDesc
 216 issueLat=1
 217 opClass=MemRead
 218 opLat=1
 219
 220 [system.cpu.fuPool.FUList5]
 221 type=FUDesc
 222 children=opList0
 223 count=0
 224 opList=system.cpu.fuPool.FUList5.opList0
 225
 226 [system.cpu.fuPool.FUList5.opList0]
 227 type=OpDesc
 228 issueLat=1
 229 opClass=MemWrite
 230 opLat=1
 231
 232 [system.cpu.fuPool.FUList6]
 233 type=FUDesc
 234 children=opList0 opList1
 235 count=4
 236 opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
 237
 238 [system.cpu.fuPool.FUList6.opList0]
 239 type=OpDesc
 240 issueLat=1
 241 opClass=MemRead
 242 opLat=1
 243
 244 [system.cpu.fuPool.FUList6.opList1]
 245 type=OpDesc
 246 issueLat=1
 247 opClass=MemWrite
 248 opLat=1
 249
 250 [system.cpu.fuPool.FUList7]
 251 type=FUDesc
 252 children=opList0
 253 count=1
 254 opList=system.cpu.fuPool.FUList7.opList0
 255
 256 [system.cpu.fuPool.FUList7.opList0]
 257 type=OpDesc
 258 issueLat=3
 259 opClass=IprAccess
 260 opLat=3
 261
 262 [system.cpu.icache]
 263 type=BaseCache
 264 adaptive_compression=false
 265 assoc=2
 266 block_size=64
 267 compressed_bus=false
 268 compression_latency=0
 269 hash_delay=1
 270 hit_latency=1
 271 latency=1
 272 lifo=false
 273 max_miss_count=0
 274 mshrs=10
 275 prefetch_access=false
 276 prefetch_cache_check_push=true
 277 prefetch_data_accesses_only=false
 278 prefetch_degree=1
 279 prefetch_latency=10
 280 prefetch_miss=false
 281 prefetch_past_page=false
 282 prefetch_policy=none
 283 prefetch_serial_squash=false
 284 prefetch_use_cpu_id=true
 285 prefetcher_size=100
 286 prioritizeRequests=false
 287 protocol=Null
 288 repl=Null
 289 size=131072
 290 split=false
 291 split_size=0
 292 store_compressed=false
 293 subblock_size=0
 294 tgts_per_mshr=20
 295 trace_addr=0
 296 two_queue=false
 297 write_buffers=8
 298 cpu_side=system.cpu.icache_port
 299 mem_side=system.cpu.toL2Bus.port[0]
 300
 301 [system.cpu.l2cache]
 302 type=BaseCache
 303 adaptive_compression=false
 304 assoc=2
 305 block_size=64
 306 compressed_bus=false
 307 compression_latency=0
 308 hash_delay=1
 309 hit_latency=1
 310 latency=1
 311 lifo=false
 312 max_miss_count=0
 313 mshrs=10
 314 prefetch_access=false
 315 prefetch_cache_check_push=true
 316 prefetch_data_accesses_only=false
 317 prefetch_degree=1
 318 prefetch_latency=10
 319 prefetch_miss=false
 320 prefetch_past_page=false
 321 prefetch_policy=none
 322 prefetch_serial_squash=false
 323 prefetch_use_cpu_id=true
 324 prefetcher_size=100
 325 prioritizeRequests=false
 326 protocol=Null
 327 repl=Null
 328 size=2097152
 329 split=false
 330 split_size=0
 331 store_compressed=false
 332 subblock_size=0
 333 tgts_per_mshr=5
 334 trace_addr=0
 335 two_queue=false
 336 write_buffers=8
 337 cpu_side=system.cpu.toL2Bus.port[2]
 338 mem_side=system.membus.port[1]
 339
 340 [system.cpu.toL2Bus]
 341 type=Bus
 342 bus_id=0
 343 clock=1000
 344 responder_set=false
 345 width=64
 346 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 347
 348 [system.cpu.workload]
 349 type=LiveProcess
 350 cmd=gzip input.log 1
 351 cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
 352 egid=100
 353 env=
 354 euid=100
 355 executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
 356 gid=100
 357 input=cin
 358 output=cout
 359 pid=100
 360 ppid=99
 361 system=system
 362 uid=100
 363
 364 [system.membus]
 365 type=Bus
 366 bus_id=0
 367 clock=1000
 368 responder_set=false
 369 width=64
 370 port=system.physmem.port system.cpu.l2cache.mem_side
 371
 372 [system.physmem]
 373 type=PhysicalMemory
 374 file=
 375 latency=1
 376 range=0:134217727
 377 zero=false
 378 port=system.membus.port[0]
 379