tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 dummy=0
   5
   6 [system]
   7 type=System
   8 children=cpu membus physmem
   9 mem_mode=atomic
  10 physmem=system.physmem
  11
  12 [system.cpu]
  13 type=DerivO3CPU
  14 children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
  15 BTBEntries=4096
  16 BTBTagSize=16
  17 LFSTSize=1024
  18 LQEntries=32
  19 RASSize=16
  20 SQEntries=32
  21 SSITSize=1024
  22 activity=0
  23 backComSize=5
  24 cachePorts=200
  25 checker=Null
  26 choiceCtrBits=2
  27 choicePredictorSize=8192
  28 clock=500
  29 commitToDecodeDelay=1
  30 commitToFetchDelay=1
  31 commitToIEWDelay=1
  32 commitToRenameDelay=1
  33 commitWidth=8
  34 cpu_id=0
  35 decodeToFetchDelay=1
  36 decodeToRenameDelay=1
  37 decodeWidth=8
  38 defer_registration=false
  39 dispatchWidth=8
  40 do_checkpoint_insts=true
  41 do_statistics_insts=true
  42 dtb=system.cpu.dtb
  43 fetchToDecodeDelay=1
  44 fetchTrapLatency=1
  45 fetchWidth=8
  46 forwardComSize=5
  47 fuPool=system.cpu.fuPool
  48 function_trace=false
  49 function_trace_start=0
  50 globalCtrBits=2
  51 globalHistoryBits=13
  52 globalPredictorSize=8192
  53 iewToCommitDelay=1
  54 iewToDecodeDelay=1
  55 iewToFetchDelay=1
  56 iewToRenameDelay=1
  57 instShiftAmt=2
  58 issueToExecuteDelay=1
  59 issueWidth=8
  60 itb=system.cpu.itb
  61 localCtrBits=2
  62 localHistoryBits=11
  63 localHistoryTableSize=2048
  64 localPredictorSize=2048
  65 max_insts_all_threads=0
  66 max_insts_any_thread=0
  67 max_loads_all_threads=0
  68 max_loads_any_thread=0
  69 numIQEntries=64
  70 numPhysFloatRegs=256
  71 numPhysIntRegs=256
  72 numROBEntries=192
  73 numRobs=1
  74 numThreads=1
  75 phase=0
  76 predType=tournament
  77 progress_interval=0
  78 renameToDecodeDelay=1
  79 renameToFetchDelay=1
  80 renameToIEWDelay=2
  81 renameToROBDelay=1
  82 renameWidth=8
  83 smtCommitPolicy=RoundRobin
  84 smtFetchPolicy=SingleThread
  85 smtIQPolicy=Partitioned
  86 smtIQThreshold=100
  87 smtLSQPolicy=Partitioned
  88 smtLSQThreshold=100
  89 smtNumFetchingThreads=1
  90 smtROBPolicy=Partitioned
  91 smtROBThreshold=100
  92 squashWidth=8
  93 system=system
  94 tracer=system.cpu.tracer
  95 trapLatency=13
  96 wbDepth=1
  97 wbWidth=8
  98 workload=system.cpu.workload
  99 dcache_port=system.cpu.dcache.cpu_side
 100 icache_port=system.cpu.icache.cpu_side
 101
 102 [system.cpu.dcache]
 103 type=BaseCache
 104 addr_range=0:18446744073709551615
 105 assoc=2
 106 block_size=64
 107 forward_snoops=true
 108 hash_delay=1
 109 latency=1000
 110 max_miss_count=0
 111 mshrs=10
 112 num_cpus=1
 113 prefetch_data_accesses_only=false
 114 prefetch_degree=1
 115 prefetch_latency=10000
 116 prefetch_on_access=false
 117 prefetch_past_page=false
 118 prefetch_policy=none
 119 prefetch_serial_squash=false
 120 prefetch_use_cpu_id=true
 121 prefetcher_size=100
 122 prioritizeRequests=false
 123 repl=Null
 124 size=262144
 125 subblock_size=0
 126 tgts_per_mshr=20
 127 trace_addr=0
 128 two_queue=false
 129 write_buffers=8
 130 cpu_side=system.cpu.dcache_port
 131 mem_side=system.cpu.toL2Bus.port[1]
 132
 133 [system.cpu.dtb]
 134 type=AlphaTLB
 135 size=64
 136
 137 [system.cpu.fuPool]
 138 type=FUPool
 139 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
 140 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
 141
 142 [system.cpu.fuPool.FUList0]
 143 type=FUDesc
 144 children=opList
 145 count=6
 146 opList=system.cpu.fuPool.FUList0.opList
 147
 148 [system.cpu.fuPool.FUList0.opList]
 149 type=OpDesc
 150 issueLat=1
 151 opClass=IntAlu
 152 opLat=1
 153
 154 [system.cpu.fuPool.FUList1]
 155 type=FUDesc
 156 children=opList0 opList1
 157 count=2
 158 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 159
 160 [system.cpu.fuPool.FUList1.opList0]
 161 type=OpDesc
 162 issueLat=1
 163 opClass=IntMult
 164 opLat=3
 165
 166 [system.cpu.fuPool.FUList1.opList1]
 167 type=OpDesc
 168 issueLat=19
 169 opClass=IntDiv
 170 opLat=20
 171
 172 [system.cpu.fuPool.FUList2]
 173 type=FUDesc
 174 children=opList0 opList1 opList2
 175 count=4
 176 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 177
 178 [system.cpu.fuPool.FUList2.opList0]
 179 type=OpDesc
 180 issueLat=1
 181 opClass=FloatAdd
 182 opLat=2
 183
 184 [system.cpu.fuPool.FUList2.opList1]
 185 type=OpDesc
 186 issueLat=1
 187 opClass=FloatCmp
 188 opLat=2
 189
 190 [system.cpu.fuPool.FUList2.opList2]
 191 type=OpDesc
 192 issueLat=1
 193 opClass=FloatCvt
 194 opLat=2
 195
 196 [system.cpu.fuPool.FUList3]
 197 type=FUDesc
 198 children=opList0 opList1 opList2
 199 count=2
 200 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 201
 202 [system.cpu.fuPool.FUList3.opList0]
 203 type=OpDesc
 204 issueLat=1
 205 opClass=FloatMult
 206 opLat=4
 207
 208 [system.cpu.fuPool.FUList3.opList1]
 209 type=OpDesc
 210 issueLat=12
 211 opClass=FloatDiv
 212 opLat=12
 213
 214 [system.cpu.fuPool.FUList3.opList2]
 215 type=OpDesc
 216 issueLat=24
 217 opClass=FloatSqrt
 218 opLat=24
 219
 220 [system.cpu.fuPool.FUList4]
 221 type=FUDesc
 222 children=opList
 223 count=0
 224 opList=system.cpu.fuPool.FUList4.opList
 225
 226 [system.cpu.fuPool.FUList4.opList]
 227 type=OpDesc
 228 issueLat=1
 229 opClass=MemRead
 230 opLat=1
 231
 232 [system.cpu.fuPool.FUList5]
 233 type=FUDesc
 234 children=opList
 235 count=0
 236 opList=system.cpu.fuPool.FUList5.opList
 237
 238 [system.cpu.fuPool.FUList5.opList]
 239 type=OpDesc
 240 issueLat=1
 241 opClass=MemWrite
 242 opLat=1
 243
 244 [system.cpu.fuPool.FUList6]
 245 type=FUDesc
 246 children=opList0 opList1
 247 count=4
 248 opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
 249
 250 [system.cpu.fuPool.FUList6.opList0]
 251 type=OpDesc
 252 issueLat=1
 253 opClass=MemRead
 254 opLat=1
 255
 256 [system.cpu.fuPool.FUList6.opList1]
 257 type=OpDesc
 258 issueLat=1
 259 opClass=MemWrite
 260 opLat=1
 261
 262 [system.cpu.fuPool.FUList7]
 263 type=FUDesc
 264 children=opList
 265 count=1
 266 opList=system.cpu.fuPool.FUList7.opList
 267
 268 [system.cpu.fuPool.FUList7.opList]
 269 type=OpDesc
 270 issueLat=3
 271 opClass=IprAccess
 272 opLat=3
 273
 274 [system.cpu.icache]
 275 type=BaseCache
 276 addr_range=0:18446744073709551615
 277 assoc=2
 278 block_size=64
 279 forward_snoops=true
 280 hash_delay=1
 281 latency=1000
 282 max_miss_count=0
 283 mshrs=10
 284 num_cpus=1
 285 prefetch_data_accesses_only=false
 286 prefetch_degree=1
 287 prefetch_latency=10000
 288 prefetch_on_access=false
 289 prefetch_past_page=false
 290 prefetch_policy=none
 291 prefetch_serial_squash=false
 292 prefetch_use_cpu_id=true
 293 prefetcher_size=100
 294 prioritizeRequests=false
 295 repl=Null
 296 size=131072
 297 subblock_size=0
 298 tgts_per_mshr=20
 299 trace_addr=0
 300 two_queue=false
 301 write_buffers=8
 302 cpu_side=system.cpu.icache_port
 303 mem_side=system.cpu.toL2Bus.port[0]
 304
 305 [system.cpu.itb]
 306 type=AlphaTLB
 307 size=48
 308
 309 [system.cpu.l2cache]
 310 type=BaseCache
 311 addr_range=0:18446744073709551615
 312 assoc=2
 313 block_size=64
 314 forward_snoops=true
 315 hash_delay=1
 316 latency=1000
 317 max_miss_count=0
 318 mshrs=10
 319 num_cpus=1
 320 prefetch_data_accesses_only=false
 321 prefetch_degree=1
 322 prefetch_latency=10000
 323 prefetch_on_access=false
 324 prefetch_past_page=false
 325 prefetch_policy=none
 326 prefetch_serial_squash=false
 327 prefetch_use_cpu_id=true
 328 prefetcher_size=100
 329 prioritizeRequests=false
 330 repl=Null
 331 size=2097152
 332 subblock_size=0
 333 tgts_per_mshr=5
 334 trace_addr=0
 335 two_queue=false
 336 write_buffers=8
 337 cpu_side=system.cpu.toL2Bus.port[2]
 338 mem_side=system.membus.port[1]
 339
 340 [system.cpu.toL2Bus]
 341 type=Bus
 342 block_size=64
 343 bus_id=0
 344 clock=1000
 345 header_cycles=1
 346 responder_set=false
 347 width=64
 348 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 349
 350 [system.cpu.tracer]
 351 type=ExeTracer
 352
 353 [system.cpu.workload]
 354 type=LiveProcess
 355 cmd=gzip input.log 1
 356 cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
 357 egid=100
 358 env=
 359 errout=cerr
 360 euid=100
 361 executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip
 362 gid=100
 363 input=cin
 364 max_stack_size=67108864
 365 output=cout
 366 pid=100
 367 ppid=99
 368 simpoint=0
 369 system=system
 370 uid=100
 371
 372 [system.membus]
 373 type=Bus
 374 block_size=64
 375 bus_id=0
 376 clock=1000
 377 header_cycles=1
 378 responder_set=false
 379 width=64
 380 port=system.physmem.port[0] system.cpu.l2cache.mem_side
 381
 382 [system.physmem]
 383 type=PhysicalMemory
 384 file=
 385 latency=30000
 386 latency_var=0
 387 null=false
 388 range=0:134217727
 389 zero=false
 390 port=system.membus.port[0]
 391