2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 264030 # Simulator instruction rate (inst/s)
4 host_mem_usage 193748 # Number of bytes of host memory used
5 host_seconds 2142.00 # Real time elapsed on the host
6 host_tick_rate 77206740 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 565552443 # Number of instructions simulated
9 sim_seconds 0.165377 # Number of seconds simulated
10 sim_ticks 165376986500 # Number of ticks simulated
11 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
12 system.cpu.BPredUnit.BTBHits 63929788 # Number of BTB hits
13 system.cpu.BPredUnit.BTBLookups 71429024 # Number of BTB lookups
14 system.cpu.BPredUnit.RASInCorrect 197 # Number of incorrect RAS predictions.
15 system.cpu.BPredUnit.condIncorrect 4120838 # Number of conditional branches incorrect
16 system.cpu.BPredUnit.condPredicted 70454375 # Number of conditional branches predicted
17 system.cpu.BPredUnit.lookups 76396550 # Number of BP lookups
18 system.cpu.BPredUnit.usedRAS 1676108 # Number of times the RAS was used to get a target.
19 system.cpu.commit.COM:branches 62547159 # Number of branches committed
20 system.cpu.commit.COM:bw_lim_events 20033371 # number cycles where commit BW limit reached
21 system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
22 system.cpu.commit.COM:committed_per_cycle::samples 320816297 # Number of insts commited each cycle
23 system.cpu.commit.COM:committed_per_cycle::mean 1.876017 # Number of insts commited each cycle
24 system.cpu.commit.COM:committed_per_cycle::stdev 2.306184 # Number of insts commited each cycle
25 system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
26 system.cpu.commit.COM:committed_per_cycle::0 102501444 31.95% 31.95% # Number of insts commited each cycle
27 system.cpu.commit.COM:committed_per_cycle::1 105613320 32.92% 64.87% # Number of insts commited each cycle
28 system.cpu.commit.COM:committed_per_cycle::2 36739083 11.45% 76.32% # Number of insts commited each cycle
29 system.cpu.commit.COM:committed_per_cycle::3 11050019 3.44% 79.77% # Number of insts commited each cycle
30 system.cpu.commit.COM:committed_per_cycle::4 10174748 3.17% 82.94% # Number of insts commited each cycle
31 system.cpu.commit.COM:committed_per_cycle::5 21768321 6.79% 89.72% # Number of insts commited each cycle
32 system.cpu.commit.COM:committed_per_cycle::6 10744082 3.35% 93.07% # Number of insts commited each cycle
33 system.cpu.commit.COM:committed_per_cycle::7 2191909 0.68% 93.76% # Number of insts commited each cycle
34 system.cpu.commit.COM:committed_per_cycle::8 20033371 6.24% 100.00% # Number of insts commited each cycle
35 system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
36 system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
37 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
38 system.cpu.commit.COM:committed_per_cycle::total 320816297 # Number of insts commited each cycle
39 system.cpu.commit.COM:count 601856963 # Number of instructions committed
40 system.cpu.commit.COM:loads 115049510 # Number of loads committed
41 system.cpu.commit.COM:membars 0 # Number of memory barriers committed
42 system.cpu.commit.COM:refs 154862033 # Number of memory references committed
43 system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
44 system.cpu.commit.branchMispredicts 4120001 # The number of times a branch was mispredicted
45 system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
46 system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
47 system.cpu.commit.commitSquashedInsts 61749735 # The number of squashed insts skipped by commit
48 system.cpu.committedInsts 565552443 # Number of Instructions Simulated
49 system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
50 system.cpu.cpi 0.584833 # CPI: Cycles Per Instruction
51 system.cpu.cpi_total 0.584833 # CPI: Total CPI of All Threads
52 system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses)
53 system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits
54 system.cpu.dcache.ReadReq_accesses 115012927 # number of ReadReq accesses(hits+misses)
55 system.cpu.dcache.ReadReq_avg_miss_latency 14990.355830 # average ReadReq miss latency
56 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7392.342173 # average ReadReq mshr miss latency
57 system.cpu.dcache.ReadReq_hits 114228619 # number of ReadReq hits
58 system.cpu.dcache.ReadReq_miss_latency 11757056000 # number of ReadReq miss cycles
59 system.cpu.dcache.ReadReq_miss_rate 0.006819 # miss rate for ReadReq accesses
60 system.cpu.dcache.ReadReq_misses 784308 # number of ReadReq misses
61 system.cpu.dcache.ReadReq_mshr_hits 566126 # number of ReadReq MSHR hits
62 system.cpu.dcache.ReadReq_mshr_miss_latency 1612876000 # number of ReadReq MSHR miss cycles
63 system.cpu.dcache.ReadReq_mshr_miss_rate 0.001897 # mshr miss rate for ReadReq accesses
64 system.cpu.dcache.ReadReq_mshr_misses 218182 # number of ReadReq MSHR misses
65 system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
66 system.cpu.dcache.WriteReq_avg_miss_latency 14906.098057 # average WriteReq miss latency
67 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11053.696113 # average WriteReq mshr miss latency
68 system.cpu.dcache.WriteReq_hits 38301940 # number of WriteReq hits
69 system.cpu.dcache.WriteReq_miss_latency 17132785891 # number of WriteReq miss cycles
70 system.cpu.dcache.WriteReq_miss_rate 0.029134 # miss rate for WriteReq accesses
71 system.cpu.dcache.WriteReq_misses 1149381 # number of WriteReq misses
72 system.cpu.dcache.WriteReq_mshr_hits 892463 # number of WriteReq MSHR hits
73 system.cpu.dcache.WriteReq_mshr_miss_latency 2839893498 # number of WriteReq MSHR miss cycles
74 system.cpu.dcache.WriteReq_mshr_miss_rate 0.006512 # mshr miss rate for WriteReq accesses
75 system.cpu.dcache.WriteReq_mshr_misses 256918 # number of WriteReq MSHR misses
76 system.cpu.dcache.avg_blocked_cycles::no_mshrs 6663.699115 # average number of cycles each access was blocked
77 system.cpu.dcache.avg_blocked_cycles::no_targets 20363.636364 # average number of cycles each access was blocked
78 system.cpu.dcache.avg_refs 321.049385 # Average number of references to valid blocks.
79 system.cpu.dcache.blocked::no_mshrs 113 # number of cycles access was blocked
80 system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
81 system.cpu.dcache.blocked_cycles::no_mshrs 752998 # number of cycles access was blocked
82 system.cpu.dcache.blocked_cycles::no_targets 224000 # number of cycles access was blocked
83 system.cpu.dcache.cache_copies 0 # number of cache copies performed
84 system.cpu.dcache.demand_accesses 154464248 # number of demand (read+write) accesses
85 system.cpu.dcache.demand_avg_miss_latency 14940.273173 # average overall miss latency
86 system.cpu.dcache.demand_avg_mshr_miss_latency 9372.278463 # average overall mshr miss latency
87 system.cpu.dcache.demand_hits 152530559 # number of demand (read+write) hits
88 system.cpu.dcache.demand_miss_latency 28889841891 # number of demand (read+write) miss cycles
89 system.cpu.dcache.demand_miss_rate 0.012519 # miss rate for demand accesses
90 system.cpu.dcache.demand_misses 1933689 # number of demand (read+write) misses
91 system.cpu.dcache.demand_mshr_hits 1458589 # number of demand (read+write) MSHR hits
92 system.cpu.dcache.demand_mshr_miss_latency 4452769498 # number of demand (read+write) MSHR miss cycles
93 system.cpu.dcache.demand_mshr_miss_rate 0.003076 # mshr miss rate for demand accesses
94 system.cpu.dcache.demand_mshr_misses 475100 # number of demand (read+write) MSHR misses
95 system.cpu.dcache.fast_writes 0 # number of fast writes performed
96 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
97 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
98 system.cpu.dcache.occ_%::0 0.999558 # Average percentage of cache occupancy
99 system.cpu.dcache.occ_blocks::0 4094.188781 # Average occupied blocks per context
100 system.cpu.dcache.overall_accesses 154464248 # number of overall (read+write) accesses
101 system.cpu.dcache.overall_avg_miss_latency 14940.273173 # average overall miss latency
102 system.cpu.dcache.overall_avg_mshr_miss_latency 9372.278463 # average overall mshr miss latency
103 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
104 system.cpu.dcache.overall_hits 152530559 # number of overall hits
105 system.cpu.dcache.overall_miss_latency 28889841891 # number of overall miss cycles
106 system.cpu.dcache.overall_miss_rate 0.012519 # miss rate for overall accesses
107 system.cpu.dcache.overall_misses 1933689 # number of overall misses
108 system.cpu.dcache.overall_mshr_hits 1458589 # number of overall MSHR hits
109 system.cpu.dcache.overall_mshr_miss_latency 4452769498 # number of overall MSHR miss cycles
110 system.cpu.dcache.overall_mshr_miss_rate 0.003076 # mshr miss rate for overall accesses
111 system.cpu.dcache.overall_mshr_misses 475100 # number of overall MSHR misses
112 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
113 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
114 system.cpu.dcache.replacements 471004 # number of replacements
115 system.cpu.dcache.sampled_refs 475100 # Sample count of references to valid blocks.
116 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
117 system.cpu.dcache.tagsinuse 4094.188781 # Cycle average of tags in use
118 system.cpu.dcache.total_refs 152530563 # Total number of references to valid blocks.
119 system.cpu.dcache.warmup_cycle 126404000 # Cycle when the warmup percentage was hit.
120 system.cpu.dcache.writebacks 423151 # number of writebacks
121 system.cpu.decode.DECODE:BlockedCycles 48113828 # Number of cycles decode is blocked
122 system.cpu.decode.DECODE:BranchMispred 871 # Number of times decode detected a branch misprediction
123 system.cpu.decode.DECODE:BranchResolved 4177876 # Number of times decode resolved a branch
124 system.cpu.decode.DECODE:DecodedInsts 689990711 # Number of instructions handled by decode
125 system.cpu.decode.DECODE:IdleCycles 144277716 # Number of cycles decode is idle
126 system.cpu.decode.DECODE:RunCycles 122985866 # Number of cycles decode is running
127 system.cpu.decode.DECODE:SquashCycles 9844039 # Number of cycles decode is squashing
128 system.cpu.decode.DECODE:SquashedInsts 3043 # Number of squashed instructions handled by decode
129 system.cpu.decode.DECODE:UnblockCycles 5438887 # Number of cycles decode is unblocking
130 system.cpu.dtb.data_accesses 163094811 # DTB accesses
131 system.cpu.dtb.data_acv 0 # DTB access violations
132 system.cpu.dtb.data_hits 163045966 # DTB hits
133 system.cpu.dtb.data_misses 48845 # DTB misses
134 system.cpu.dtb.fetch_accesses 0 # ITB accesses
135 system.cpu.dtb.fetch_acv 0 # ITB acv
136 system.cpu.dtb.fetch_hits 0 # ITB hits
137 system.cpu.dtb.fetch_misses 0 # ITB misses
138 system.cpu.dtb.read_accesses 122278185 # DTB read accesses
139 system.cpu.dtb.read_acv 0 # DTB read access violations
140 system.cpu.dtb.read_hits 122255138 # DTB read hits
141 system.cpu.dtb.read_misses 23047 # DTB read misses
142 system.cpu.dtb.write_accesses 40816626 # DTB write accesses
143 system.cpu.dtb.write_acv 0 # DTB write access violations
144 system.cpu.dtb.write_hits 40790828 # DTB write hits
145 system.cpu.dtb.write_misses 25798 # DTB write misses
146 system.cpu.fetch.Branches 76396550 # Number of branches that fetch encountered
147 system.cpu.fetch.CacheLines 65649275 # Number of cache lines fetched
148 system.cpu.fetch.Cycles 195872330 # Number of cycles fetch has run and was not squashing or blocked
149 system.cpu.fetch.IcacheSquashes 1325100 # Number of outstanding Icache misses that were squashed
150 system.cpu.fetch.Insts 699185184 # Number of instructions fetch has processed
151 system.cpu.fetch.SquashCycles 4170349 # Number of cycles fetch has spent squashing
152 system.cpu.fetch.branchRate 0.230977 # Number of branch fetches per cycle
153 system.cpu.fetch.icacheStallCycles 65649275 # Number of cycles fetch is stalled on an Icache miss
154 system.cpu.fetch.predictedBranches 65605896 # Number of branches that fetch has predicted taken
155 system.cpu.fetch.rate 2.113913 # Number of inst fetches per cycle
156 system.cpu.fetch.rateDist::samples 330660336 # Number of instructions fetched each cycle (Total)
157 system.cpu.fetch.rateDist::mean 2.114512 # Number of instructions fetched each cycle (Total)
158 system.cpu.fetch.rateDist::stdev 3.085107 # Number of instructions fetched each cycle (Total)
159 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
160 system.cpu.fetch.rateDist::0 200437318 60.62% 60.62% # Number of instructions fetched each cycle (Total)
161 system.cpu.fetch.rateDist::1 10372140 3.14% 63.75% # Number of instructions fetched each cycle (Total)
162 system.cpu.fetch.rateDist::2 15863919 4.80% 68.55% # Number of instructions fetched each cycle (Total)
163 system.cpu.fetch.rateDist::3 13948828 4.22% 72.77% # Number of instructions fetched each cycle (Total)
164 system.cpu.fetch.rateDist::4 12077397 3.65% 76.42% # Number of instructions fetched each cycle (Total)
165 system.cpu.fetch.rateDist::5 13850642 4.19% 80.61% # Number of instructions fetched each cycle (Total)
166 system.cpu.fetch.rateDist::6 5888624 1.78% 82.39% # Number of instructions fetched each cycle (Total)
167 system.cpu.fetch.rateDist::7 3427564 1.04% 83.43% # Number of instructions fetched each cycle (Total)
168 system.cpu.fetch.rateDist::8 54793904 16.57% 100.00% # Number of instructions fetched each cycle (Total)
169 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
170 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
171 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
172 system.cpu.fetch.rateDist::total 330660336 # Number of instructions fetched each cycle (Total)
173 system.cpu.icache.ReadReq_accesses 65649275 # number of ReadReq accesses(hits+misses)
174 system.cpu.icache.ReadReq_avg_miss_latency 36269.949066 # average ReadReq miss latency
175 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35524.725275 # average ReadReq mshr miss latency
176 system.cpu.icache.ReadReq_hits 65648097 # number of ReadReq hits
177 system.cpu.icache.ReadReq_miss_latency 42726000 # number of ReadReq miss cycles
178 system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
179 system.cpu.icache.ReadReq_misses 1178 # number of ReadReq misses
180 system.cpu.icache.ReadReq_mshr_hits 268 # number of ReadReq MSHR hits
181 system.cpu.icache.ReadReq_mshr_miss_latency 32327500 # number of ReadReq MSHR miss cycles
182 system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
183 system.cpu.icache.ReadReq_mshr_misses 910 # number of ReadReq MSHR misses
184 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
185 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
186 system.cpu.icache.avg_refs 72140.765934 # Average number of references to valid blocks.
187 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
188 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
189 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
190 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
191 system.cpu.icache.cache_copies 0 # number of cache copies performed
192 system.cpu.icache.demand_accesses 65649275 # number of demand (read+write) accesses
193 system.cpu.icache.demand_avg_miss_latency 36269.949066 # average overall miss latency
194 system.cpu.icache.demand_avg_mshr_miss_latency 35524.725275 # average overall mshr miss latency
195 system.cpu.icache.demand_hits 65648097 # number of demand (read+write) hits
196 system.cpu.icache.demand_miss_latency 42726000 # number of demand (read+write) miss cycles
197 system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
198 system.cpu.icache.demand_misses 1178 # number of demand (read+write) misses
199 system.cpu.icache.demand_mshr_hits 268 # number of demand (read+write) MSHR hits
200 system.cpu.icache.demand_mshr_miss_latency 32327500 # number of demand (read+write) MSHR miss cycles
201 system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
202 system.cpu.icache.demand_mshr_misses 910 # number of demand (read+write) MSHR misses
203 system.cpu.icache.fast_writes 0 # number of fast writes performed
204 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
205 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
206 system.cpu.icache.occ_%::0 0.378879 # Average percentage of cache occupancy
207 system.cpu.icache.occ_blocks::0 775.944948 # Average occupied blocks per context
208 system.cpu.icache.overall_accesses 65649275 # number of overall (read+write) accesses
209 system.cpu.icache.overall_avg_miss_latency 36269.949066 # average overall miss latency
210 system.cpu.icache.overall_avg_mshr_miss_latency 35524.725275 # average overall mshr miss latency
211 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
212 system.cpu.icache.overall_hits 65648097 # number of overall hits
213 system.cpu.icache.overall_miss_latency 42726000 # number of overall miss cycles
214 system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
215 system.cpu.icache.overall_misses 1178 # number of overall misses
216 system.cpu.icache.overall_mshr_hits 268 # number of overall MSHR hits
217 system.cpu.icache.overall_mshr_miss_latency 32327500 # number of overall MSHR miss cycles
218 system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
219 system.cpu.icache.overall_mshr_misses 910 # number of overall MSHR misses
220 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
221 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
222 system.cpu.icache.replacements 32 # number of replacements
223 system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks.
224 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
225 system.cpu.icache.tagsinuse 775.944948 # Cycle average of tags in use
226 system.cpu.icache.total_refs 65648097 # Total number of references to valid blocks.
227 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
228 system.cpu.icache.writebacks 0 # number of writebacks
229 system.cpu.idleCycles 93638 # Total number of cycles that the CPU has spent unscheduled due to idling
230 system.cpu.iew.EXEC:branches 67433622 # Number of branches executed
231 system.cpu.iew.EXEC:nop 43234709 # number of nop insts executed
232 system.cpu.iew.EXEC:rate 1.811577 # Inst execution rate
233 system.cpu.iew.EXEC:refs 164032675 # number of memory reference insts executed
234 system.cpu.iew.EXEC:stores 41211382 # Number of stores executed
235 system.cpu.iew.EXEC:swp 0 # number of swp insts executed
236 system.cpu.iew.WB:consumers 492720055 # num instructions consuming a value
237 system.cpu.iew.WB:count 595983189 # cumulative count of insts written-back
238 system.cpu.iew.WB:fanout 0.807592 # average fanout of values written-back
239 system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
240 system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
241 system.cpu.iew.WB:producers 397916939 # num instructions producing a value
242 system.cpu.iew.WB:rate 1.801893 # insts written-back per cycle
243 system.cpu.iew.WB:sent 597091543 # cumulative count of insts sent to commit
244 system.cpu.iew.branchMispredicts 4603878 # Number of branch mispredicts detected at execute
245 system.cpu.iew.iewBlockCycles 1505457 # Number of cycles IEW is blocking
246 system.cpu.iew.iewDispLoadInsts 126939472 # Number of dispatched load instructions
247 system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions
248 system.cpu.iew.iewDispSquashedInsts 3143406 # Number of squashed instructions skipped by dispatch
249 system.cpu.iew.iewDispStoreInsts 43126164 # Number of dispatched store instructions
250 system.cpu.iew.iewDispatchedInsts 663744184 # Number of instructions dispatched to IQ
251 system.cpu.iew.iewExecLoadInsts 122821293 # Number of load instructions executed
252 system.cpu.iew.iewExecSquashedInsts 6299898 # Number of squashed instructions skipped in execute
253 system.cpu.iew.iewExecutedInsts 599186314 # Number of executed instructions
254 system.cpu.iew.iewIQFullEvents 2121 # Number of times the IQ has become full, causing a stall
255 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
256 system.cpu.iew.iewLSQFullEvents 28444 # Number of times the LSQ has become full, causing a stall
257 system.cpu.iew.iewSquashCycles 9844039 # Number of cycles IEW is squashing
258 system.cpu.iew.iewUnblockCycles 43665 # Number of cycles IEW is unblocking
259 system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
260 system.cpu.iew.lsq.thread.0.cacheBlocked 720 # Number of times an access to memory failed due to the cache being blocked
261 system.cpu.iew.lsq.thread.0.forwLoads 7235686 # Number of loads that had data forwarded from stores
262 system.cpu.iew.lsq.thread.0.ignoredResponses 12544 # Number of memory responses ignored because the instruction is squashed
263 system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
264 system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
265 system.cpu.iew.lsq.thread.0.memOrderViolation 71476 # Number of memory ordering violations
266 system.cpu.iew.lsq.thread.0.rescheduledLoads 5929 # Number of loads that were rescheduled
267 system.cpu.iew.lsq.thread.0.squashedLoads 11889962 # Number of loads squashed
268 system.cpu.iew.lsq.thread.0.squashedStores 3313641 # Number of stores squashed
269 system.cpu.iew.memOrderViolationEvents 71476 # Number of memory order violations
270 system.cpu.iew.predictedNotTakenIncorrect 943110 # Number of branches that were predicted not taken incorrectly
271 system.cpu.iew.predictedTakenIncorrect 3660768 # Number of branches that were predicted taken incorrectly
272 system.cpu.ipc 1.709889 # IPC: Instructions Per Cycle
273 system.cpu.ipc_total 1.709889 # IPC: Total IPC of All Threads
274 system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
275 system.cpu.iq.ISSUE:FU_type_0::IntAlu 438748901 72.46% 72.46% # Type of FU issued
276 system.cpu.iq.ISSUE:FU_type_0::IntMult 6682 0.00% 72.46% # Type of FU issued
277 system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.46% # Type of FU issued
278 system.cpu.iq.ISSUE:FU_type_0::FloatAdd 29 0.00% 72.46% # Type of FU issued
279 system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.46% # Type of FU issued
280 system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.46% # Type of FU issued
281 system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.46% # Type of FU issued
282 system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.46% # Type of FU issued
283 system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.46% # Type of FU issued
284 system.cpu.iq.ISSUE:FU_type_0::MemRead 124774485 20.61% 93.07% # Type of FU issued
285 system.cpu.iq.ISSUE:FU_type_0::MemWrite 41956101 6.93% 100.00% # Type of FU issued
286 system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
287 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
288 system.cpu.iq.ISSUE:FU_type_0::total 605486212 # Type of FU issued
289 system.cpu.iq.ISSUE:fu_busy_cnt 7206090 # FU busy when requested
290 system.cpu.iq.ISSUE:fu_busy_rate 0.011901 # FU busy rate (busy events/executed inst)
291 system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
292 system.cpu.iq.ISSUE:fu_full::IntAlu 5226098 72.52% 72.52% # attempts to use FU when none available
293 system.cpu.iq.ISSUE:fu_full::IntMult 48 0.00% 72.52% # attempts to use FU when none available
294 system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 72.52% # attempts to use FU when none available
295 system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 72.52% # attempts to use FU when none available
296 system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 72.52% # attempts to use FU when none available
297 system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 72.52% # attempts to use FU when none available
298 system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 72.52% # attempts to use FU when none available
299 system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 72.52% # attempts to use FU when none available
300 system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 72.52% # attempts to use FU when none available
301 system.cpu.iq.ISSUE:fu_full::MemRead 1579159 21.91% 94.44% # attempts to use FU when none available
302 system.cpu.iq.ISSUE:fu_full::MemWrite 400785 5.56% 100.00% # attempts to use FU when none available
303 system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
304 system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
305 system.cpu.iq.ISSUE:issued_per_cycle::samples 330660336 # Number of insts issued each cycle
306 system.cpu.iq.ISSUE:issued_per_cycle::mean 1.831143 # Number of insts issued each cycle
307 system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.672265 # Number of insts issued each cycle
308 system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
309 system.cpu.iq.ISSUE:issued_per_cycle::0 90539952 27.38% 27.38% # Number of insts issued each cycle
310 system.cpu.iq.ISSUE:issued_per_cycle::1 66701453 20.17% 47.55% # Number of insts issued each cycle
311 system.cpu.iq.ISSUE:issued_per_cycle::2 79600053 24.07% 71.63% # Number of insts issued each cycle
312 system.cpu.iq.ISSUE:issued_per_cycle::3 36541170 11.05% 82.68% # Number of insts issued each cycle
313 system.cpu.iq.ISSUE:issued_per_cycle::4 31317153 9.47% 92.15% # Number of insts issued each cycle
314 system.cpu.iq.ISSUE:issued_per_cycle::5 13281184 4.02% 96.17% # Number of insts issued each cycle
315 system.cpu.iq.ISSUE:issued_per_cycle::6 11041150 3.34% 99.50% # Number of insts issued each cycle
316 system.cpu.iq.ISSUE:issued_per_cycle::7 1066057 0.32% 99.83% # Number of insts issued each cycle
317 system.cpu.iq.ISSUE:issued_per_cycle::8 572164 0.17% 100.00% # Number of insts issued each cycle
318 system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
319 system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
320 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
321 system.cpu.iq.ISSUE:issued_per_cycle::total 330660336 # Number of insts issued each cycle
322 system.cpu.iq.ISSUE:rate 1.830624 # Inst issue rate
323 system.cpu.iq.iqInstsAdded 620509446 # Number of instructions added to the IQ (excludes non-spec)
324 system.cpu.iq.iqInstsIssued 605486212 # Number of instructions issued
325 system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ
326 system.cpu.iq.iqSquashedInstsExamined 53535562 # Number of squashed instructions iterated over during squash; mainly for profiling
327 system.cpu.iq.iqSquashedInstsIssued 17232 # Number of squashed instructions issued
328 system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
329 system.cpu.iq.iqSquashedOperandsExamined 29599324 # Number of squashed operands that are examined and possibly removed from graph
330 system.cpu.itb.data_accesses 0 # DTB accesses
331 system.cpu.itb.data_acv 0 # DTB access violations
332 system.cpu.itb.data_hits 0 # DTB hits
333 system.cpu.itb.data_misses 0 # DTB misses
334 system.cpu.itb.fetch_accesses 65649312 # ITB accesses
335 system.cpu.itb.fetch_acv 0 # ITB acv
336 system.cpu.itb.fetch_hits 65649275 # ITB hits
337 system.cpu.itb.fetch_misses 37 # ITB misses
338 system.cpu.itb.read_accesses 0 # DTB read accesses
339 system.cpu.itb.read_acv 0 # DTB read access violations
340 system.cpu.itb.read_hits 0 # DTB read hits
341 system.cpu.itb.read_misses 0 # DTB read misses
342 system.cpu.itb.write_accesses 0 # DTB write accesses
343 system.cpu.itb.write_acv 0 # DTB write access violations
344 system.cpu.itb.write_hits 0 # DTB write hits
345 system.cpu.itb.write_misses 0 # DTB write misses
346 system.cpu.l2cache.ReadExReq_accesses 256918 # number of ReadExReq accesses(hits+misses)
347 system.cpu.l2cache.ReadExReq_avg_miss_latency 34522.310610 # average ReadExReq miss latency
348 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31406.220232 # average ReadExReq mshr miss latency
349 system.cpu.l2cache.ReadExReq_hits 197081 # number of ReadExReq hits
350 system.cpu.l2cache.ReadExReq_miss_latency 2065711500 # number of ReadExReq miss cycles
351 system.cpu.l2cache.ReadExReq_miss_rate 0.232903 # miss rate for ReadExReq accesses
352 system.cpu.l2cache.ReadExReq_misses 59837 # number of ReadExReq misses
353 system.cpu.l2cache.ReadExReq_mshr_miss_latency 1879254000 # number of ReadExReq MSHR miss cycles
354 system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.232903 # mshr miss rate for ReadExReq accesses
355 system.cpu.l2cache.ReadExReq_mshr_misses 59837 # number of ReadExReq MSHR misses
356 system.cpu.l2cache.ReadReq_accesses 219092 # number of ReadReq accesses(hits+misses)
357 system.cpu.l2cache.ReadReq_avg_miss_latency 34389.734476 # average ReadReq miss latency
358 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.456070 # average ReadReq mshr miss latency
359 system.cpu.l2cache.ReadReq_hits 186176 # number of ReadReq hits
360 system.cpu.l2cache.ReadReq_miss_latency 1131972500 # number of ReadReq miss cycles
361 system.cpu.l2cache.ReadReq_miss_rate 0.150238 # miss rate for ReadReq accesses
362 system.cpu.l2cache.ReadReq_misses 32916 # number of ReadReq misses
363 system.cpu.l2cache.ReadReq_mshr_miss_latency 1021003500 # number of ReadReq MSHR miss cycles
364 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150238 # mshr miss rate for ReadReq accesses
365 system.cpu.l2cache.ReadReq_mshr_misses 32916 # number of ReadReq MSHR misses
366 system.cpu.l2cache.Writeback_accesses 423151 # number of Writeback accesses(hits+misses)
367 system.cpu.l2cache.Writeback_hits 423151 # number of Writeback hits
368 system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5261.194030 # average number of cycles each access was blocked
369 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
370 system.cpu.l2cache.avg_refs 5.283534 # Average number of references to valid blocks.
371 system.cpu.l2cache.blocked::no_mshrs 67 # number of cycles access was blocked
372 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
373 system.cpu.l2cache.blocked_cycles::no_mshrs 352500 # number of cycles access was blocked
374 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
375 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
376 system.cpu.l2cache.demand_accesses 476010 # number of demand (read+write) accesses
377 system.cpu.l2cache.demand_avg_miss_latency 34475.262256 # average overall miss latency
378 system.cpu.l2cache.demand_avg_mshr_miss_latency 31268.611258 # average overall mshr miss latency
379 system.cpu.l2cache.demand_hits 383257 # number of demand (read+write) hits
380 system.cpu.l2cache.demand_miss_latency 3197684000 # number of demand (read+write) miss cycles
381 system.cpu.l2cache.demand_miss_rate 0.194855 # miss rate for demand accesses
382 system.cpu.l2cache.demand_misses 92753 # number of demand (read+write) misses
383 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
384 system.cpu.l2cache.demand_mshr_miss_latency 2900257500 # number of demand (read+write) MSHR miss cycles
385 system.cpu.l2cache.demand_mshr_miss_rate 0.194855 # mshr miss rate for demand accesses
386 system.cpu.l2cache.demand_mshr_misses 92753 # number of demand (read+write) MSHR misses
387 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
388 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
389 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
390 system.cpu.l2cache.occ_%::0 0.052815 # Average percentage of cache occupancy
391 system.cpu.l2cache.occ_%::1 0.488399 # Average percentage of cache occupancy
392 system.cpu.l2cache.occ_blocks::0 1730.637326 # Average occupied blocks per context
393 system.cpu.l2cache.occ_blocks::1 16003.856484 # Average occupied blocks per context
394 system.cpu.l2cache.overall_accesses 476010 # number of overall (read+write) accesses
395 system.cpu.l2cache.overall_avg_miss_latency 34475.262256 # average overall miss latency
396 system.cpu.l2cache.overall_avg_mshr_miss_latency 31268.611258 # average overall mshr miss latency
397 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
398 system.cpu.l2cache.overall_hits 383257 # number of overall hits
399 system.cpu.l2cache.overall_miss_latency 3197684000 # number of overall miss cycles
400 system.cpu.l2cache.overall_miss_rate 0.194855 # miss rate for overall accesses
401 system.cpu.l2cache.overall_misses 92753 # number of overall misses
402 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
403 system.cpu.l2cache.overall_mshr_miss_latency 2900257500 # number of overall MSHR miss cycles
404 system.cpu.l2cache.overall_mshr_miss_rate 0.194855 # mshr miss rate for overall accesses
405 system.cpu.l2cache.overall_mshr_misses 92753 # number of overall MSHR misses
406 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
407 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
408 system.cpu.l2cache.replacements 74446 # number of replacements
409 system.cpu.l2cache.sampled_refs 90349 # Sample count of references to valid blocks.
410 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
411 system.cpu.l2cache.tagsinuse 17734.493810 # Cycle average of tags in use
412 system.cpu.l2cache.total_refs 477362 # Total number of references to valid blocks.
413 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
414 system.cpu.l2cache.writebacks 59324 # number of writebacks
415 system.cpu.memDep0.conflictingLoads 22261692 # Number of conflicting loads.
416 system.cpu.memDep0.conflictingStores 15435128 # Number of conflicting stores.
417 system.cpu.memDep0.insertedLoads 126939472 # Number of loads inserted to the mem dependence unit.
418 system.cpu.memDep0.insertedStores 43126164 # Number of stores inserted to the mem dependence unit.
419 system.cpu.numCycles 330753974 # number of cpu cycles simulated
420 system.cpu.rename.RENAME:BlockCycles 12738848 # Number of cycles rename is blocking
421 system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
422 system.cpu.rename.RENAME:IQFullEvents 34708853 # Number of times rename has blocked due to IQ full
423 system.cpu.rename.RENAME:IdleCycles 151708807 # Number of cycles rename is idle
424 system.cpu.rename.RENAME:LSQFullEvents 618719 # Number of times rename has blocked due to LSQ full
425 system.cpu.rename.RENAME:ROBFullEvents 82 # Number of times rename has blocked due to ROB full
426 system.cpu.rename.RENAME:RenameLookups 896183749 # Number of register rename lookups that rename has made
427 system.cpu.rename.RENAME:RenamedInsts 680208714 # Number of instructions processed by rename
428 system.cpu.rename.RENAME:RenamedOperands 518824645 # Number of destination operands rename has renamed
429 system.cpu.rename.RENAME:RunCycles 115765657 # Number of cycles rename is running
430 system.cpu.rename.RENAME:SquashCycles 9844039 # Number of cycles rename is squashing
431 system.cpu.rename.RENAME:UnblockCycles 40602289 # Number of cycles rename is unblocking
432 system.cpu.rename.RENAME:UndoneMaps 54969756 # Number of HB maps that are undone due to squashing
433 system.cpu.rename.RENAME:serializeStallCycles 696 # count of cycles rename stalled for serializing inst
434 system.cpu.rename.RENAME:serializingInsts 32 # count of serializing insts renamed
435 system.cpu.rename.RENAME:skidInsts 79641546 # count of insts added to the skid buffer
436 system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed
437 system.cpu.timesIdled 3516 # Number of times that the entire CPU went into an idle state and unscheduled itself
438 system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
440 ---------- End Simulation Statistics ----------
projects / gem5.git / blob