2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 309694 # Simulator instruction rate (inst/s)
4 host_mem_usage 206028 # Number of bytes of host memory used
5 host_seconds 1826.17 # Real time elapsed on the host
6 host_tick_rate 91491135 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 565552443 # Number of instructions simulated
9 sim_seconds 0.167078 # Number of seconds simulated
10 sim_ticks 167078146500 # Number of ticks simulated
11 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
12 system.cpu.BPredUnit.BTBHits 65718859 # Number of BTB hits
13 system.cpu.BPredUnit.BTBLookups 73181368 # Number of BTB lookups
14 system.cpu.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions.
15 system.cpu.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect
16 system.cpu.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted
17 system.cpu.BPredUnit.lookups 76039018 # Number of BP lookups
18 system.cpu.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target.
19 system.cpu.commit.COM:branches 62547159 # Number of branches committed
20 system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached
21 system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
22 system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
23 system.cpu.commit.COM:committed_per_cycle.samples 322711249
24 system.cpu.commit.COM:committed_per_cycle.min_value 0
34 system.cpu.commit.COM:committed_per_cycle.max_value 8
35 system.cpu.commit.COM:committed_per_cycle.end_dist
37 system.cpu.commit.COM:count 601856963 # Number of instructions committed
38 system.cpu.commit.COM:loads 115049510 # Number of loads committed
39 system.cpu.commit.COM:membars 0 # Number of memory barriers committed
40 system.cpu.commit.COM:refs 154862033 # Number of memory references committed
41 system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
42 system.cpu.commit.branchMispredicts 4206223 # The number of times a branch was mispredicted
43 system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
44 system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
45 system.cpu.commit.commitSquashedInsts 61418165 # The number of squashed insts skipped by commit
46 system.cpu.committedInsts 565552443 # Number of Instructions Simulated
47 system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
48 system.cpu.cpi 0.590849 # CPI: Cycles Per Instruction
49 system.cpu.cpi_total 0.590849 # CPI: Total CPI of All Threads
50 system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
51 system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
52 system.cpu.dcache.ReadReq_accesses 113146786 # number of ReadReq accesses(hits+misses)
53 system.cpu.dcache.ReadReq_avg_miss_latency 19647.173839 # average ReadReq miss latency
54 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.243845 # average ReadReq mshr miss latency
55 system.cpu.dcache.ReadReq_hits 112293703 # number of ReadReq hits
56 system.cpu.dcache.ReadReq_miss_latency 16760670000 # number of ReadReq miss cycles
57 system.cpu.dcache.ReadReq_miss_rate 0.007540 # miss rate for ReadReq accesses
58 system.cpu.dcache.ReadReq_misses 853083 # number of ReadReq misses
59 system.cpu.dcache.ReadReq_mshr_hits 636806 # number of ReadReq MSHR hits
60 system.cpu.dcache.ReadReq_mshr_miss_latency 1688311000 # number of ReadReq MSHR miss cycles
61 system.cpu.dcache.ReadReq_mshr_miss_rate 0.001911 # mshr miss rate for ReadReq accesses
62 system.cpu.dcache.ReadReq_mshr_misses 216277 # number of ReadReq MSHR misses
63 system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
64 system.cpu.dcache.WriteReq_avg_miss_latency 32801.298408 # average WriteReq miss latency
65 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35637.649046 # average WriteReq mshr miss latency
66 system.cpu.dcache.WriteReq_hits 37121636 # number of WriteReq hits
67 system.cpu.dcache.WriteReq_miss_latency 76416692881 # number of WriteReq miss cycles
68 system.cpu.dcache.WriteReq_miss_rate 0.059052 # miss rate for WriteReq accesses
69 system.cpu.dcache.WriteReq_misses 2329685 # number of WriteReq misses
70 system.cpu.dcache.WriteReq_mshr_hits 1992407 # number of WriteReq MSHR hits
71 system.cpu.dcache.WriteReq_mshr_miss_latency 12019794995 # number of WriteReq MSHR miss cycles
72 system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # mshr miss rate for WriteReq accesses
73 system.cpu.dcache.WriteReq_mshr_misses 337278 # number of WriteReq MSHR misses
74 system.cpu.dcache.avg_blocked_cycles_no_mshrs 6922.723577 # average number of cycles each access was blocked
75 system.cpu.dcache.avg_blocked_cycles_no_targets 21318.181818 # average number of cycles each access was blocked
76 system.cpu.dcache.avg_refs 317.179202 # Average number of references to valid blocks.
77 system.cpu.dcache.blocked_no_mshrs 123 # number of cycles access was blocked
78 system.cpu.dcache.blocked_no_targets 11 # number of cycles access was blocked
79 system.cpu.dcache.blocked_cycles_no_mshrs 851495 # number of cycles access was blocked
80 system.cpu.dcache.blocked_cycles_no_targets 234500 # number of cycles access was blocked
81 system.cpu.dcache.cache_copies 0 # number of cache copies performed
82 system.cpu.dcache.demand_accesses 152598107 # number of demand (read+write) accesses
83 system.cpu.dcache.demand_avg_miss_latency 29275.574871 # average overall miss latency
84 system.cpu.dcache.demand_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency
85 system.cpu.dcache.demand_hits 149415339 # number of demand (read+write) hits
86 system.cpu.dcache.demand_miss_latency 93177362881 # number of demand (read+write) miss cycles
87 system.cpu.dcache.demand_miss_rate 0.020857 # miss rate for demand accesses
88 system.cpu.dcache.demand_misses 3182768 # number of demand (read+write) misses
89 system.cpu.dcache.demand_mshr_hits 2629213 # number of demand (read+write) MSHR hits
90 system.cpu.dcache.demand_mshr_miss_latency 13708105995 # number of demand (read+write) MSHR miss cycles
91 system.cpu.dcache.demand_mshr_miss_rate 0.003628 # mshr miss rate for demand accesses
92 system.cpu.dcache.demand_mshr_misses 553555 # number of demand (read+write) MSHR misses
93 system.cpu.dcache.fast_writes 0 # number of fast writes performed
94 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
95 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
96 system.cpu.dcache.overall_accesses 152598107 # number of overall (read+write) accesses
97 system.cpu.dcache.overall_avg_miss_latency 29275.574871 # average overall miss latency
98 system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency
99 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
100 system.cpu.dcache.overall_hits 149415339 # number of overall hits
101 system.cpu.dcache.overall_miss_latency 93177362881 # number of overall miss cycles
102 system.cpu.dcache.overall_miss_rate 0.020857 # miss rate for overall accesses
103 system.cpu.dcache.overall_misses 3182768 # number of overall misses
104 system.cpu.dcache.overall_mshr_hits 2629213 # number of overall MSHR hits
105 system.cpu.dcache.overall_mshr_miss_latency 13708105995 # number of overall MSHR miss cycles
106 system.cpu.dcache.overall_mshr_miss_rate 0.003628 # mshr miss rate for overall accesses
107 system.cpu.dcache.overall_mshr_misses 553555 # number of overall MSHR misses
108 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
109 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
110 system.cpu.dcache.replacements 468828 # number of replacements
111 system.cpu.dcache.sampled_refs 472924 # Sample count of references to valid blocks.
112 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
113 system.cpu.dcache.tagsinuse 4094.203417 # Cycle average of tags in use
114 system.cpu.dcache.total_refs 150001657 # Total number of references to valid blocks.
115 system.cpu.dcache.warmup_cycle 126581000 # Cycle when the warmup percentage was hit.
116 system.cpu.dcache.writebacks 334123 # number of writebacks
117 system.cpu.decode.DECODE:BlockedCycles 49202518 # Number of cycles decode is blocked
118 system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction
119 system.cpu.decode.DECODE:BranchResolved 4158991 # Number of times decode resolved a branch
120 system.cpu.decode.DECODE:DecodedInsts 689696194 # Number of instructions handled by decode
121 system.cpu.decode.DECODE:IdleCycles 144199483 # Number of cycles decode is idle
122 system.cpu.decode.DECODE:RunCycles 123896058 # Number of cycles decode is running
123 system.cpu.decode.DECODE:SquashCycles 9869862 # Number of cycles decode is squashing
124 system.cpu.decode.DECODE:SquashedInsts 2004 # Number of squashed instructions handled by decode
125 system.cpu.decode.DECODE:UnblockCycles 5413191 # Number of cycles decode is unblocking
126 system.cpu.dtb.accesses 163077390 # DTB accesses
127 system.cpu.dtb.acv 0 # DTB access violations
128 system.cpu.dtb.hits 163013880 # DTB hits
129 system.cpu.dtb.misses 63510 # DTB misses
130 system.cpu.dtb.read_accesses 122284109 # DTB read accesses
131 system.cpu.dtb.read_acv 0 # DTB read access violations
132 system.cpu.dtb.read_hits 122260496 # DTB read hits
133 system.cpu.dtb.read_misses 23613 # DTB read misses
134 system.cpu.dtb.write_accesses 40793281 # DTB write accesses
135 system.cpu.dtb.write_acv 0 # DTB write access violations
136 system.cpu.dtb.write_hits 40753384 # DTB write hits
137 system.cpu.dtb.write_misses 39897 # DTB write misses
138 system.cpu.fetch.Branches 76039018 # Number of branches that fetch encountered
139 system.cpu.fetch.CacheLines 66014406 # Number of cache lines fetched
140 system.cpu.fetch.Cycles 197129335 # Number of cycles fetch has run and was not squashing or blocked
141 system.cpu.fetch.IcacheSquashes 1352914 # Number of outstanding Icache misses that were squashed
142 system.cpu.fetch.Insts 698864013 # Number of instructions fetch has processed
143 system.cpu.fetch.SquashCycles 4233116 # Number of cycles fetch has spent squashing
144 system.cpu.fetch.branchRate 0.227555 # Number of branch fetches per cycle
145 system.cpu.fetch.icacheStallCycles 66014406 # Number of cycles fetch is stalled on an Icache miss
146 system.cpu.fetch.predictedBranches 67411078 # Number of branches that fetch has predicted taken
147 system.cpu.fetch.rate 2.091429 # Number of inst fetches per cycle
148 system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
149 system.cpu.fetch.rateDist.samples 332581112
150 system.cpu.fetch.rateDist.min_value 0
160 system.cpu.fetch.rateDist.max_value 8
161 system.cpu.fetch.rateDist.end_dist
163 system.cpu.icache.ReadReq_accesses 66014406 # number of ReadReq accesses(hits+misses)
164 system.cpu.icache.ReadReq_avg_miss_latency 36214.713430 # average ReadReq miss latency
165 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35498.337029 # average ReadReq mshr miss latency
166 system.cpu.icache.ReadReq_hits 66013237 # number of ReadReq hits
167 system.cpu.icache.ReadReq_miss_latency 42335000 # number of ReadReq miss cycles
168 system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
169 system.cpu.icache.ReadReq_misses 1169 # number of ReadReq misses
170 system.cpu.icache.ReadReq_mshr_hits 267 # number of ReadReq MSHR hits
171 system.cpu.icache.ReadReq_mshr_miss_latency 32019500 # number of ReadReq MSHR miss cycles
172 system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
173 system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses
174 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
175 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
176 system.cpu.icache.avg_refs 73185.406874 # Average number of references to valid blocks.
177 system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
178 system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
179 system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
180 system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
181 system.cpu.icache.cache_copies 0 # number of cache copies performed
182 system.cpu.icache.demand_accesses 66014406 # number of demand (read+write) accesses
183 system.cpu.icache.demand_avg_miss_latency 36214.713430 # average overall miss latency
184 system.cpu.icache.demand_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency
185 system.cpu.icache.demand_hits 66013237 # number of demand (read+write) hits
186 system.cpu.icache.demand_miss_latency 42335000 # number of demand (read+write) miss cycles
187 system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
188 system.cpu.icache.demand_misses 1169 # number of demand (read+write) misses
189 system.cpu.icache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits
190 system.cpu.icache.demand_mshr_miss_latency 32019500 # number of demand (read+write) MSHR miss cycles
191 system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
192 system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses
193 system.cpu.icache.fast_writes 0 # number of fast writes performed
194 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
195 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
196 system.cpu.icache.overall_accesses 66014406 # number of overall (read+write) accesses
197 system.cpu.icache.overall_avg_miss_latency 36214.713430 # average overall miss latency
198 system.cpu.icache.overall_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency
199 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
200 system.cpu.icache.overall_hits 66013237 # number of overall hits
201 system.cpu.icache.overall_miss_latency 42335000 # number of overall miss cycles
202 system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
203 system.cpu.icache.overall_misses 1169 # number of overall misses
204 system.cpu.icache.overall_mshr_hits 267 # number of overall MSHR hits
205 system.cpu.icache.overall_mshr_miss_latency 32019500 # number of overall MSHR miss cycles
206 system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
207 system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses
208 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
209 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
210 system.cpu.icache.replacements 34 # number of replacements
211 system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks.
212 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
213 system.cpu.icache.tagsinuse 769.803945 # Cycle average of tags in use
214 system.cpu.icache.total_refs 66013237 # Total number of references to valid blocks.
215 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
216 system.cpu.icache.writebacks 0 # number of writebacks
217 system.cpu.idleCycles 1575182 # Total number of cycles that the CPU has spent unscheduled due to idling
218 system.cpu.iew.EXEC:branches 67316859 # Number of branches executed
219 system.cpu.iew.EXEC:nop 42997381 # number of nop insts executed
220 system.cpu.iew.EXEC:rate 1.793347 # Inst execution rate
221 system.cpu.iew.EXEC:refs 164017993 # number of memory reference insts executed
222 system.cpu.iew.EXEC:stores 41189464 # Number of stores executed
223 system.cpu.iew.EXEC:swp 0 # number of swp insts executed
224 system.cpu.iew.WB:consumers 487237002 # num instructions consuming a value
225 system.cpu.iew.WB:count 596051147 # cumulative count of insts written-back
226 system.cpu.iew.WB:fanout 0.811465 # average fanout of values written-back
227 system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
228 system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
229 system.cpu.iew.WB:producers 395375802 # num instructions producing a value
230 system.cpu.iew.WB:rate 1.783750 # insts written-back per cycle
231 system.cpu.iew.WB:sent 597227180 # cumulative count of insts sent to commit
232 system.cpu.iew.branchMispredicts 4671561 # Number of branch mispredicts detected at execute
233 system.cpu.iew.iewBlockCycles 2251979 # Number of cycles IEW is blocking
234 system.cpu.iew.iewDispLoadInsts 126977202 # Number of dispatched load instructions
235 system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
236 system.cpu.iew.iewDispSquashedInsts 3270425 # Number of squashed instructions skipped by dispatch
237 system.cpu.iew.iewDispStoreInsts 43223597 # Number of dispatched store instructions
238 system.cpu.iew.iewDispatchedInsts 663379957 # Number of instructions dispatched to IQ
239 system.cpu.iew.iewExecLoadInsts 122828529 # Number of load instructions executed
240 system.cpu.iew.iewExecSquashedInsts 6459968 # Number of squashed instructions skipped in execute
241 system.cpu.iew.iewExecutedInsts 599258144 # Number of executed instructions
242 system.cpu.iew.iewIQFullEvents 2443 # Number of times the IQ has become full, causing a stall
243 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
244 system.cpu.iew.iewLSQFullEvents 34441 # Number of times the LSQ has become full, causing a stall
245 system.cpu.iew.iewSquashCycles 9869862 # Number of cycles IEW is squashing
246 system.cpu.iew.iewUnblockCycles 84552 # Number of cycles IEW is unblocking
247 system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
248 system.cpu.iew.lsq.thread.0.cacheBlocked 207 # Number of times an access to memory failed due to the cache being blocked
249 system.cpu.iew.lsq.thread.0.forwLoads 9107751 # Number of loads that had data forwarded from stores
250 system.cpu.iew.lsq.thread.0.ignoredResponses 14447 # Number of memory responses ignored because the instruction is squashed
251 system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
252 system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
253 system.cpu.iew.lsq.thread.0.memOrderViolation 29567 # Number of memory ordering violations
254 system.cpu.iew.lsq.thread.0.rescheduledLoads 5881 # Number of loads that were rescheduled
255 system.cpu.iew.lsq.thread.0.squashedLoads 11927692 # Number of loads squashed
256 system.cpu.iew.lsq.thread.0.squashedStores 3411074 # Number of stores squashed
257 system.cpu.iew.memOrderViolationEvents 29567 # Number of memory order violations
258 system.cpu.iew.predictedNotTakenIncorrect 540315 # Number of branches that were predicted not taken incorrectly
259 system.cpu.iew.predictedTakenIncorrect 4131246 # Number of branches that were predicted taken incorrectly
260 system.cpu.ipc 1.692479 # IPC: Instructions Per Cycle
261 system.cpu.ipc_total 1.692479 # IPC: Total IPC of All Threads
262 system.cpu.iq.ISSUE:FU_type_0 605718112 # Type of FU issued
263 system.cpu.iq.ISSUE:FU_type_0.start_dist
264 No_OpClass 0 0.00% # Type of FU issued
265 IntAlu 438834840 72.45% # Type of FU issued
266 IntMult 6546 0.00% # Type of FU issued
267 IntDiv 0 0.00% # Type of FU issued
268 FloatAdd 29 0.00% # Type of FU issued
269 FloatCmp 5 0.00% # Type of FU issued
270 FloatCvt 5 0.00% # Type of FU issued
271 FloatMult 4 0.00% # Type of FU issued
272 FloatDiv 0 0.00% # Type of FU issued
273 FloatSqrt 0 0.00% # Type of FU issued
274 MemRead 124855453 20.61% # Type of FU issued
275 MemWrite 42021230 6.94% # Type of FU issued
276 IprAccess 0 0.00% # Type of FU issued
277 InstPrefetch 0 0.00% # Type of FU issued
278 system.cpu.iq.ISSUE:FU_type_0.end_dist
279 system.cpu.iq.ISSUE:fu_busy_cnt 7232323 # FU busy when requested
280 system.cpu.iq.ISSUE:fu_busy_rate 0.011940 # FU busy rate (busy events/executed inst)
281 system.cpu.iq.ISSUE:fu_full.start_dist
282 No_OpClass 0 0.00% # attempts to use FU when none available
283 IntAlu 5390831 74.54% # attempts to use FU when none available
284 IntMult 67 0.00% # attempts to use FU when none available
285 IntDiv 0 0.00% # attempts to use FU when none available
286 FloatAdd 0 0.00% # attempts to use FU when none available
287 FloatCmp 0 0.00% # attempts to use FU when none available
288 FloatCvt 0 0.00% # attempts to use FU when none available
289 FloatMult 0 0.00% # attempts to use FU when none available
290 FloatDiv 0 0.00% # attempts to use FU when none available
291 FloatSqrt 0 0.00% # attempts to use FU when none available
292 MemRead 1490139 20.60% # attempts to use FU when none available
293 MemWrite 351286 4.86% # attempts to use FU when none available
294 IprAccess 0 0.00% # attempts to use FU when none available
295 InstPrefetch 0 0.00% # attempts to use FU when none available
296 system.cpu.iq.ISSUE:fu_full.end_dist
297 system.cpu.iq.ISSUE:issued_per_cycle::samples 332581112
298 system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
299 system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00%
300 system.cpu.iq.ISSUE:issued_per_cycle::0-1 92203773 27.72%
301 system.cpu.iq.ISSUE:issued_per_cycle::1-2 67051353 20.16%
302 system.cpu.iq.ISSUE:issued_per_cycle::2-3 80133780 24.09%
303 system.cpu.iq.ISSUE:issued_per_cycle::3-4 36043478 10.84%
304 system.cpu.iq.ISSUE:issued_per_cycle::4-5 30084945 9.05%
305 system.cpu.iq.ISSUE:issued_per_cycle::5-6 14579095 4.38%
306 system.cpu.iq.ISSUE:issued_per_cycle::6-7 10850493 3.26%
307 system.cpu.iq.ISSUE:issued_per_cycle::7-8 1143008 0.34%
308 system.cpu.iq.ISSUE:issued_per_cycle::8 491187 0.15%
309 system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00%
310 system.cpu.iq.ISSUE:issued_per_cycle::total 332581112
311 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8
312 system.cpu.iq.ISSUE:issued_per_cycle::mean 1.821264
313 system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.674645
314 system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate
315 system.cpu.iq.iqInstsAdded 620382553 # Number of instructions added to the IQ (excludes non-spec)
316 system.cpu.iq.iqInstsIssued 605718112 # Number of instructions issued
317 system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
318 system.cpu.iq.iqSquashedInstsExamined 53519286 # Number of squashed instructions iterated over during squash; mainly for profiling
319 system.cpu.iq.iqSquashedInstsIssued 12833 # Number of squashed instructions issued
320 system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
321 system.cpu.iq.iqSquashedOperandsExamined 29313548 # Number of squashed operands that are examined and possibly removed from graph
322 system.cpu.itb.accesses 66014446 # ITB accesses
323 system.cpu.itb.acv 0 # ITB acv
324 system.cpu.itb.hits 66014406 # ITB hits
325 system.cpu.itb.misses 40 # ITB misses
326 system.cpu.l2cache.ReadExReq_accesses 256647 # number of ReadExReq accesses(hits+misses)
327 system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026 # average ReadExReq miss latency
328 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31141.538767 # average ReadExReq mshr miss latency
329 system.cpu.l2cache.ReadExReq_miss_latency 8792814000 # number of ReadExReq miss cycles
330 system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
331 system.cpu.l2cache.ReadExReq_misses 256647 # number of ReadExReq misses
332 system.cpu.l2cache.ReadExReq_mshr_miss_latency 7992382500 # number of ReadExReq MSHR miss cycles
333 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
334 system.cpu.l2cache.ReadExReq_mshr_misses 256647 # number of ReadExReq MSHR misses
335 system.cpu.l2cache.ReadReq_accesses 217179 # number of ReadReq accesses(hits+misses)
336 system.cpu.l2cache.ReadReq_avg_miss_latency 34303.986479 # average ReadReq miss latency
337 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31015.630238 # average ReadReq mshr miss latency
338 system.cpu.l2cache.ReadReq_hits 181383 # number of ReadReq hits
339 system.cpu.l2cache.ReadReq_miss_latency 1227945500 # number of ReadReq miss cycles
340 system.cpu.l2cache.ReadReq_miss_rate 0.164823 # miss rate for ReadReq accesses
341 system.cpu.l2cache.ReadReq_misses 35796 # number of ReadReq misses
342 system.cpu.l2cache.ReadReq_mshr_miss_latency 1110235500 # number of ReadReq MSHR miss cycles
343 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164823 # mshr miss rate for ReadReq accesses
344 system.cpu.l2cache.ReadReq_mshr_misses 35796 # number of ReadReq MSHR misses
345 system.cpu.l2cache.UpgradeReq_accesses 80643 # number of UpgradeReq accesses(hits+misses)
346 system.cpu.l2cache.UpgradeReq_avg_miss_latency 34136.391255 # average UpgradeReq miss latency
347 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31030.684622 # average UpgradeReq mshr miss latency
348 system.cpu.l2cache.UpgradeReq_miss_latency 2752861000 # number of UpgradeReq miss cycles
349 system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
350 system.cpu.l2cache.UpgradeReq_misses 80643 # number of UpgradeReq misses
351 system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2502407500 # number of UpgradeReq MSHR miss cycles
352 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
353 system.cpu.l2cache.UpgradeReq_mshr_misses 80643 # number of UpgradeReq MSHR misses
354 system.cpu.l2cache.Writeback_accesses 334123 # number of Writeback accesses(hits+misses)
355 system.cpu.l2cache.Writeback_hits 334123 # number of Writeback hits
356 system.cpu.l2cache.avg_blocked_cycles_no_mshrs 5083.333333 # average number of cycles each access was blocked
357 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
358 system.cpu.l2cache.avg_refs 3.723010 # Average number of references to valid blocks.
359 system.cpu.l2cache.blocked_no_mshrs 78 # number of cycles access was blocked
360 system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
361 system.cpu.l2cache.blocked_cycles_no_mshrs 396500 # number of cycles access was blocked
362 system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
363 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
364 system.cpu.l2cache.demand_accesses 473826 # number of demand (read+write) accesses
365 system.cpu.l2cache.demand_avg_miss_latency 34265.684253 # average overall miss latency
366 system.cpu.l2cache.demand_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency
367 system.cpu.l2cache.demand_hits 181383 # number of demand (read+write) hits
368 system.cpu.l2cache.demand_miss_latency 10020759500 # number of demand (read+write) miss cycles
369 system.cpu.l2cache.demand_miss_rate 0.617195 # miss rate for demand accesses
370 system.cpu.l2cache.demand_misses 292443 # number of demand (read+write) misses
371 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
372 system.cpu.l2cache.demand_mshr_miss_latency 9102618000 # number of demand (read+write) MSHR miss cycles
373 system.cpu.l2cache.demand_mshr_miss_rate 0.617195 # mshr miss rate for demand accesses
374 system.cpu.l2cache.demand_mshr_misses 292443 # number of demand (read+write) MSHR misses
375 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
376 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
377 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
378 system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses
379 system.cpu.l2cache.overall_avg_miss_latency 34265.684253 # average overall miss latency
380 system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency
381 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
382 system.cpu.l2cache.overall_hits 181383 # number of overall hits
383 system.cpu.l2cache.overall_miss_latency 10020759500 # number of overall miss cycles
384 system.cpu.l2cache.overall_miss_rate 0.617195 # miss rate for overall accesses
385 system.cpu.l2cache.overall_misses 292443 # number of overall misses
386 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
387 system.cpu.l2cache.overall_mshr_miss_latency 9102618000 # number of overall MSHR miss cycles
388 system.cpu.l2cache.overall_mshr_miss_rate 0.617195 # mshr miss rate for overall accesses
389 system.cpu.l2cache.overall_mshr_misses 292443 # number of overall MSHR misses
390 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
391 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
392 system.cpu.l2cache.replacements 85262 # number of replacements
393 system.cpu.l2cache.sampled_refs 100888 # Sample count of references to valid blocks.
394 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
395 system.cpu.l2cache.tagsinuse 16333.162457 # Cycle average of tags in use
396 system.cpu.l2cache.total_refs 375607 # Total number of references to valid blocks.
397 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
398 system.cpu.l2cache.writebacks 63236 # number of writebacks
399 system.cpu.memDep0.conflictingLoads 19292303 # Number of conflicting loads.
400 system.cpu.memDep0.conflictingStores 14732751 # Number of conflicting stores.
401 system.cpu.memDep0.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit.
402 system.cpu.memDep0.insertedStores 43223597 # Number of stores inserted to the mem dependence unit.
403 system.cpu.numCycles 334156294 # number of cpu cycles simulated
404 system.cpu.rename.RENAME:BlockCycles 15214853 # Number of cycles rename is blocking
405 system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
406 system.cpu.rename.RENAME:IQFullEvents 31587363 # Number of times rename has blocked due to IQ full
407 system.cpu.rename.RENAME:IdleCycles 151899436 # Number of cycles rename is idle
408 system.cpu.rename.RENAME:LSQFullEvents 2286618 # Number of times rename has blocked due to LSQ full
409 system.cpu.rename.RENAME:ROBFullEvents 131 # Number of times rename has blocked due to ROB full
410 system.cpu.rename.RENAME:RenameLookups 896816353 # Number of register rename lookups that rename has made
411 system.cpu.rename.RENAME:RenamedInsts 680424744 # Number of instructions processed by rename
412 system.cpu.rename.RENAME:RenamedOperands 519473797 # Number of destination operands rename has renamed
413 system.cpu.rename.RENAME:RunCycles 116400987 # Number of cycles rename is running
414 system.cpu.rename.RENAME:SquashCycles 9869862 # Number of cycles rename is squashing
415 system.cpu.rename.RENAME:UnblockCycles 39195268 # Number of cycles rename is unblocking
416 system.cpu.rename.RENAME:UndoneMaps 55618908 # Number of HB maps that are undone due to squashing
417 system.cpu.rename.RENAME:serializeStallCycles 706 # count of cycles rename stalled for serializing inst
418 system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed
419 system.cpu.rename.RENAME:skidInsts 77660298 # count of insts added to the skid buffer
420 system.cpu.rename.RENAME:tempSerializingInsts 26 # count of temporary serializing insts renamed
421 system.cpu.timesIdled 36534 # Number of times that the entire CPU went into an idle state and unscheduled itself
422 system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
424 ---------- End Simulation Statistics ----------
projects / gem5.git / blob