tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 dummy=0
   5
   6 [system]
   7 type=System
   8 children=cpu membus physmem
   9 mem_mode=atomic
  10 physmem=system.physmem
  11
  12 [system.cpu]
  13 type=TimingSimpleCPU
  14 children=dcache icache l2cache toL2Bus workload
  15 clock=500
  16 cpu_id=0
  17 defer_registration=false
  18 function_trace=false
  19 function_trace_start=0
  20 max_insts_all_threads=0
  21 max_insts_any_thread=0
  22 max_loads_all_threads=0
  23 max_loads_any_thread=0
  24 phase=0
  25 progress_interval=0
  26 system=system
  27 workload=system.cpu.workload
  28 dcache_port=system.cpu.dcache.cpu_side
  29 icache_port=system.cpu.icache.cpu_side
  30
  31 [system.cpu.dcache]
  32 type=BaseCache
  33 adaptive_compression=false
  34 assoc=2
  35 block_size=64
  36 compressed_bus=false
  37 compression_latency=0
  38 hash_delay=1
  39 hit_latency=1
  40 latency=1
  41 lifo=false
  42 max_miss_count=0
  43 mshrs=10
  44 prefetch_access=false
  45 prefetch_cache_check_push=true
  46 prefetch_data_accesses_only=false
  47 prefetch_degree=1
  48 prefetch_latency=10
  49 prefetch_miss=false
  50 prefetch_past_page=false
  51 prefetch_policy=none
  52 prefetch_serial_squash=false
  53 prefetch_use_cpu_id=true
  54 prefetcher_size=100
  55 prioritizeRequests=false
  56 protocol=Null
  57 repl=Null
  58 size=262144
  59 split=false
  60 split_size=0
  61 store_compressed=false
  62 subblock_size=0
  63 tgts_per_mshr=5
  64 trace_addr=0
  65 two_queue=false
  66 write_buffers=8
  67 cpu_side=system.cpu.dcache_port
  68 mem_side=system.cpu.toL2Bus.port[1]
  69
  70 [system.cpu.icache]
  71 type=BaseCache
  72 adaptive_compression=false
  73 assoc=2
  74 block_size=64
  75 compressed_bus=false
  76 compression_latency=0
  77 hash_delay=1
  78 hit_latency=1
  79 latency=1
  80 lifo=false
  81 max_miss_count=0
  82 mshrs=10
  83 prefetch_access=false
  84 prefetch_cache_check_push=true
  85 prefetch_data_accesses_only=false
  86 prefetch_degree=1
  87 prefetch_latency=10
  88 prefetch_miss=false
  89 prefetch_past_page=false
  90 prefetch_policy=none
  91 prefetch_serial_squash=false
  92 prefetch_use_cpu_id=true
  93 prefetcher_size=100
  94 prioritizeRequests=false
  95 protocol=Null
  96 repl=Null
  97 size=131072
  98 split=false
  99 split_size=0
 100 store_compressed=false
 101 subblock_size=0
 102 tgts_per_mshr=5
 103 trace_addr=0
 104 two_queue=false
 105 write_buffers=8
 106 cpu_side=system.cpu.icache_port
 107 mem_side=system.cpu.toL2Bus.port[0]
 108
 109 [system.cpu.l2cache]
 110 type=BaseCache
 111 adaptive_compression=false
 112 assoc=2
 113 block_size=64
 114 compressed_bus=false
 115 compression_latency=0
 116 hash_delay=1
 117 hit_latency=1
 118 latency=1
 119 lifo=false
 120 max_miss_count=0
 121 mshrs=10
 122 prefetch_access=false
 123 prefetch_cache_check_push=true
 124 prefetch_data_accesses_only=false
 125 prefetch_degree=1
 126 prefetch_latency=10
 127 prefetch_miss=false
 128 prefetch_past_page=false
 129 prefetch_policy=none
 130 prefetch_serial_squash=false
 131 prefetch_use_cpu_id=true
 132 prefetcher_size=100
 133 prioritizeRequests=false
 134 protocol=Null
 135 repl=Null
 136 size=2097152
 137 split=false
 138 split_size=0
 139 store_compressed=false
 140 subblock_size=0
 141 tgts_per_mshr=5
 142 trace_addr=0
 143 two_queue=false
 144 write_buffers=8
 145 cpu_side=system.cpu.toL2Bus.port[2]
 146 mem_side=system.membus.port[1]
 147
 148 [system.cpu.toL2Bus]
 149 type=Bus
 150 bus_id=0
 151 clock=1000
 152 responder_set=false
 153 width=64
 154 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 155
 156 [system.cpu.workload]
 157 type=LiveProcess
 158 cmd=gzip input.log 1
 159 cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
 160 egid=100
 161 env=
 162 euid=100
 163 executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
 164 gid=100
 165 input=cin
 166 output=cout
 167 pid=100
 168 ppid=99
 169 system=system
 170 uid=100
 171
 172 [system.membus]
 173 type=Bus
 174 bus_id=0
 175 clock=1000
 176 responder_set=false
 177 width=64
 178 port=system.physmem.port system.cpu.l2cache.mem_side
 179
 180 [system.physmem]
 181 type=PhysicalMemory
 182 file=
 183 latency=1
 184 range=0:134217727
 185 zero=false
 186 port=system.membus.port[0]
 187