2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 238408 # Simulator instruction rate (inst/s)
4 host_mem_usage 258640 # Number of bytes of host memory used
5 host_seconds 2526.59 # Real time elapsed on the host
6 host_tick_rate 77778012 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 602359865 # Number of instructions simulated
9 sim_seconds 0.196513 # Number of seconds simulated
10 sim_ticks 196513140500 # Number of ticks simulated
11 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
12 system.cpu.BPredUnit.BTBHits 75744427 # Number of BTB hits
13 system.cpu.BPredUnit.BTBLookups 81879675 # Number of BTB lookups
14 system.cpu.BPredUnit.RASInCorrect 1640 # Number of incorrect RAS predictions.
15 system.cpu.BPredUnit.condIncorrect 3832102 # Number of conditional branches incorrect
16 system.cpu.BPredUnit.condPredicted 81880205 # Number of conditional branches predicted
17 system.cpu.BPredUnit.lookups 88398894 # Number of BP lookups
18 system.cpu.BPredUnit.usedRAS 1393010 # Number of times the RAS was used to get a target.
19 system.cpu.commit.COM:branches 70828614 # Number of branches committed
20 system.cpu.commit.COM:bw_lim_events 7897771 # number cycles where commit BW limit reached
21 system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
22 system.cpu.commit.COM:committed_per_cycle::samples 379244728 # Number of insts commited each cycle
23 system.cpu.commit.COM:committed_per_cycle::mean 1.588315 # Number of insts commited each cycle
24 system.cpu.commit.COM:committed_per_cycle::stdev 1.904338 # Number of insts commited each cycle
25 system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
26 system.cpu.commit.COM:committed_per_cycle::0 123478650 32.56% 32.56% # Number of insts commited each cycle
27 system.cpu.commit.COM:committed_per_cycle::1 123013107 32.44% 65.00% # Number of insts commited each cycle
28 system.cpu.commit.COM:committed_per_cycle::2 59170888 15.60% 80.60% # Number of insts commited each cycle
29 system.cpu.commit.COM:committed_per_cycle::3 18488020 4.87% 85.47% # Number of insts commited each cycle
30 system.cpu.commit.COM:committed_per_cycle::4 17225820 4.54% 90.01% # Number of insts commited each cycle
31 system.cpu.commit.COM:committed_per_cycle::5 14373715 3.79% 93.80% # Number of insts commited each cycle
32 system.cpu.commit.COM:committed_per_cycle::6 7590349 2.00% 95.81% # Number of insts commited each cycle
33 system.cpu.commit.COM:committed_per_cycle::7 8006408 2.11% 97.92% # Number of insts commited each cycle
34 system.cpu.commit.COM:committed_per_cycle::8 7897771 2.08% 100.00% # Number of insts commited each cycle
35 system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
36 system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
37 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
38 system.cpu.commit.COM:committed_per_cycle::total 379244728 # Number of insts commited each cycle
39 system.cpu.commit.COM:count 602359916 # Number of instructions committed
40 system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions.
41 system.cpu.commit.COM:function_calls 997573 # Number of function calls committed.
42 system.cpu.commit.COM:int_insts 533522691 # Number of committed integer instructions.
43 system.cpu.commit.COM:loads 148952607 # Number of loads committed
44 system.cpu.commit.COM:membars 1328 # Number of memory barriers committed
45 system.cpu.commit.COM:refs 219173633 # Number of memory references committed
46 system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
47 system.cpu.commit.branchMispredicts 3891220 # The number of times a branch was mispredicted
48 system.cpu.commit.commitCommittedInsts 602359916 # The number of committed instructions
49 system.cpu.commit.commitNonSpecStalls 6310 # The number of times commit has been forced to stall to communicate backwards
50 system.cpu.commit.commitSquashedInsts 86859726 # The number of squashed insts skipped by commit
51 system.cpu.committedInsts 602359865 # Number of Instructions Simulated
52 system.cpu.committedInsts_total 602359865 # Number of Instructions Simulated
53 system.cpu.cpi 0.652478 # CPI: Cycles Per Instruction
54 system.cpu.cpi_total 0.652478 # CPI: Total CPI of All Threads
55 system.cpu.dcache.LoadLockedReq_accesses 1356 # number of LoadLockedReq accesses(hits+misses)
56 system.cpu.dcache.LoadLockedReq_avg_miss_latency 10607.142857 # average LoadLockedReq miss latency
57 system.cpu.dcache.LoadLockedReq_hits 1342 # number of LoadLockedReq hits
58 system.cpu.dcache.LoadLockedReq_miss_latency 148500 # number of LoadLockedReq miss cycles
59 system.cpu.dcache.LoadLockedReq_miss_rate 0.010324 # miss rate for LoadLockedReq accesses
60 system.cpu.dcache.LoadLockedReq_misses 14 # number of LoadLockedReq misses
61 system.cpu.dcache.LoadLockedReq_mshr_hits 14 # number of LoadLockedReq MSHR hits
62 system.cpu.dcache.ReadReq_accesses 139395234 # number of ReadReq accesses(hits+misses)
63 system.cpu.dcache.ReadReq_avg_miss_latency 13041.881358 # average ReadReq miss latency
64 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7904.223289 # average ReadReq mshr miss latency
65 system.cpu.dcache.ReadReq_hits 139153026 # number of ReadReq hits
66 system.cpu.dcache.ReadReq_miss_latency 3158848000 # number of ReadReq miss cycles
67 system.cpu.dcache.ReadReq_miss_rate 0.001738 # miss rate for ReadReq accesses
68 system.cpu.dcache.ReadReq_misses 242208 # number of ReadReq misses
69 system.cpu.dcache.ReadReq_mshr_hits 46247 # number of ReadReq MSHR hits
70 system.cpu.dcache.ReadReq_mshr_miss_latency 1548919500 # number of ReadReq MSHR miss cycles
71 system.cpu.dcache.ReadReq_mshr_miss_rate 0.001406 # mshr miss rate for ReadReq accesses
72 system.cpu.dcache.ReadReq_mshr_misses 195961 # number of ReadReq MSHR misses
73 system.cpu.dcache.StoreCondReq_accesses 1340 # number of StoreCondReq accesses(hits+misses)
74 system.cpu.dcache.StoreCondReq_hits 1340 # number of StoreCondReq hits
75 system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
76 system.cpu.dcache.WriteReq_avg_miss_latency 17910.212192 # average WriteReq miss latency
77 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10351.034278 # average WriteReq mshr miss latency
78 system.cpu.dcache.WriteReq_hits 67926304 # number of WriteReq hits
79 system.cpu.dcache.WriteReq_miss_latency 26708191996 # number of WriteReq miss cycles
80 system.cpu.dcache.WriteReq_miss_rate 0.021482 # miss rate for WriteReq accesses
81 system.cpu.dcache.WriteReq_misses 1491227 # number of WriteReq misses
82 system.cpu.dcache.WriteReq_mshr_hits 1243368 # number of WriteReq MSHR hits
83 system.cpu.dcache.WriteReq_mshr_miss_latency 2565597005 # number of WriteReq MSHR miss cycles
84 system.cpu.dcache.WriteReq_mshr_miss_rate 0.003571 # mshr miss rate for WriteReq accesses
85 system.cpu.dcache.WriteReq_mshr_misses 247859 # number of WriteReq MSHR misses
86 system.cpu.dcache.avg_blocked_cycles::no_mshrs 4376.771337 # average number of cycles each access was blocked
87 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
88 system.cpu.dcache.avg_refs 466.592209 # Average number of references to valid blocks.
89 system.cpu.dcache.blocked::no_mshrs 2191 # number of cycles access was blocked
90 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
91 system.cpu.dcache.blocked_cycles::no_mshrs 9589506 # number of cycles access was blocked
92 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
93 system.cpu.dcache.cache_copies 0 # number of cache copies performed
94 system.cpu.dcache.demand_accesses 208812765 # number of demand (read+write) accesses
95 system.cpu.dcache.demand_avg_miss_latency 17229.974009 # average overall miss latency
96 system.cpu.dcache.demand_avg_mshr_miss_latency 9270.687452 # average overall mshr miss latency
97 system.cpu.dcache.demand_hits 207079330 # number of demand (read+write) hits
98 system.cpu.dcache.demand_miss_latency 29867039996 # number of demand (read+write) miss cycles
99 system.cpu.dcache.demand_miss_rate 0.008301 # miss rate for demand accesses
100 system.cpu.dcache.demand_misses 1733435 # number of demand (read+write) misses
101 system.cpu.dcache.demand_mshr_hits 1289615 # number of demand (read+write) MSHR hits
102 system.cpu.dcache.demand_mshr_miss_latency 4114516505 # number of demand (read+write) MSHR miss cycles
103 system.cpu.dcache.demand_mshr_miss_rate 0.002125 # mshr miss rate for demand accesses
104 system.cpu.dcache.demand_mshr_misses 443820 # number of demand (read+write) MSHR misses
105 system.cpu.dcache.fast_writes 0 # number of fast writes performed
106 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
107 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
108 system.cpu.dcache.occ_%::0 0.999719 # Average percentage of cache occupancy
109 system.cpu.dcache.occ_blocks::0 4094.849519 # Average occupied blocks per context
110 system.cpu.dcache.overall_accesses 208812765 # number of overall (read+write) accesses
111 system.cpu.dcache.overall_avg_miss_latency 17229.974009 # average overall miss latency
112 system.cpu.dcache.overall_avg_mshr_miss_latency 9270.687452 # average overall mshr miss latency
113 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
114 system.cpu.dcache.overall_hits 207079330 # number of overall hits
115 system.cpu.dcache.overall_miss_latency 29867039996 # number of overall miss cycles
116 system.cpu.dcache.overall_miss_rate 0.008301 # miss rate for overall accesses
117 system.cpu.dcache.overall_misses 1733435 # number of overall misses
118 system.cpu.dcache.overall_mshr_hits 1289615 # number of overall MSHR hits
119 system.cpu.dcache.overall_mshr_miss_latency 4114516505 # number of overall MSHR miss cycles
120 system.cpu.dcache.overall_mshr_miss_rate 0.002125 # mshr miss rate for overall accesses
121 system.cpu.dcache.overall_mshr_misses 443820 # number of overall MSHR misses
122 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
123 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
124 system.cpu.dcache.replacements 439722 # number of replacements
125 system.cpu.dcache.sampled_refs 443818 # Sample count of references to valid blocks.
126 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
127 system.cpu.dcache.tagsinuse 4094.849519 # Cycle average of tags in use
128 system.cpu.dcache.total_refs 207082021 # Total number of references to valid blocks.
129 system.cpu.dcache.warmup_cycle 89315000 # Cycle when the warmup percentage was hit.
130 system.cpu.dcache.writebacks 394264 # number of writebacks
131 system.cpu.decode.DECODE:BlockedCycles 64227537 # Number of cycles decode is blocked
132 system.cpu.decode.DECODE:BranchMispred 1274 # Number of times decode detected a branch misprediction
133 system.cpu.decode.DECODE:BranchResolved 5983982 # Number of times decode resolved a branch
134 system.cpu.decode.DECODE:DecodedInsts 722350979 # Number of instructions handled by decode
135 system.cpu.decode.DECODE:IdleCycles 163737957 # Number of cycles decode is idle
136 system.cpu.decode.DECODE:RunCycles 138388023 # Number of cycles decode is running
137 system.cpu.decode.DECODE:SquashCycles 12871984 # Number of cycles decode is squashing
138 system.cpu.decode.DECODE:SquashedInsts 4747 # Number of squashed instructions handled by decode
139 system.cpu.decode.DECODE:UnblockCycles 12891210 # Number of cycles decode is unblocking
140 system.cpu.dtb.accesses 0 # DTB accesses
141 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
142 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
143 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
144 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
145 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
146 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
147 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
148 system.cpu.dtb.hits 0 # DTB hits
149 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
150 system.cpu.dtb.inst_hits 0 # ITB inst hits
151 system.cpu.dtb.inst_misses 0 # ITB inst misses
152 system.cpu.dtb.misses 0 # DTB misses
153 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
154 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
155 system.cpu.dtb.read_accesses 0 # DTB read accesses
156 system.cpu.dtb.read_hits 0 # DTB read hits
157 system.cpu.dtb.read_misses 0 # DTB read misses
158 system.cpu.dtb.write_accesses 0 # DTB write accesses
159 system.cpu.dtb.write_hits 0 # DTB write hits
160 system.cpu.dtb.write_misses 0 # DTB write misses
161 system.cpu.fetch.Branches 88398894 # Number of branches that fetch encountered
162 system.cpu.fetch.CacheLines 71395519 # Number of cache lines fetched
163 system.cpu.fetch.Cycles 153789076 # Number of cycles fetch has run and was not squashing or blocked
164 system.cpu.fetch.IcacheSquashes 942755 # Number of outstanding Icache misses that were squashed
165 system.cpu.fetch.Insts 689805737 # Number of instructions fetch has processed
166 system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
167 system.cpu.fetch.SquashCycles 4451587 # Number of cycles fetch has spent squashing
168 system.cpu.fetch.branchRate 0.224919 # Number of branch fetches per cycle
169 system.cpu.fetch.icacheStallCycles 71395519 # Number of cycles fetch is stalled on an Icache miss
170 system.cpu.fetch.predictedBranches 77137437 # Number of branches that fetch has predicted taken
171 system.cpu.fetch.rate 1.755114 # Number of inst fetches per cycle
172 system.cpu.fetch.rateDist::samples 392116711 # Number of instructions fetched each cycle (Total)
173 system.cpu.fetch.rateDist::mean 1.872365 # Number of instructions fetched each cycle (Total)
174 system.cpu.fetch.rateDist::stdev 2.899483 # Number of instructions fetched each cycle (Total)
175 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
176 system.cpu.fetch.rateDist::0 238327790 60.78% 60.78% # Number of instructions fetched each cycle (Total)
177 system.cpu.fetch.rateDist::1 25111973 6.40% 67.18% # Number of instructions fetched each cycle (Total)
178 system.cpu.fetch.rateDist::2 18227974 4.65% 71.83% # Number of instructions fetched each cycle (Total)
179 system.cpu.fetch.rateDist::3 22524916 5.74% 77.58% # Number of instructions fetched each cycle (Total)
180 system.cpu.fetch.rateDist::4 11352449 2.90% 80.47% # Number of instructions fetched each cycle (Total)
181 system.cpu.fetch.rateDist::5 12221762 3.12% 83.59% # Number of instructions fetched each cycle (Total)
182 system.cpu.fetch.rateDist::6 4491606 1.15% 84.73% # Number of instructions fetched each cycle (Total)
183 system.cpu.fetch.rateDist::7 7291145 1.86% 86.59% # Number of instructions fetched each cycle (Total)
184 system.cpu.fetch.rateDist::8 52567096 13.41% 100.00% # Number of instructions fetched each cycle (Total)
185 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
186 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
187 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
188 system.cpu.fetch.rateDist::total 392116711 # Number of instructions fetched each cycle (Total)
189 system.cpu.fp_regfile_reads 16 # number of floating regfile reads
190 system.cpu.icache.ReadReq_accesses 71395519 # number of ReadReq accesses(hits+misses)
191 system.cpu.icache.ReadReq_avg_miss_latency 35429.359823 # average ReadReq miss latency
192 system.cpu.icache.ReadReq_avg_mshr_miss_latency 34341.412742 # average ReadReq mshr miss latency
193 system.cpu.icache.ReadReq_hits 71394613 # number of ReadReq hits
194 system.cpu.icache.ReadReq_miss_latency 32099000 # number of ReadReq miss cycles
195 system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
196 system.cpu.icache.ReadReq_misses 906 # number of ReadReq misses
197 system.cpu.icache.ReadReq_mshr_hits 184 # number of ReadReq MSHR hits
198 system.cpu.icache.ReadReq_mshr_miss_latency 24794500 # number of ReadReq MSHR miss cycles
199 system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
200 system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses
201 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
202 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
203 system.cpu.icache.avg_refs 99159.184722 # Average number of references to valid blocks.
204 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
205 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
206 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
207 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
208 system.cpu.icache.cache_copies 0 # number of cache copies performed
209 system.cpu.icache.demand_accesses 71395519 # number of demand (read+write) accesses
210 system.cpu.icache.demand_avg_miss_latency 35429.359823 # average overall miss latency
211 system.cpu.icache.demand_avg_mshr_miss_latency 34341.412742 # average overall mshr miss latency
212 system.cpu.icache.demand_hits 71394613 # number of demand (read+write) hits
213 system.cpu.icache.demand_miss_latency 32099000 # number of demand (read+write) miss cycles
214 system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses
215 system.cpu.icache.demand_misses 906 # number of demand (read+write) misses
216 system.cpu.icache.demand_mshr_hits 184 # number of demand (read+write) MSHR hits
217 system.cpu.icache.demand_mshr_miss_latency 24794500 # number of demand (read+write) MSHR miss cycles
218 system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses
219 system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses
220 system.cpu.icache.fast_writes 0 # number of fast writes performed
221 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
222 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
223 system.cpu.icache.occ_%::0 0.307172 # Average percentage of cache occupancy
224 system.cpu.icache.occ_blocks::0 629.087764 # Average occupied blocks per context
225 system.cpu.icache.overall_accesses 71395519 # number of overall (read+write) accesses
226 system.cpu.icache.overall_avg_miss_latency 35429.359823 # average overall miss latency
227 system.cpu.icache.overall_avg_mshr_miss_latency 34341.412742 # average overall mshr miss latency
228 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
229 system.cpu.icache.overall_hits 71394613 # number of overall hits
230 system.cpu.icache.overall_miss_latency 32099000 # number of overall miss cycles
231 system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses
232 system.cpu.icache.overall_misses 906 # number of overall misses
233 system.cpu.icache.overall_mshr_hits 184 # number of overall MSHR hits
234 system.cpu.icache.overall_mshr_miss_latency 24794500 # number of overall MSHR miss cycles
235 system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses
236 system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses
237 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
238 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
239 system.cpu.icache.replacements 31 # number of replacements
240 system.cpu.icache.sampled_refs 720 # Sample count of references to valid blocks.
241 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
242 system.cpu.icache.tagsinuse 629.087764 # Cycle average of tags in use
243 system.cpu.icache.total_refs 71394613 # Total number of references to valid blocks.
244 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
245 system.cpu.icache.writebacks 0 # number of writebacks
246 system.cpu.idleCycles 909571 # Total number of cycles that the CPU has spent unscheduled due to idling
247 system.cpu.iew.EXEC:branches 73704412 # Number of branches executed
248 system.cpu.iew.EXEC:nop 61098 # number of nop insts executed
249 system.cpu.iew.EXEC:rate 1.622472 # Inst execution rate
250 system.cpu.iew.EXEC:refs 239165331 # number of memory reference insts executed
251 system.cpu.iew.EXEC:stores 73423365 # Number of stores executed
252 system.cpu.iew.EXEC:swp 0 # number of swp insts executed
253 system.cpu.iew.WB:consumers 736448308 # num instructions consuming a value
254 system.cpu.iew.WB:count 631945179 # cumulative count of insts written-back
255 system.cpu.iew.WB:fanout 0.594878 # average fanout of values written-back
256 system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
257 system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
258 system.cpu.iew.WB:producers 438096934 # num instructions producing a value
259 system.cpu.iew.WB:rate 1.607895 # insts written-back per cycle
260 system.cpu.iew.WB:sent 632881856 # cumulative count of insts sent to commit
261 system.cpu.iew.branchMispredicts 4305441 # Number of branch mispredicts detected at execute
262 system.cpu.iew.iewBlockCycles 811047 # Number of cycles IEW is blocking
263 system.cpu.iew.iewDispLoadInsts 176106355 # Number of dispatched load instructions
264 system.cpu.iew.iewDispNonSpecInsts 5819 # Number of dispatched non-speculative instructions
265 system.cpu.iew.iewDispSquashedInsts 2956217 # Number of squashed instructions skipped by dispatch
266 system.cpu.iew.iewDispStoreInsts 82187861 # Number of dispatched store instructions
267 system.cpu.iew.iewDispatchedInsts 689217371 # Number of instructions dispatched to IQ
268 system.cpu.iew.iewExecLoadInsts 165741966 # Number of load instructions executed
269 system.cpu.iew.iewExecSquashedInsts 6134058 # Number of squashed instructions skipped in execute
270 system.cpu.iew.iewExecutedInsts 637674087 # Number of executed instructions
271 system.cpu.iew.iewIQFullEvents 25252 # Number of times the IQ has become full, causing a stall
272 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
273 system.cpu.iew.iewLSQFullEvents 3721 # Number of times the LSQ has become full, causing a stall
274 system.cpu.iew.iewSquashCycles 12871984 # Number of cycles IEW is squashing
275 system.cpu.iew.iewUnblockCycles 65726 # Number of cycles IEW is unblocking
276 system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
277 system.cpu.iew.lsq.thread.0.cacheBlocked 8982 # Number of times an access to memory failed due to the cache being blocked
278 system.cpu.iew.lsq.thread.0.forwLoads 25082678 # Number of loads that had data forwarded from stores
279 system.cpu.iew.lsq.thread.0.ignoredResponses 87734 # Number of memory responses ignored because the instruction is squashed
280 system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
281 system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
282 system.cpu.iew.lsq.thread.0.memOrderViolation 611520 # Number of memory ordering violations
283 system.cpu.iew.lsq.thread.0.rescheduledLoads 15892 # Number of loads that were rescheduled
284 system.cpu.iew.lsq.thread.0.squashedLoads 27153747 # Number of loads squashed
285 system.cpu.iew.lsq.thread.0.squashedStores 11966835 # Number of stores squashed
286 system.cpu.iew.memOrderViolationEvents 611520 # Number of memory order violations
287 system.cpu.iew.predictedNotTakenIncorrect 628522 # Number of branches that were predicted not taken incorrectly
288 system.cpu.iew.predictedTakenIncorrect 3676919 # Number of branches that were predicted taken incorrectly
289 system.cpu.int_regfile_reads 1724767298 # number of integer regfile reads
290 system.cpu.int_regfile_writes 495432851 # number of integer regfile writes
291 system.cpu.ipc 1.532620 # IPC: Instructions Per Cycle
292 system.cpu.ipc_total 1.532620 # IPC: Total IPC of All Threads
293 system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
294 system.cpu.iq.ISSUE:FU_type_0::IntAlu 400863775 62.26% 62.26% # Type of FU issued
295 system.cpu.iq.ISSUE:FU_type_0::IntMult 6585 0.00% 62.27% # Type of FU issued
296 system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.27% # Type of FU issued
297 system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.27% # Type of FU issued
298 system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.27% # Type of FU issued
299 system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.27% # Type of FU issued
300 system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.27% # Type of FU issued
301 system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.27% # Type of FU issued
302 system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued
303 system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued
304 system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued
305 system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued
306 system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued
307 system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued
308 system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued
309 system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued
310 system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued
311 system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued
312 system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued
313 system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued
314 system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued
315 system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued
316 system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued
317 system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued
318 system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued
319 system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 62.27% # Type of FU issued
320 system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued
321 system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued
322 system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued
323 system.cpu.iq.ISSUE:FU_type_0::MemRead 168265891 26.14% 88.40% # Type of FU issued
324 system.cpu.iq.ISSUE:FU_type_0::MemWrite 74671891 11.60% 100.00% # Type of FU issued
325 system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
326 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
327 system.cpu.iq.ISSUE:FU_type_0::total 643808145 # Type of FU issued
328 system.cpu.iq.ISSUE:fu_busy_cnt 3945011 # FU busy when requested
329 system.cpu.iq.ISSUE:fu_busy_rate 0.006128 # FU busy rate (busy events/executed inst)
330 system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
331 system.cpu.iq.ISSUE:fu_full::IntAlu 107679 2.73% 2.73% # attempts to use FU when none available
332 system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.73% # attempts to use FU when none available
333 system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.73% # attempts to use FU when none available
334 system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.73% # attempts to use FU when none available
335 system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.73% # attempts to use FU when none available
336 system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.73% # attempts to use FU when none available
337 system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.73% # attempts to use FU when none available
338 system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.73% # attempts to use FU when none available
339 system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.73% # attempts to use FU when none available
340 system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.73% # attempts to use FU when none available
341 system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.73% # attempts to use FU when none available
342 system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.73% # attempts to use FU when none available
343 system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.73% # attempts to use FU when none available
344 system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.73% # attempts to use FU when none available
345 system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.73% # attempts to use FU when none available
346 system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.73% # attempts to use FU when none available
347 system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.73% # attempts to use FU when none available
348 system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.73% # attempts to use FU when none available
349 system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.73% # attempts to use FU when none available
350 system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.73% # attempts to use FU when none available
351 system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.73% # attempts to use FU when none available
352 system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.73% # attempts to use FU when none available
353 system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.73% # attempts to use FU when none available
354 system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.73% # attempts to use FU when none available
355 system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.73% # attempts to use FU when none available
356 system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.73% # attempts to use FU when none available
357 system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.73% # attempts to use FU when none available
358 system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.73% # attempts to use FU when none available
359 system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.73% # attempts to use FU when none available
360 system.cpu.iq.ISSUE:fu_full::MemRead 3407280 86.37% 89.10% # attempts to use FU when none available
361 system.cpu.iq.ISSUE:fu_full::MemWrite 430052 10.90% 100.00% # attempts to use FU when none available
362 system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
363 system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
364 system.cpu.iq.ISSUE:issued_per_cycle::samples 392116711 # Number of insts issued each cycle
365 system.cpu.iq.ISSUE:issued_per_cycle::mean 1.641879 # Number of insts issued each cycle
366 system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.551770 # Number of insts issued each cycle
367 system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
368 system.cpu.iq.ISSUE:issued_per_cycle::0 108904518 27.77% 27.77% # Number of insts issued each cycle
369 system.cpu.iq.ISSUE:issued_per_cycle::1 107421508 27.40% 55.17% # Number of insts issued each cycle
370 system.cpu.iq.ISSUE:issued_per_cycle::2 76290088 19.46% 74.62% # Number of insts issued each cycle
371 system.cpu.iq.ISSUE:issued_per_cycle::3 48454562 12.36% 86.98% # Number of insts issued each cycle
372 system.cpu.iq.ISSUE:issued_per_cycle::4 26882762 6.86% 93.84% # Number of insts issued each cycle
373 system.cpu.iq.ISSUE:issued_per_cycle::5 16851716 4.30% 98.14% # Number of insts issued each cycle
374 system.cpu.iq.ISSUE:issued_per_cycle::6 5414053 1.38% 99.52% # Number of insts issued each cycle
375 system.cpu.iq.ISSUE:issued_per_cycle::7 1011203 0.26% 99.77% # Number of insts issued each cycle
376 system.cpu.iq.ISSUE:issued_per_cycle::8 886301 0.23% 100.00% # Number of insts issued each cycle
377 system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
378 system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
379 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
380 system.cpu.iq.ISSUE:issued_per_cycle::total 392116711 # Number of insts issued each cycle
381 system.cpu.iq.ISSUE:rate 1.638079 # Inst issue rate
382 system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
383 system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
384 system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
385 system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
386 system.cpu.iq.int_alu_accesses 647753136 # Number of integer alu accesses
387 system.cpu.iq.int_inst_queue_reads 1684034505 # Number of integer instruction queue reads
388 system.cpu.iq.int_inst_queue_wakeup_accesses 631945163 # Number of integer instruction queue wakeup accesses
389 system.cpu.iq.int_inst_queue_writes 776263645 # Number of integer instruction queue writes
390 system.cpu.iq.iqInstsAdded 689149113 # Number of instructions added to the IQ (excludes non-spec)
391 system.cpu.iq.iqInstsIssued 643808145 # Number of instructions issued
392 system.cpu.iq.iqNonSpecInstsAdded 7160 # Number of non-speculative instructions added to the IQ
393 system.cpu.iq.iqSquashedInstsExamined 86496318 # Number of squashed instructions iterated over during squash; mainly for profiling
394 system.cpu.iq.iqSquashedInstsIssued 356529 # Number of squashed instructions issued
395 system.cpu.iq.iqSquashedNonSpecRemoved 850 # Number of squashed non-spec instructions that were removed
396 system.cpu.iq.iqSquashedOperandsExamined 162226931 # Number of squashed operands that are examined and possibly removed from graph
397 system.cpu.itb.accesses 0 # DTB accesses
398 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
399 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
400 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
401 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
402 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
403 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
404 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
405 system.cpu.itb.hits 0 # DTB hits
406 system.cpu.itb.inst_accesses 0 # ITB inst accesses
407 system.cpu.itb.inst_hits 0 # ITB inst hits
408 system.cpu.itb.inst_misses 0 # ITB inst misses
409 system.cpu.itb.misses 0 # DTB misses
410 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
411 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
412 system.cpu.itb.read_accesses 0 # DTB read accesses
413 system.cpu.itb.read_hits 0 # DTB read hits
414 system.cpu.itb.read_misses 0 # DTB read misses
415 system.cpu.itb.write_accesses 0 # DTB write accesses
416 system.cpu.itb.write_hits 0 # DTB write hits
417 system.cpu.itb.write_misses 0 # DTB write misses
418 system.cpu.l2cache.ReadExReq_accesses 247858 # number of ReadExReq accesses(hits+misses)
419 system.cpu.l2cache.ReadExReq_avg_miss_latency 34335.577877 # average ReadExReq miss latency
420 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31238.064273 # average ReadExReq mshr miss latency
421 system.cpu.l2cache.ReadExReq_hits 189420 # number of ReadExReq hits
422 system.cpu.l2cache.ReadExReq_miss_latency 2006502500 # number of ReadExReq miss cycles
423 system.cpu.l2cache.ReadExReq_miss_rate 0.235772 # miss rate for ReadExReq accesses
424 system.cpu.l2cache.ReadExReq_misses 58438 # number of ReadExReq misses
425 system.cpu.l2cache.ReadExReq_mshr_miss_latency 1825490000 # number of ReadExReq MSHR miss cycles
426 system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235772 # mshr miss rate for ReadExReq accesses
427 system.cpu.l2cache.ReadExReq_mshr_misses 58438 # number of ReadExReq MSHR misses
428 system.cpu.l2cache.ReadReq_accesses 196680 # number of ReadReq accesses(hits+misses)
429 system.cpu.l2cache.ReadReq_avg_miss_latency 34348.019439 # average ReadReq miss latency
430 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31098.694669 # average ReadReq mshr miss latency
431 system.cpu.l2cache.ReadReq_hits 163962 # number of ReadReq hits
432 system.cpu.l2cache.ReadReq_miss_latency 1123798500 # number of ReadReq miss cycles
433 system.cpu.l2cache.ReadReq_miss_rate 0.166351 # miss rate for ReadReq accesses
434 system.cpu.l2cache.ReadReq_misses 32718 # number of ReadReq misses
435 system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
436 system.cpu.l2cache.ReadReq_mshr_miss_latency 1017300500 # number of ReadReq MSHR miss cycles
437 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166321 # mshr miss rate for ReadReq accesses
438 system.cpu.l2cache.ReadReq_mshr_misses 32712 # number of ReadReq MSHR misses
439 system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses)
440 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 32000 # average UpgradeReq mshr miss latency
441 system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits
442 system.cpu.l2cache.UpgradeReq_miss_rate 0.500000 # miss rate for UpgradeReq accesses
443 system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
444 system.cpu.l2cache.UpgradeReq_mshr_miss_latency 32000 # number of UpgradeReq MSHR miss cycles
445 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.500000 # mshr miss rate for UpgradeReq accesses
446 system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
447 system.cpu.l2cache.Writeback_accesses 394264 # number of Writeback accesses(hits+misses)
448 system.cpu.l2cache.Writeback_hits 394264 # number of Writeback hits
449 system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6213.636364 # average number of cycles each access was blocked
450 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
451 system.cpu.l2cache.avg_refs 4.739861 # Average number of references to valid blocks.
452 system.cpu.l2cache.blocked::no_mshrs 330 # number of cycles access was blocked
453 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
454 system.cpu.l2cache.blocked_cycles::no_mshrs 2050500 # number of cycles access was blocked
455 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
456 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
457 system.cpu.l2cache.demand_accesses 444538 # number of demand (read+write) accesses
458 system.cpu.l2cache.demand_avg_miss_latency 34340.043442 # average overall miss latency
459 system.cpu.l2cache.demand_avg_mshr_miss_latency 31188.047175 # average overall mshr miss latency
460 system.cpu.l2cache.demand_hits 353382 # number of demand (read+write) hits
461 system.cpu.l2cache.demand_miss_latency 3130301000 # number of demand (read+write) miss cycles
462 system.cpu.l2cache.demand_miss_rate 0.205058 # miss rate for demand accesses
463 system.cpu.l2cache.demand_misses 91156 # number of demand (read+write) misses
464 system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
465 system.cpu.l2cache.demand_mshr_miss_latency 2842790500 # number of demand (read+write) MSHR miss cycles
466 system.cpu.l2cache.demand_mshr_miss_rate 0.205044 # mshr miss rate for demand accesses
467 system.cpu.l2cache.demand_mshr_misses 91150 # number of demand (read+write) MSHR misses
468 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
469 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
470 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
471 system.cpu.l2cache.occ_%::0 0.057260 # Average percentage of cache occupancy
472 system.cpu.l2cache.occ_%::1 0.487109 # Average percentage of cache occupancy
473 system.cpu.l2cache.occ_blocks::0 1876.282231 # Average occupied blocks per context
474 system.cpu.l2cache.occ_blocks::1 15961.603623 # Average occupied blocks per context
475 system.cpu.l2cache.overall_accesses 444538 # number of overall (read+write) accesses
476 system.cpu.l2cache.overall_avg_miss_latency 34340.043442 # average overall miss latency
477 system.cpu.l2cache.overall_avg_mshr_miss_latency 31188.047175 # average overall mshr miss latency
478 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
479 system.cpu.l2cache.overall_hits 353382 # number of overall hits
480 system.cpu.l2cache.overall_miss_latency 3130301000 # number of overall miss cycles
481 system.cpu.l2cache.overall_miss_rate 0.205058 # miss rate for overall accesses
482 system.cpu.l2cache.overall_misses 91156 # number of overall misses
483 system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits
484 system.cpu.l2cache.overall_mshr_miss_latency 2842790500 # number of overall MSHR miss cycles
485 system.cpu.l2cache.overall_mshr_miss_rate 0.205044 # mshr miss rate for overall accesses
486 system.cpu.l2cache.overall_mshr_misses 91150 # number of overall MSHR misses
487 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
488 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
489 system.cpu.l2cache.replacements 72953 # number of replacements
490 system.cpu.l2cache.sampled_refs 88472 # Sample count of references to valid blocks.
491 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
492 system.cpu.l2cache.tagsinuse 17837.885854 # Cycle average of tags in use
493 system.cpu.l2cache.total_refs 419345 # Total number of references to valid blocks.
494 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
495 system.cpu.l2cache.writebacks 58134 # number of writebacks
496 system.cpu.memDep0.conflictingLoads 25914382 # Number of conflicting loads.
497 system.cpu.memDep0.conflictingStores 23086559 # Number of conflicting stores.
498 system.cpu.memDep0.insertedLoads 176106355 # Number of loads inserted to the mem dependence unit.
499 system.cpu.memDep0.insertedStores 82187861 # Number of stores inserted to the mem dependence unit.
500 system.cpu.misc_regfile_reads 922126402 # number of misc regfile reads
501 system.cpu.misc_regfile_writes 2682 # number of misc regfile writes
502 system.cpu.numCycles 393026282 # number of cpu cycles simulated
503 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
504 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
505 system.cpu.rename.RENAME:BlockCycles 9628088 # Number of cycles rename is blocking
506 system.cpu.rename.RENAME:CommittedMaps 471021820 # Number of HB maps that are committed
507 system.cpu.rename.RENAME:IQFullEvents 50048668 # Number of times rename has blocked due to IQ full
508 system.cpu.rename.RENAME:IdleCycles 176696020 # Number of cycles rename is idle
509 system.cpu.rename.RENAME:LSQFullEvents 1915065 # Number of times rename has blocked due to LSQ full
510 system.cpu.rename.RENAME:RenameLookups 2034394520 # Number of register rename lookups that rename has made
511 system.cpu.rename.RENAME:RenamedInsts 711291370 # Number of instructions processed by rename
512 system.cpu.rename.RENAME:RenamedOperands 553214444 # Number of destination operands rename has renamed
513 system.cpu.rename.RENAME:RunCycles 138291459 # Number of cycles rename is running
514 system.cpu.rename.RENAME:SquashCycles 12871984 # Number of cycles rename is squashing
515 system.cpu.rename.RENAME:UnblockCycles 54521168 # Number of cycles rename is unblocking
516 system.cpu.rename.RENAME:UndoneMaps 82192621 # Number of HB maps that are undone due to squashing
517 system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups
518 system.cpu.rename.RENAME:int_rename_lookups 2034394424 # Number of integer rename lookups
519 system.cpu.rename.RENAME:serializeStallCycles 107992 # count of cycles rename stalled for serializing inst
520 system.cpu.rename.RENAME:serializingInsts 6480 # count of serializing insts renamed
521 system.cpu.rename.RENAME:skidInsts 91409775 # count of insts added to the skid buffer
522 system.cpu.rename.RENAME:tempSerializingInsts 6477 # count of temporary serializing insts renamed
523 system.cpu.rob.rob_reads 1060565987 # The number of ROB reads
524 system.cpu.rob.rob_writes 1391311417 # The number of ROB writes
525 system.cpu.timesIdled 36947 # Number of times that the entire CPU went into an idle state and unscheduled itself
526 system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
528 ---------- End Simulation Statistics ----------
projects / gem5.git / blob