2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.177099 # Number of seconds simulated
4 sim_ticks 177098873000 # Number of ticks simulated
5 sim_freq 1000000000000 # Frequency of simulated ticks
6 host_inst_rate 166594 # Simulator instruction rate (inst/s)
7 host_tick_rate 48979898 # Simulator tick rate (ticks/s)
8 host_mem_usage 214636 # Number of bytes of host memory used
9 host_seconds 3615.75 # Real time elapsed on the host
10 sim_insts 602359805 # Number of instructions simulated
11 system.cpu.dtb.inst_hits 0 # ITB inst hits
12 system.cpu.dtb.inst_misses 0 # ITB inst misses
13 system.cpu.dtb.read_hits 0 # DTB read hits
14 system.cpu.dtb.read_misses 0 # DTB read misses
15 system.cpu.dtb.write_hits 0 # DTB write hits
16 system.cpu.dtb.write_misses 0 # DTB write misses
17 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
18 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
19 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
20 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
21 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
22 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
23 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
24 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
25 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
26 system.cpu.dtb.read_accesses 0 # DTB read accesses
27 system.cpu.dtb.write_accesses 0 # DTB write accesses
28 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
29 system.cpu.dtb.hits 0 # DTB hits
30 system.cpu.dtb.misses 0 # DTB misses
31 system.cpu.dtb.accesses 0 # DTB accesses
32 system.cpu.itb.inst_hits 0 # ITB inst hits
33 system.cpu.itb.inst_misses 0 # ITB inst misses
34 system.cpu.itb.read_hits 0 # DTB read hits
35 system.cpu.itb.read_misses 0 # DTB read misses
36 system.cpu.itb.write_hits 0 # DTB write hits
37 system.cpu.itb.write_misses 0 # DTB write misses
38 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
39 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
40 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
41 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
42 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
43 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
44 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
45 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
46 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
47 system.cpu.itb.read_accesses 0 # DTB read accesses
48 system.cpu.itb.write_accesses 0 # DTB write accesses
49 system.cpu.itb.inst_accesses 0 # ITB inst accesses
50 system.cpu.itb.hits 0 # DTB hits
51 system.cpu.itb.misses 0 # DTB misses
52 system.cpu.itb.accesses 0 # DTB accesses
53 system.cpu.workload.num_syscalls 48 # Number of system calls
54 system.cpu.numCycles 354197747 # number of cpu cycles simulated
55 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
56 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
57 system.cpu.BPredUnit.lookups 91137531 # Number of BP lookups
58 system.cpu.BPredUnit.condPredicted 84224367 # Number of conditional branches predicted
59 system.cpu.BPredUnit.condIncorrect 4001637 # Number of conditional branches incorrect
60 system.cpu.BPredUnit.BTBLookups 86284566 # Number of BTB lookups
61 system.cpu.BPredUnit.BTBHits 80014553 # Number of BTB hits
62 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
63 system.cpu.BPredUnit.usedRAS 1704311 # Number of times the RAS was used to get a target.
64 system.cpu.BPredUnit.RASInCorrect 1605 # Number of incorrect RAS predictions.
65 system.cpu.fetch.icacheStallCycles 76786839 # Number of cycles fetch is stalled on an Icache miss
66 system.cpu.fetch.Insts 703787736 # Number of instructions fetch has processed
67 system.cpu.fetch.Branches 91137531 # Number of branches that fetch encountered
68 system.cpu.fetch.predictedBranches 81718864 # Number of branches that fetch has predicted taken
69 system.cpu.fetch.Cycles 159146597 # Number of cycles fetch has run and was not squashing or blocked
70 system.cpu.fetch.SquashCycles 18455506 # Number of cycles fetch has spent squashing
71 system.cpu.fetch.BlockedCycles 103039518 # Number of cycles fetch has spent blocked
72 system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
73 system.cpu.fetch.PendingTrapStallCycles 620 # Number of stall cycles due to pending traps
74 system.cpu.fetch.CacheLines 74412736 # Number of cache lines fetched
75 system.cpu.fetch.IcacheSquashes 1337820 # Number of outstanding Icache misses that were squashed
76 system.cpu.fetch.rateDist::samples 353350911 # Number of instructions fetched each cycle (Total)
77 system.cpu.fetch.rateDist::mean 2.128080 # Number of instructions fetched each cycle (Total)
78 system.cpu.fetch.rateDist::stdev 2.980798 # Number of instructions fetched each cycle (Total)
79 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
80 system.cpu.fetch.rateDist::0 194204457 54.96% 54.96% # Number of instructions fetched each cycle (Total)
81 system.cpu.fetch.rateDist::1 25620928 7.25% 62.21% # Number of instructions fetched each cycle (Total)
82 system.cpu.fetch.rateDist::2 19248235 5.45% 67.66% # Number of instructions fetched each cycle (Total)
83 system.cpu.fetch.rateDist::3 24404617 6.91% 74.57% # Number of instructions fetched each cycle (Total)
84 system.cpu.fetch.rateDist::4 11778472 3.33% 77.90% # Number of instructions fetched each cycle (Total)
85 system.cpu.fetch.rateDist::5 13409998 3.80% 81.69% # Number of instructions fetched each cycle (Total)
86 system.cpu.fetch.rateDist::6 4602257 1.30% 83.00% # Number of instructions fetched each cycle (Total)
87 system.cpu.fetch.rateDist::7 7805373 2.21% 85.21% # Number of instructions fetched each cycle (Total)
88 system.cpu.fetch.rateDist::8 52276574 14.79% 100.00% # Number of instructions fetched each cycle (Total)
89 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
90 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
91 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
92 system.cpu.fetch.rateDist::total 353350911 # Number of instructions fetched each cycle (Total)
93 system.cpu.fetch.branchRate 0.257307 # Number of branch fetches per cycle
94 system.cpu.fetch.rate 1.986991 # Number of inst fetches per cycle
95 system.cpu.decode.IdleCycles 98877750 # Number of cycles decode is idle
96 system.cpu.decode.BlockedCycles 83515155 # Number of cycles decode is blocked
97 system.cpu.decode.RunCycles 137076269 # Number of cycles decode is running
98 system.cpu.decode.UnblockCycles 19506954 # Number of cycles decode is unblocking
99 system.cpu.decode.SquashCycles 14374783 # Number of cycles decode is squashing
100 system.cpu.decode.BranchResolved 6301291 # Number of times decode resolved a branch
101 system.cpu.decode.BranchMispred 2551 # Number of times decode detected a branch misprediction
102 system.cpu.decode.DecodedInsts 740114896 # Number of instructions handled by decode
103 system.cpu.decode.SquashedInsts 7230 # Number of squashed instructions handled by decode
104 system.cpu.rename.SquashCycles 14374783 # Number of cycles rename is squashing
105 system.cpu.rename.IdleCycles 111843103 # Number of cycles rename is idle
106 system.cpu.rename.BlockCycles 9537973 # Number of cycles rename is blocking
107 system.cpu.rename.serializeStallCycles 119731 # count of cycles rename stalled for serializing inst
108 system.cpu.rename.RunCycles 143514381 # Number of cycles rename is running
109 system.cpu.rename.UnblockCycles 73960940 # Number of cycles rename is unblocking
110 system.cpu.rename.RenamedInsts 727174418 # Number of instructions processed by rename
111 system.cpu.rename.ROBFullEvents 286 # Number of times rename has blocked due to ROB full
112 system.cpu.rename.IQFullEvents 59845789 # Number of times rename has blocked due to IQ full
113 system.cpu.rename.LSQFullEvents 10289393 # Number of times rename has blocked due to LSQ full
114 system.cpu.rename.FullRegisterEvents 334 # Number of times there has been no free registers
115 system.cpu.rename.RenamedOperands 752889395 # Number of destination operands rename has renamed
116 system.cpu.rename.RenameLookups 3380302991 # Number of register rename lookups that rename has made
117 system.cpu.rename.int_rename_lookups 3380302863 # Number of integer rename lookups
118 system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
119 system.cpu.rename.CommittedMaps 627417394 # Number of HB maps that are committed
120 system.cpu.rename.UndoneMaps 125472001 # Number of HB maps that are undone due to squashing
121 system.cpu.rename.serializingInsts 13297 # count of serializing insts renamed
122 system.cpu.rename.tempSerializingInsts 13294 # count of temporary serializing insts renamed
123 system.cpu.rename.skidInsts 132095966 # count of insts added to the skid buffer
124 system.cpu.memDep0.insertedLoads 179744866 # Number of loads inserted to the mem dependence unit.
125 system.cpu.memDep0.insertedStores 82855502 # Number of stores inserted to the mem dependence unit.
126 system.cpu.memDep0.conflictingLoads 19180586 # Number of conflicting loads.
127 system.cpu.memDep0.conflictingStores 24795671 # Number of conflicting stores.
128 system.cpu.iq.iqInstsAdded 702443112 # Number of instructions added to the IQ (excludes non-spec)
129 system.cpu.iq.iqNonSpecInstsAdded 9504 # Number of non-speculative instructions added to the IQ
130 system.cpu.iq.iqInstsIssued 663038146 # Number of instructions issued
131 system.cpu.iq.iqSquashedInstsIssued 743101 # Number of squashed instructions issued
132 system.cpu.iq.iqSquashedInstsExamined 99536301 # Number of squashed instructions iterated over during squash; mainly for profiling
133 system.cpu.iq.iqSquashedOperandsExamined 237037166 # Number of squashed operands that are examined and possibly removed from graph
134 system.cpu.iq.iqSquashedNonSpecRemoved 3158 # Number of squashed non-spec instructions that were removed
135 system.cpu.iq.issued_per_cycle::samples 353350911 # Number of insts issued each cycle
136 system.cpu.iq.issued_per_cycle::mean 1.876430 # Number of insts issued each cycle
137 system.cpu.iq.issued_per_cycle::stdev 1.733239 # Number of insts issued each cycle
138 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
139 system.cpu.iq.issued_per_cycle::0 85428360 24.18% 24.18% # Number of insts issued each cycle
140 system.cpu.iq.issued_per_cycle::1 90441308 25.60% 49.77% # Number of insts issued each cycle
141 system.cpu.iq.issued_per_cycle::2 76153703 21.55% 71.32% # Number of insts issued each cycle
142 system.cpu.iq.issued_per_cycle::3 42544702 12.04% 83.36% # Number of insts issued each cycle
143 system.cpu.iq.issued_per_cycle::4 25577763 7.24% 90.60% # Number of insts issued each cycle
144 system.cpu.iq.issued_per_cycle::5 18033700 5.10% 95.71% # Number of insts issued each cycle
145 system.cpu.iq.issued_per_cycle::6 7283699 2.06% 97.77% # Number of insts issued each cycle
146 system.cpu.iq.issued_per_cycle::7 6627828 1.88% 99.64% # Number of insts issued each cycle
147 system.cpu.iq.issued_per_cycle::8 1259848 0.36% 100.00% # Number of insts issued each cycle
148 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
149 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
150 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
151 system.cpu.iq.issued_per_cycle::total 353350911 # Number of insts issued each cycle
152 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
153 system.cpu.iq.fu_full::IntAlu 202982 4.88% 4.88% # attempts to use FU when none available
154 system.cpu.iq.fu_full::IntMult 0 0.00% 4.88% # attempts to use FU when none available
155 system.cpu.iq.fu_full::IntDiv 0 0.00% 4.88% # attempts to use FU when none available
156 system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.88% # attempts to use FU when none available
157 system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.88% # attempts to use FU when none available
158 system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.88% # attempts to use FU when none available
159 system.cpu.iq.fu_full::FloatMult 0 0.00% 4.88% # attempts to use FU when none available
160 system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.88% # attempts to use FU when none available
161 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.88% # attempts to use FU when none available
162 system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.88% # attempts to use FU when none available
163 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.88% # attempts to use FU when none available
164 system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.88% # attempts to use FU when none available
165 system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.88% # attempts to use FU when none available
166 system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.88% # attempts to use FU when none available
167 system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.88% # attempts to use FU when none available
168 system.cpu.iq.fu_full::SimdMult 0 0.00% 4.88% # attempts to use FU when none available
169 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.88% # attempts to use FU when none available
170 system.cpu.iq.fu_full::SimdShift 0 0.00% 4.88% # attempts to use FU when none available
171 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.88% # attempts to use FU when none available
172 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.88% # attempts to use FU when none available
173 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.88% # attempts to use FU when none available
174 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.88% # attempts to use FU when none available
175 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.88% # attempts to use FU when none available
176 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.88% # attempts to use FU when none available
177 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.88% # attempts to use FU when none available
178 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.88% # attempts to use FU when none available
179 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.88% # attempts to use FU when none available
180 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.88% # attempts to use FU when none available
181 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.88% # attempts to use FU when none available
182 system.cpu.iq.fu_full::MemRead 2990868 71.85% 76.73% # attempts to use FU when none available
183 system.cpu.iq.fu_full::MemWrite 968637 23.27% 100.00% # attempts to use FU when none available
184 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
185 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
186 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
187 system.cpu.iq.FU_type_0::IntAlu 412586864 62.23% 62.23% # Type of FU issued
188 system.cpu.iq.FU_type_0::IntMult 6565 0.00% 62.23% # Type of FU issued
189 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.23% # Type of FU issued
190 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.23% # Type of FU issued
191 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.23% # Type of FU issued
192 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.23% # Type of FU issued
193 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.23% # Type of FU issued
194 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.23% # Type of FU issued
195 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.23% # Type of FU issued
196 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.23% # Type of FU issued
197 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.23% # Type of FU issued
198 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.23% # Type of FU issued
199 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.23% # Type of FU issued
200 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.23% # Type of FU issued
201 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.23% # Type of FU issued
202 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.23% # Type of FU issued
203 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.23% # Type of FU issued
204 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.23% # Type of FU issued
205 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.23% # Type of FU issued
206 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.23% # Type of FU issued
207 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.23% # Type of FU issued
208 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.23% # Type of FU issued
209 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.23% # Type of FU issued
210 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.23% # Type of FU issued
211 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.23% # Type of FU issued
212 system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.23% # Type of FU issued
213 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.23% # Type of FU issued
214 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.23% # Type of FU issued
215 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.23% # Type of FU issued
216 system.cpu.iq.FU_type_0::MemRead 172485012 26.01% 88.24% # Type of FU issued
217 system.cpu.iq.FU_type_0::MemWrite 77959702 11.76% 100.00% # Type of FU issued
218 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
219 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
220 system.cpu.iq.FU_type_0::total 663038146 # Type of FU issued
221 system.cpu.iq.rate 1.871943 # Inst issue rate
222 system.cpu.iq.fu_busy_cnt 4162487 # FU busy when requested
223 system.cpu.iq.fu_busy_rate 0.006278 # FU busy rate (busy events/executed inst)
224 system.cpu.iq.int_inst_queue_reads 1684332755 # Number of integer instruction queue reads
225 system.cpu.iq.int_inst_queue_writes 802000478 # Number of integer instruction queue writes
226 system.cpu.iq.int_inst_queue_wakeup_accesses 650204091 # Number of integer instruction queue wakeup accesses
227 system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
228 system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
229 system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
230 system.cpu.iq.int_alu_accesses 667200613 # Number of integer alu accesses
231 system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
232 system.cpu.iew.lsq.thread0.forwLoads 29662170 # Number of loads that had data forwarded from stores
233 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
234 system.cpu.iew.lsq.thread0.squashedLoads 30792271 # Number of loads squashed
235 system.cpu.iew.lsq.thread0.ignoredResponses 224606 # Number of memory responses ignored because the instruction is squashed
236 system.cpu.iew.lsq.thread0.memOrderViolation 11800 # Number of memory ordering violations
237 system.cpu.iew.lsq.thread0.squashedStores 12634488 # Number of stores squashed
238 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
239 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
240 system.cpu.iew.lsq.thread0.rescheduledLoads 13695 # Number of loads that were rescheduled
241 system.cpu.iew.lsq.thread0.cacheBlocked 12640 # Number of times an access to memory failed due to the cache being blocked
242 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
243 system.cpu.iew.iewSquashCycles 14374783 # Number of cycles IEW is squashing
244 system.cpu.iew.iewBlockCycles 826341 # Number of cycles IEW is blocking
245 system.cpu.iew.iewUnblockCycles 58736 # Number of cycles IEW is unblocking
246 system.cpu.iew.iewDispatchedInsts 702522112 # Number of instructions dispatched to IQ
247 system.cpu.iew.iewDispSquashedInsts 1853549 # Number of squashed instructions skipped by dispatch
248 system.cpu.iew.iewDispLoadInsts 179744866 # Number of dispatched load instructions
249 system.cpu.iew.iewDispStoreInsts 82855502 # Number of dispatched store instructions
250 system.cpu.iew.iewDispNonSpecInsts 8175 # Number of dispatched non-speculative instructions
251 system.cpu.iew.iewIQFullEvents 13020 # Number of times the IQ has become full, causing a stall
252 system.cpu.iew.iewLSQFullEvents 5275 # Number of times the LSQ has become full, causing a stall
253 system.cpu.iew.memOrderViolationEvents 11800 # Number of memory order violations
254 system.cpu.iew.predictedTakenIncorrect 4156328 # Number of branches that were predicted taken incorrectly
255 system.cpu.iew.predictedNotTakenIncorrect 497844 # Number of branches that were predicted not taken incorrectly
256 system.cpu.iew.branchMispredicts 4654172 # Number of branch mispredicts detected at execute
257 system.cpu.iew.iewExecutedInsts 656067860 # Number of executed instructions
258 system.cpu.iew.iewExecLoadInsts 169121282 # Number of load instructions executed
259 system.cpu.iew.iewExecSquashedInsts 6970286 # Number of squashed instructions skipped in execute
260 system.cpu.iew.exec_swp 0 # number of swp insts executed
261 system.cpu.iew.exec_nop 69496 # number of nop insts executed
262 system.cpu.iew.exec_refs 245806937 # number of memory reference insts executed
263 system.cpu.iew.exec_branches 76463124 # Number of branches executed
264 system.cpu.iew.exec_stores 76685655 # Number of stores executed
265 system.cpu.iew.exec_rate 1.852264 # Inst execution rate
266 system.cpu.iew.wb_sent 652210228 # cumulative count of insts sent to commit
267 system.cpu.iew.wb_count 650204107 # cumulative count of insts written-back
268 system.cpu.iew.wb_producers 423315850 # num instructions producing a value
269 system.cpu.iew.wb_consumers 657380921 # num instructions consuming a value
270 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
271 system.cpu.iew.wb_rate 1.835709 # insts written-back per cycle
272 system.cpu.iew.wb_fanout 0.643943 # average fanout of values written-back
273 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
274 system.cpu.commit.commitCommittedInsts 602359856 # The number of committed instructions
275 system.cpu.commit.commitSquashedInsts 100172226 # The number of squashed insts skipped by commit
276 system.cpu.commit.commitNonSpecStalls 6346 # The number of times commit has been forced to stall to communicate backwards
277 system.cpu.commit.branchMispredicts 4060978 # The number of times a branch was mispredicted
278 system.cpu.commit.committed_per_cycle::samples 338976129 # Number of insts commited each cycle
279 system.cpu.commit.committed_per_cycle::mean 1.776998 # Number of insts commited each cycle
280 system.cpu.commit.committed_per_cycle::stdev 2.152747 # Number of insts commited each cycle
281 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
282 system.cpu.commit.committed_per_cycle::0 108154848 31.91% 31.91% # Number of insts commited each cycle
283 system.cpu.commit.committed_per_cycle::1 106518775 31.42% 63.33% # Number of insts commited each cycle
284 system.cpu.commit.committed_per_cycle::2 49308103 14.55% 77.88% # Number of insts commited each cycle
285 system.cpu.commit.committed_per_cycle::3 9862304 2.91% 80.79% # Number of insts commited each cycle
286 system.cpu.commit.committed_per_cycle::4 23329668 6.88% 87.67% # Number of insts commited each cycle
287 system.cpu.commit.committed_per_cycle::5 14306268 4.22% 91.89% # Number of insts commited each cycle
288 system.cpu.commit.committed_per_cycle::6 7919036 2.34% 94.22% # Number of insts commited each cycle
289 system.cpu.commit.committed_per_cycle::7 1343281 0.40% 94.62% # Number of insts commited each cycle
290 system.cpu.commit.committed_per_cycle::8 18233846 5.38% 100.00% # Number of insts commited each cycle
291 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
292 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
293 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
294 system.cpu.commit.committed_per_cycle::total 338976129 # Number of insts commited each cycle
295 system.cpu.commit.count 602359856 # Number of instructions committed
296 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
297 system.cpu.commit.refs 219173609 # Number of memory references committed
298 system.cpu.commit.loads 148952595 # Number of loads committed
299 system.cpu.commit.membars 1328 # Number of memory barriers committed
300 system.cpu.commit.branches 70828602 # Number of branches committed
301 system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
302 system.cpu.commit.int_insts 533522643 # Number of committed integer instructions.
303 system.cpu.commit.function_calls 997573 # Number of function calls committed.
304 system.cpu.commit.bw_lim_events 18233846 # number cycles where commit BW limit reached
305 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
306 system.cpu.rob.rob_reads 1023273753 # The number of ROB reads
307 system.cpu.rob.rob_writes 1419480895 # The number of ROB writes
308 system.cpu.timesIdled 37084 # Number of times that the entire CPU went into an idle state and unscheduled itself
309 system.cpu.idleCycles 846836 # Total number of cycles that the CPU has spent unscheduled due to idling
310 system.cpu.committedInsts 602359805 # Number of Instructions Simulated
311 system.cpu.committedInsts_total 602359805 # Number of Instructions Simulated
312 system.cpu.cpi 0.588017 # CPI: Cycles Per Instruction
313 system.cpu.cpi_total 0.588017 # CPI: Total CPI of All Threads
314 system.cpu.ipc 1.700631 # IPC: Instructions Per Cycle
315 system.cpu.ipc_total 1.700631 # IPC: Total IPC of All Threads
316 system.cpu.int_regfile_reads 3275893571 # number of integer regfile reads
317 system.cpu.int_regfile_writes 675997918 # number of integer regfile writes
318 system.cpu.fp_regfile_reads 16 # number of floating regfile reads
319 system.cpu.misc_regfile_reads 943643021 # number of misc regfile reads
320 system.cpu.misc_regfile_writes 2658 # number of misc regfile writes
321 system.cpu.icache.replacements 41 # number of replacements
322 system.cpu.icache.tagsinuse 657.503073 # Cycle average of tags in use
323 system.cpu.icache.total_refs 74411745 # Total number of references to valid blocks.
324 system.cpu.icache.sampled_refs 766 # Sample count of references to valid blocks.
325 system.cpu.icache.avg_refs 97143.270235 # Average number of references to valid blocks.
326 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
327 system.cpu.icache.occ_blocks::0 657.503073 # Average occupied blocks per context
328 system.cpu.icache.occ_percent::0 0.321046 # Average percentage of cache occupancy
329 system.cpu.icache.ReadReq_hits 74411745 # number of ReadReq hits
330 system.cpu.icache.demand_hits 74411745 # number of demand (read+write) hits
331 system.cpu.icache.overall_hits 74411745 # number of overall hits
332 system.cpu.icache.ReadReq_misses 991 # number of ReadReq misses
333 system.cpu.icache.demand_misses 991 # number of demand (read+write) misses
334 system.cpu.icache.overall_misses 991 # number of overall misses
335 system.cpu.icache.ReadReq_miss_latency 34848500 # number of ReadReq miss cycles
336 system.cpu.icache.demand_miss_latency 34848500 # number of demand (read+write) miss cycles
337 system.cpu.icache.overall_miss_latency 34848500 # number of overall miss cycles
338 system.cpu.icache.ReadReq_accesses 74412736 # number of ReadReq accesses(hits+misses)
339 system.cpu.icache.demand_accesses 74412736 # number of demand (read+write) accesses
340 system.cpu.icache.overall_accesses 74412736 # number of overall (read+write) accesses
341 system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
342 system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses
343 system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses
344 system.cpu.icache.ReadReq_avg_miss_latency 35164.984864 # average ReadReq miss latency
345 system.cpu.icache.demand_avg_miss_latency 35164.984864 # average overall miss latency
346 system.cpu.icache.overall_avg_miss_latency 35164.984864 # average overall miss latency
347 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
348 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
349 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
350 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
351 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
352 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
353 system.cpu.icache.fast_writes 0 # number of fast writes performed
354 system.cpu.icache.cache_copies 0 # number of cache copies performed
355 system.cpu.icache.writebacks 0 # number of writebacks
356 system.cpu.icache.ReadReq_mshr_hits 225 # number of ReadReq MSHR hits
357 system.cpu.icache.demand_mshr_hits 225 # number of demand (read+write) MSHR hits
358 system.cpu.icache.overall_mshr_hits 225 # number of overall MSHR hits
359 system.cpu.icache.ReadReq_mshr_misses 766 # number of ReadReq MSHR misses
360 system.cpu.icache.demand_mshr_misses 766 # number of demand (read+write) MSHR misses
361 system.cpu.icache.overall_mshr_misses 766 # number of overall MSHR misses
362 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
363 system.cpu.icache.ReadReq_mshr_miss_latency 26233500 # number of ReadReq MSHR miss cycles
364 system.cpu.icache.demand_mshr_miss_latency 26233500 # number of demand (read+write) MSHR miss cycles
365 system.cpu.icache.overall_mshr_miss_latency 26233500 # number of overall MSHR miss cycles
366 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
367 system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
368 system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses
369 system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses
370 system.cpu.icache.ReadReq_avg_mshr_miss_latency 34247.389034 # average ReadReq mshr miss latency
371 system.cpu.icache.demand_avg_mshr_miss_latency 34247.389034 # average overall mshr miss latency
372 system.cpu.icache.overall_avg_mshr_miss_latency 34247.389034 # average overall mshr miss latency
373 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
374 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
375 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
376 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
377 system.cpu.dcache.replacements 441233 # number of replacements
378 system.cpu.dcache.tagsinuse 4094.750739 # Cycle average of tags in use
379 system.cpu.dcache.total_refs 205781738 # Total number of references to valid blocks.
380 system.cpu.dcache.sampled_refs 445329 # Sample count of references to valid blocks.
381 system.cpu.dcache.avg_refs 462.089237 # Average number of references to valid blocks.
382 system.cpu.dcache.warmup_cycle 87973000 # Cycle when the warmup percentage was hit.
383 system.cpu.dcache.occ_blocks::0 4094.750739 # Average occupied blocks per context
384 system.cpu.dcache.occ_percent::0 0.999695 # Average percentage of cache occupancy
385 system.cpu.dcache.ReadReq_hits 137926945 # number of ReadReq hits
386 system.cpu.dcache.WriteReq_hits 67852137 # number of WriteReq hits
387 system.cpu.dcache.LoadLockedReq_hits 1328 # number of LoadLockedReq hits
388 system.cpu.dcache.StoreCondReq_hits 1328 # number of StoreCondReq hits
389 system.cpu.dcache.demand_hits 205779082 # number of demand (read+write) hits
390 system.cpu.dcache.overall_hits 205779082 # number of overall hits
391 system.cpu.dcache.ReadReq_misses 249074 # number of ReadReq misses
392 system.cpu.dcache.WriteReq_misses 1565394 # number of WriteReq misses
393 system.cpu.dcache.LoadLockedReq_misses 11 # number of LoadLockedReq misses
394 system.cpu.dcache.demand_misses 1814468 # number of demand (read+write) misses
395 system.cpu.dcache.overall_misses 1814468 # number of overall misses
396 system.cpu.dcache.ReadReq_miss_latency 3282849000 # number of ReadReq miss cycles
397 system.cpu.dcache.WriteReq_miss_latency 27038418025 # number of WriteReq miss cycles
398 system.cpu.dcache.LoadLockedReq_miss_latency 203000 # number of LoadLockedReq miss cycles
399 system.cpu.dcache.demand_miss_latency 30321267025 # number of demand (read+write) miss cycles
400 system.cpu.dcache.overall_miss_latency 30321267025 # number of overall miss cycles
401 system.cpu.dcache.ReadReq_accesses 138176019 # number of ReadReq accesses(hits+misses)
402 system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
403 system.cpu.dcache.LoadLockedReq_accesses 1339 # number of LoadLockedReq accesses(hits+misses)
404 system.cpu.dcache.StoreCondReq_accesses 1328 # number of StoreCondReq accesses(hits+misses)
405 system.cpu.dcache.demand_accesses 207593550 # number of demand (read+write) accesses
406 system.cpu.dcache.overall_accesses 207593550 # number of overall (read+write) accesses
407 system.cpu.dcache.ReadReq_miss_rate 0.001803 # miss rate for ReadReq accesses
408 system.cpu.dcache.WriteReq_miss_rate 0.022550 # miss rate for WriteReq accesses
409 system.cpu.dcache.LoadLockedReq_miss_rate 0.008215 # miss rate for LoadLockedReq accesses
410 system.cpu.dcache.demand_miss_rate 0.008740 # miss rate for demand accesses
411 system.cpu.dcache.overall_miss_rate 0.008740 # miss rate for overall accesses
412 system.cpu.dcache.ReadReq_avg_miss_latency 13180.215518 # average ReadReq miss latency
413 system.cpu.dcache.WriteReq_avg_miss_latency 17272.595925 # average WriteReq miss latency
414 system.cpu.dcache.LoadLockedReq_avg_miss_latency 18454.545455 # average LoadLockedReq miss latency
415 system.cpu.dcache.demand_avg_miss_latency 16710.830406 # average overall miss latency
416 system.cpu.dcache.overall_avg_miss_latency 16710.830406 # average overall miss latency
417 system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked
418 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
419 system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked
420 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
421 system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 # average number of cycles each access was blocked
422 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
423 system.cpu.dcache.fast_writes 0 # number of fast writes performed
424 system.cpu.dcache.cache_copies 0 # number of cache copies performed
425 system.cpu.dcache.writebacks 395275 # number of writebacks
426 system.cpu.dcache.ReadReq_mshr_hits 51126 # number of ReadReq MSHR hits
427 system.cpu.dcache.WriteReq_mshr_hits 1318013 # number of WriteReq MSHR hits
428 system.cpu.dcache.LoadLockedReq_mshr_hits 11 # number of LoadLockedReq MSHR hits
429 system.cpu.dcache.demand_mshr_hits 1369139 # number of demand (read+write) MSHR hits
430 system.cpu.dcache.overall_mshr_hits 1369139 # number of overall MSHR hits
431 system.cpu.dcache.ReadReq_mshr_misses 197948 # number of ReadReq MSHR misses
432 system.cpu.dcache.WriteReq_mshr_misses 247381 # number of WriteReq MSHR misses
433 system.cpu.dcache.demand_mshr_misses 445329 # number of demand (read+write) MSHR misses
434 system.cpu.dcache.overall_mshr_misses 445329 # number of overall MSHR misses
435 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
436 system.cpu.dcache.ReadReq_mshr_miss_latency 1625134500 # number of ReadReq MSHR miss cycles
437 system.cpu.dcache.WriteReq_mshr_miss_latency 2544872027 # number of WriteReq MSHR miss cycles
438 system.cpu.dcache.demand_mshr_miss_latency 4170006527 # number of demand (read+write) MSHR miss cycles
439 system.cpu.dcache.overall_mshr_miss_latency 4170006527 # number of overall MSHR miss cycles
440 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
441 system.cpu.dcache.ReadReq_mshr_miss_rate 0.001433 # mshr miss rate for ReadReq accesses
442 system.cpu.dcache.WriteReq_mshr_miss_rate 0.003564 # mshr miss rate for WriteReq accesses
443 system.cpu.dcache.demand_mshr_miss_rate 0.002145 # mshr miss rate for demand accesses
444 system.cpu.dcache.overall_mshr_miss_rate 0.002145 # mshr miss rate for overall accesses
445 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8209.906137 # average ReadReq mshr miss latency
446 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10287.257417 # average WriteReq mshr miss latency
447 system.cpu.dcache.demand_avg_mshr_miss_latency 9363.878227 # average overall mshr miss latency
448 system.cpu.dcache.overall_avg_mshr_miss_latency 9363.878227 # average overall mshr miss latency
449 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
450 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
451 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
452 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
453 system.cpu.l2cache.replacements 72960 # number of replacements
454 system.cpu.l2cache.tagsinuse 17805.724339 # Cycle average of tags in use
455 system.cpu.l2cache.total_refs 422235 # Total number of references to valid blocks.
456 system.cpu.l2cache.sampled_refs 88493 # Sample count of references to valid blocks.
457 system.cpu.l2cache.avg_refs 4.771394 # Average number of references to valid blocks.
458 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
459 system.cpu.l2cache.occ_blocks::0 1879.670498 # Average occupied blocks per context
460 system.cpu.l2cache.occ_blocks::1 15926.053841 # Average occupied blocks per context
461 system.cpu.l2cache.occ_percent::0 0.057363 # Average percentage of cache occupancy
462 system.cpu.l2cache.occ_percent::1 0.486025 # Average percentage of cache occupancy
463 system.cpu.l2cache.ReadReq_hits 165899 # number of ReadReq hits
464 system.cpu.l2cache.Writeback_hits 395275 # number of Writeback hits
465 system.cpu.l2cache.ReadExReq_hits 189031 # number of ReadExReq hits
466 system.cpu.l2cache.demand_hits 354930 # number of demand (read+write) hits
467 system.cpu.l2cache.overall_hits 354930 # number of overall hits
468 system.cpu.l2cache.ReadReq_misses 32812 # number of ReadReq misses
469 system.cpu.l2cache.ReadExReq_misses 58353 # number of ReadExReq misses
470 system.cpu.l2cache.demand_misses 91165 # number of demand (read+write) misses
471 system.cpu.l2cache.overall_misses 91165 # number of overall misses
472 system.cpu.l2cache.ReadReq_miss_latency 1126662000 # number of ReadReq miss cycles
473 system.cpu.l2cache.ReadExReq_miss_latency 2003366500 # number of ReadExReq miss cycles
474 system.cpu.l2cache.demand_miss_latency 3130028500 # number of demand (read+write) miss cycles
475 system.cpu.l2cache.overall_miss_latency 3130028500 # number of overall miss cycles
476 system.cpu.l2cache.ReadReq_accesses 198711 # number of ReadReq accesses(hits+misses)
477 system.cpu.l2cache.Writeback_accesses 395275 # number of Writeback accesses(hits+misses)
478 system.cpu.l2cache.ReadExReq_accesses 247384 # number of ReadExReq accesses(hits+misses)
479 system.cpu.l2cache.demand_accesses 446095 # number of demand (read+write) accesses
480 system.cpu.l2cache.overall_accesses 446095 # number of overall (read+write) accesses
481 system.cpu.l2cache.ReadReq_miss_rate 0.165124 # miss rate for ReadReq accesses
482 system.cpu.l2cache.ReadExReq_miss_rate 0.235880 # miss rate for ReadExReq accesses
483 system.cpu.l2cache.demand_miss_rate 0.204362 # miss rate for demand accesses
484 system.cpu.l2cache.overall_miss_rate 0.204362 # miss rate for overall accesses
485 system.cpu.l2cache.ReadReq_avg_miss_latency 34336.888943 # average ReadReq miss latency
486 system.cpu.l2cache.ReadExReq_avg_miss_latency 34331.850976 # average ReadExReq miss latency
487 system.cpu.l2cache.demand_avg_miss_latency 34333.664235 # average overall miss latency
488 system.cpu.l2cache.overall_avg_miss_latency 34333.664235 # average overall miss latency
489 system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked
490 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
491 system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked
492 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
493 system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 # average number of cycles each access was blocked
494 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
495 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
496 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
497 system.cpu.l2cache.writebacks 58128 # number of writebacks
498 system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
499 system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
500 system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
501 system.cpu.l2cache.ReadReq_mshr_misses 32801 # number of ReadReq MSHR misses
502 system.cpu.l2cache.ReadExReq_mshr_misses 58353 # number of ReadExReq MSHR misses
503 system.cpu.l2cache.demand_mshr_misses 91154 # number of demand (read+write) MSHR misses
504 system.cpu.l2cache.overall_mshr_misses 91154 # number of overall MSHR misses
505 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
506 system.cpu.l2cache.ReadReq_mshr_miss_latency 1019608000 # number of ReadReq MSHR miss cycles
507 system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822407000 # number of ReadExReq MSHR miss cycles
508 system.cpu.l2cache.demand_mshr_miss_latency 2842015000 # number of demand (read+write) MSHR miss cycles
509 system.cpu.l2cache.overall_mshr_miss_latency 2842015000 # number of overall MSHR miss cycles
510 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
511 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165069 # mshr miss rate for ReadReq accesses
512 system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235880 # mshr miss rate for ReadExReq accesses
513 system.cpu.l2cache.demand_mshr_miss_rate 0.204338 # mshr miss rate for demand accesses
514 system.cpu.l2cache.overall_mshr_miss_rate 0.204338 # mshr miss rate for overall accesses
515 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31084.662053 # average ReadReq mshr miss latency
516 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31230.733638 # average ReadExReq mshr miss latency
517 system.cpu.l2cache.demand_avg_mshr_miss_latency 31178.171007 # average overall mshr miss latency
518 system.cpu.l2cache.overall_avg_mshr_miss_latency 31178.171007 # average overall mshr miss latency
519 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
520 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
521 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
522 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
524 ---------- End Simulation Statistics ----------
projects / gem5.git / blob