2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.181677 # Number of seconds simulated
4 sim_ticks 181676511500 # Number of ticks simulated
5 sim_freq 1000000000000 # Frequency of simulated ticks
6 host_inst_rate 82416 # Simulator instruction rate (inst/s)
7 host_tick_rate 24857445 # Simulator tick rate (ticks/s)
8 host_mem_usage 257796 # Number of bytes of host memory used
9 host_seconds 7308.74 # Real time elapsed on the host
10 sim_insts 602359820 # Number of instructions simulated
11 system.cpu.dtb.inst_hits 0 # ITB inst hits
12 system.cpu.dtb.inst_misses 0 # ITB inst misses
13 system.cpu.dtb.read_hits 0 # DTB read hits
14 system.cpu.dtb.read_misses 0 # DTB read misses
15 system.cpu.dtb.write_hits 0 # DTB write hits
16 system.cpu.dtb.write_misses 0 # DTB write misses
17 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
18 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
19 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
20 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
21 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
22 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
23 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
24 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
25 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
26 system.cpu.dtb.read_accesses 0 # DTB read accesses
27 system.cpu.dtb.write_accesses 0 # DTB write accesses
28 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
29 system.cpu.dtb.hits 0 # DTB hits
30 system.cpu.dtb.misses 0 # DTB misses
31 system.cpu.dtb.accesses 0 # DTB accesses
32 system.cpu.itb.inst_hits 0 # ITB inst hits
33 system.cpu.itb.inst_misses 0 # ITB inst misses
34 system.cpu.itb.read_hits 0 # DTB read hits
35 system.cpu.itb.read_misses 0 # DTB read misses
36 system.cpu.itb.write_hits 0 # DTB write hits
37 system.cpu.itb.write_misses 0 # DTB write misses
38 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
39 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
40 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
41 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
42 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
43 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
44 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
45 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
46 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
47 system.cpu.itb.read_accesses 0 # DTB read accesses
48 system.cpu.itb.write_accesses 0 # DTB write accesses
49 system.cpu.itb.inst_accesses 0 # ITB inst accesses
50 system.cpu.itb.hits 0 # DTB hits
51 system.cpu.itb.misses 0 # DTB misses
52 system.cpu.itb.accesses 0 # DTB accesses
53 system.cpu.workload.num_syscalls 48 # Number of system calls
54 system.cpu.numCycles 363353024 # number of cpu cycles simulated
55 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
56 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
57 system.cpu.BPredUnit.lookups 93642406 # Number of BP lookups
58 system.cpu.BPredUnit.condPredicted 86055517 # Number of conditional branches predicted
59 system.cpu.BPredUnit.condIncorrect 3937297 # Number of conditional branches incorrect
60 system.cpu.BPredUnit.BTBLookups 88612742 # Number of BTB lookups
61 system.cpu.BPredUnit.BTBHits 82226729 # Number of BTB hits
62 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
63 system.cpu.BPredUnit.usedRAS 1811116 # Number of times the RAS was used to get a target.
64 system.cpu.BPredUnit.RASInCorrect 1799 # Number of incorrect RAS predictions.
65 system.cpu.fetch.icacheStallCycles 80077128 # Number of cycles fetch is stalled on an Icache miss
66 system.cpu.fetch.Insts 720176236 # Number of instructions fetch has processed
67 system.cpu.fetch.Branches 93642406 # Number of branches that fetch encountered
68 system.cpu.fetch.predictedBranches 84037845 # Number of branches that fetch has predicted taken
69 system.cpu.fetch.Cycles 163199656 # Number of cycles fetch has run and was not squashing or blocked
70 system.cpu.fetch.SquashCycles 20933611 # Number of cycles fetch has spent squashing
71 system.cpu.fetch.BlockedCycles 102893232 # Number of cycles fetch has spent blocked
72 system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
73 system.cpu.fetch.PendingTrapStallCycles 623 # Number of stall cycles due to pending traps
74 system.cpu.fetch.CacheLines 77424762 # Number of cache lines fetched
75 system.cpu.fetch.IcacheSquashes 1579270 # Number of outstanding Icache misses that were squashed
76 system.cpu.fetch.rateDist::samples 362477887 # Number of instructions fetched each cycle (Total)
77 system.cpu.fetch.rateDist::mean 2.126441 # Number of instructions fetched each cycle (Total)
78 system.cpu.fetch.rateDist::stdev 2.976296 # Number of instructions fetched each cycle (Total)
79 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
80 system.cpu.fetch.rateDist::0 199278398 54.98% 54.98% # Number of instructions fetched each cycle (Total)
81 system.cpu.fetch.rateDist::1 25830413 7.13% 62.10% # Number of instructions fetched each cycle (Total)
82 system.cpu.fetch.rateDist::2 19932307 5.50% 67.60% # Number of instructions fetched each cycle (Total)
83 system.cpu.fetch.rateDist::3 25118126 6.93% 74.53% # Number of instructions fetched each cycle (Total)
84 system.cpu.fetch.rateDist::4 12539166 3.46% 77.99% # Number of instructions fetched each cycle (Total)
85 system.cpu.fetch.rateDist::5 13666852 3.77% 81.76% # Number of instructions fetched each cycle (Total)
86 system.cpu.fetch.rateDist::6 4829528 1.33% 83.09% # Number of instructions fetched each cycle (Total)
87 system.cpu.fetch.rateDist::7 7994396 2.21% 85.30% # Number of instructions fetched each cycle (Total)
88 system.cpu.fetch.rateDist::8 53288701 14.70% 100.00% # Number of instructions fetched each cycle (Total)
89 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
90 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
91 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
92 system.cpu.fetch.rateDist::total 362477887 # Number of instructions fetched each cycle (Total)
93 system.cpu.fetch.branchRate 0.257717 # Number of branch fetches per cycle
94 system.cpu.fetch.rate 1.982029 # Number of inst fetches per cycle
95 system.cpu.decode.IdleCycles 102756406 # Number of cycles decode is idle
96 system.cpu.decode.BlockedCycles 83077250 # Number of cycles decode is blocked
97 system.cpu.decode.RunCycles 141158544 # Number of cycles decode is running
98 system.cpu.decode.UnblockCycles 19181042 # Number of cycles decode is unblocking
99 system.cpu.decode.SquashCycles 16304645 # Number of cycles decode is squashing
100 system.cpu.decode.BranchResolved 6938686 # Number of times decode resolved a branch
101 system.cpu.decode.BranchMispred 2613 # Number of times decode detected a branch misprediction
102 system.cpu.decode.DecodedInsts 758024516 # Number of instructions handled by decode
103 system.cpu.decode.SquashedInsts 7262 # Number of squashed instructions handled by decode
104 system.cpu.rename.SquashCycles 16304645 # Number of cycles rename is squashing
105 system.cpu.rename.IdleCycles 116075491 # Number of cycles rename is idle
106 system.cpu.rename.BlockCycles 10185612 # Number of cycles rename is blocking
107 system.cpu.rename.serializeStallCycles 109358 # count of cycles rename stalled for serializing inst
108 system.cpu.rename.RunCycles 146924183 # Number of cycles rename is running
109 system.cpu.rename.UnblockCycles 72878598 # Number of cycles rename is unblocking
110 system.cpu.rename.RenamedInsts 743558817 # Number of instructions processed by rename
111 system.cpu.rename.ROBFullEvents 188 # Number of times rename has blocked due to ROB full
112 system.cpu.rename.IQFullEvents 58921601 # Number of times rename has blocked due to IQ full
113 system.cpu.rename.LSQFullEvents 10117687 # Number of times rename has blocked due to LSQ full
114 system.cpu.rename.FullRegisterEvents 591 # Number of times there has been no free registers
115 system.cpu.rename.RenamedOperands 767454765 # Number of destination operands rename has renamed
116 system.cpu.rename.RenameLookups 3458233737 # Number of register rename lookups that rename has made
117 system.cpu.rename.int_rename_lookups 3458233609 # Number of integer rename lookups
118 system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
119 system.cpu.rename.CommittedMaps 627417418 # Number of HB maps that are committed
120 system.cpu.rename.UndoneMaps 140037342 # Number of HB maps that are undone due to squashing
121 system.cpu.rename.serializingInsts 6399 # count of serializing insts renamed
122 system.cpu.rename.tempSerializingInsts 6398 # count of temporary serializing insts renamed
123 system.cpu.rename.skidInsts 130096693 # count of insts added to the skid buffer
124 system.cpu.memDep0.insertedLoads 183828757 # Number of loads inserted to the mem dependence unit.
125 system.cpu.memDep0.insertedStores 85345746 # Number of stores inserted to the mem dependence unit.
126 system.cpu.memDep0.conflictingLoads 25811031 # Number of conflicting loads.
127 system.cpu.memDep0.conflictingStores 37497456 # Number of conflicting stores.
128 system.cpu.iq.iqInstsAdded 715547655 # Number of instructions added to the IQ (excludes non-spec)
129 system.cpu.iq.iqNonSpecInstsAdded 7366 # Number of non-speculative instructions added to the IQ
130 system.cpu.iq.iqInstsIssued 667339389 # Number of instructions issued
131 system.cpu.iq.iqSquashedInstsIssued 840250 # Number of squashed instructions issued
132 system.cpu.iq.iqSquashedInstsExamined 112563133 # Number of squashed instructions iterated over during squash; mainly for profiling
133 system.cpu.iq.iqSquashedOperandsExamined 285197370 # Number of squashed operands that are examined and possibly removed from graph
134 system.cpu.iq.iqSquashedNonSpecRemoved 1065 # Number of squashed non-spec instructions that were removed
135 system.cpu.iq.issued_per_cycle::samples 362477887 # Number of insts issued each cycle
136 system.cpu.iq.issued_per_cycle::mean 1.841049 # Number of insts issued each cycle
137 system.cpu.iq.issued_per_cycle::stdev 1.675765 # Number of insts issued each cycle
138 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
139 system.cpu.iq.issued_per_cycle::0 89414922 24.67% 24.67% # Number of insts issued each cycle
140 system.cpu.iq.issued_per_cycle::1 90190265 24.88% 49.55% # Number of insts issued each cycle
141 system.cpu.iq.issued_per_cycle::2 79396670 21.90% 71.45% # Number of insts issued each cycle
142 system.cpu.iq.issued_per_cycle::3 45359007 12.51% 83.97% # Number of insts issued each cycle
143 system.cpu.iq.issued_per_cycle::4 28036434 7.73% 91.70% # Number of insts issued each cycle
144 system.cpu.iq.issued_per_cycle::5 16328709 4.50% 96.21% # Number of insts issued each cycle
145 system.cpu.iq.issued_per_cycle::6 8232346 2.27% 98.48% # Number of insts issued each cycle
146 system.cpu.iq.issued_per_cycle::7 5060866 1.40% 99.87% # Number of insts issued each cycle
147 system.cpu.iq.issued_per_cycle::8 458668 0.13% 100.00% # Number of insts issued each cycle
148 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
149 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
150 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
151 system.cpu.iq.issued_per_cycle::total 362477887 # Number of insts issued each cycle
152 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
153 system.cpu.iq.fu_full::IntAlu 175813 5.16% 5.16% # attempts to use FU when none available
154 system.cpu.iq.fu_full::IntMult 0 0.00% 5.16% # attempts to use FU when none available
155 system.cpu.iq.fu_full::IntDiv 0 0.00% 5.16% # attempts to use FU when none available
156 system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.16% # attempts to use FU when none available
157 system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.16% # attempts to use FU when none available
158 system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.16% # attempts to use FU when none available
159 system.cpu.iq.fu_full::FloatMult 0 0.00% 5.16% # attempts to use FU when none available
160 system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.16% # attempts to use FU when none available
161 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.16% # attempts to use FU when none available
162 system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.16% # attempts to use FU when none available
163 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.16% # attempts to use FU when none available
164 system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.16% # attempts to use FU when none available
165 system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.16% # attempts to use FU when none available
166 system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.16% # attempts to use FU when none available
167 system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.16% # attempts to use FU when none available
168 system.cpu.iq.fu_full::SimdMult 0 0.00% 5.16% # attempts to use FU when none available
169 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.16% # attempts to use FU when none available
170 system.cpu.iq.fu_full::SimdShift 0 0.00% 5.16% # attempts to use FU when none available
171 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.16% # attempts to use FU when none available
172 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.16% # attempts to use FU when none available
173 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.16% # attempts to use FU when none available
174 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.16% # attempts to use FU when none available
175 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.16% # attempts to use FU when none available
176 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.16% # attempts to use FU when none available
177 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.16% # attempts to use FU when none available
178 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.16% # attempts to use FU when none available
179 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.16% # attempts to use FU when none available
180 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.16% # attempts to use FU when none available
181 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.16% # attempts to use FU when none available
182 system.cpu.iq.fu_full::MemRead 2586346 75.94% 81.11% # attempts to use FU when none available
183 system.cpu.iq.fu_full::MemWrite 643459 18.89% 100.00% # attempts to use FU when none available
184 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
185 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
186 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
187 system.cpu.iq.FU_type_0::IntAlu 414934483 62.18% 62.18% # Type of FU issued
188 system.cpu.iq.FU_type_0::IntMult 6549 0.00% 62.18% # Type of FU issued
189 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.18% # Type of FU issued
190 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.18% # Type of FU issued
191 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.18% # Type of FU issued
192 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.18% # Type of FU issued
193 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.18% # Type of FU issued
194 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.18% # Type of FU issued
195 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.18% # Type of FU issued
196 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.18% # Type of FU issued
197 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.18% # Type of FU issued
198 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.18% # Type of FU issued
199 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.18% # Type of FU issued
200 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.18% # Type of FU issued
201 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.18% # Type of FU issued
202 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.18% # Type of FU issued
203 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.18% # Type of FU issued
204 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.18% # Type of FU issued
205 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.18% # Type of FU issued
206 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.18% # Type of FU issued
207 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.18% # Type of FU issued
208 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.18% # Type of FU issued
209 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.18% # Type of FU issued
210 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.18% # Type of FU issued
211 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.18% # Type of FU issued
212 system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.18% # Type of FU issued
213 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.18% # Type of FU issued
214 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.18% # Type of FU issued
215 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.18% # Type of FU issued
216 system.cpu.iq.FU_type_0::MemRead 174108289 26.09% 88.27% # Type of FU issued
217 system.cpu.iq.FU_type_0::MemWrite 78290065 11.73% 100.00% # Type of FU issued
218 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
219 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
220 system.cpu.iq.FU_type_0::total 667339389 # Type of FU issued
221 system.cpu.iq.rate 1.836614 # Inst issue rate
222 system.cpu.iq.fu_busy_cnt 3405618 # FU busy when requested
223 system.cpu.iq.fu_busy_rate 0.005103 # FU busy rate (busy events/executed inst)
224 system.cpu.iq.int_inst_queue_reads 1701402497 # Number of integer instruction queue reads
225 system.cpu.iq.int_inst_queue_writes 828782976 # Number of integer instruction queue writes
226 system.cpu.iq.int_inst_queue_wakeup_accesses 653330026 # Number of integer instruction queue wakeup accesses
227 system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
228 system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
229 system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
230 system.cpu.iq.int_alu_accesses 670744987 # Number of integer alu accesses
231 system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
232 system.cpu.iew.lsq.thread0.forwLoads 28288943 # Number of loads that had data forwarded from stores
233 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
234 system.cpu.iew.lsq.thread0.squashedLoads 34876158 # Number of loads squashed
235 system.cpu.iew.lsq.thread0.ignoredResponses 159827 # Number of memory responses ignored because the instruction is squashed
236 system.cpu.iew.lsq.thread0.memOrderViolation 665311 # Number of memory ordering violations
237 system.cpu.iew.lsq.thread0.squashedStores 15124729 # Number of stores squashed
238 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
239 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
240 system.cpu.iew.lsq.thread0.rescheduledLoads 15440 # Number of loads that were rescheduled
241 system.cpu.iew.lsq.thread0.cacheBlocked 12578 # Number of times an access to memory failed due to the cache being blocked
242 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
243 system.cpu.iew.iewSquashCycles 16304645 # Number of cycles IEW is squashing
244 system.cpu.iew.iewBlockCycles 784511 # Number of cycles IEW is blocking
245 system.cpu.iew.iewUnblockCycles 50454 # Number of cycles IEW is unblocking
246 system.cpu.iew.iewDispatchedInsts 715624477 # Number of instructions dispatched to IQ
247 system.cpu.iew.iewDispSquashedInsts 2065189 # Number of squashed instructions skipped by dispatch
248 system.cpu.iew.iewDispLoadInsts 183828757 # Number of dispatched load instructions
249 system.cpu.iew.iewDispStoreInsts 85345746 # Number of dispatched store instructions
250 system.cpu.iew.iewDispNonSpecInsts 6034 # Number of dispatched non-speculative instructions
251 system.cpu.iew.iewIQFullEvents 13250 # Number of times the IQ has become full, causing a stall
252 system.cpu.iew.iewLSQFullEvents 5066 # Number of times the LSQ has become full, causing a stall
253 system.cpu.iew.memOrderViolationEvents 665311 # Number of memory order violations
254 system.cpu.iew.predictedTakenIncorrect 4094363 # Number of branches that were predicted taken incorrectly
255 system.cpu.iew.predictedNotTakenIncorrect 486296 # Number of branches that were predicted not taken incorrectly
256 system.cpu.iew.branchMispredicts 4580659 # Number of branch mispredicts detected at execute
257 system.cpu.iew.iewExecutedInsts 659689382 # Number of executed instructions
258 system.cpu.iew.iewExecLoadInsts 170637671 # Number of load instructions executed
259 system.cpu.iew.iewExecSquashedInsts 7650007 # Number of squashed instructions skipped in execute
260 system.cpu.iew.exec_swp 0 # number of swp insts executed
261 system.cpu.iew.exec_nop 69456 # number of nop insts executed
262 system.cpu.iew.exec_refs 247330517 # number of memory reference insts executed
263 system.cpu.iew.exec_branches 76920251 # Number of branches executed
264 system.cpu.iew.exec_stores 76692846 # Number of stores executed
265 system.cpu.iew.exec_rate 1.815560 # Inst execution rate
266 system.cpu.iew.wb_sent 655349780 # cumulative count of insts sent to commit
267 system.cpu.iew.wb_count 653330042 # cumulative count of insts written-back
268 system.cpu.iew.wb_producers 425170180 # num instructions producing a value
269 system.cpu.iew.wb_consumers 661395893 # num instructions consuming a value
270 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
271 system.cpu.iew.wb_rate 1.798059 # insts written-back per cycle
272 system.cpu.iew.wb_fanout 0.642838 # average fanout of values written-back
273 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
274 system.cpu.commit.commitCommittedInsts 602359871 # The number of committed instructions
275 system.cpu.commit.commitSquashedInsts 113270616 # The number of squashed insts skipped by commit
276 system.cpu.commit.commitNonSpecStalls 6301 # The number of times commit has been forced to stall to communicate backwards
277 system.cpu.commit.branchMispredicts 3996549 # The number of times a branch was mispredicted
278 system.cpu.commit.committed_per_cycle::samples 346173243 # Number of insts commited each cycle
279 system.cpu.commit.committed_per_cycle::mean 1.740053 # Number of insts commited each cycle
280 system.cpu.commit.committed_per_cycle::stdev 2.116155 # Number of insts commited each cycle
281 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
282 system.cpu.commit.committed_per_cycle::0 112054418 32.37% 32.37% # Number of insts commited each cycle
283 system.cpu.commit.committed_per_cycle::1 109168598 31.54% 63.91% # Number of insts commited each cycle
284 system.cpu.commit.committed_per_cycle::2 49782434 14.38% 78.29% # Number of insts commited each cycle
285 system.cpu.commit.committed_per_cycle::3 10491888 3.03% 81.32% # Number of insts commited each cycle
286 system.cpu.commit.committed_per_cycle::4 23443534 6.77% 88.09% # Number of insts commited each cycle
287 system.cpu.commit.committed_per_cycle::5 14637280 4.23% 92.32% # Number of insts commited each cycle
288 system.cpu.commit.committed_per_cycle::6 8029663 2.32% 94.64% # Number of insts commited each cycle
289 system.cpu.commit.committed_per_cycle::7 1511197 0.44% 95.07% # Number of insts commited each cycle
290 system.cpu.commit.committed_per_cycle::8 17054231 4.93% 100.00% # Number of insts commited each cycle
291 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
292 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
293 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
294 system.cpu.commit.committed_per_cycle::total 346173243 # Number of insts commited each cycle
295 system.cpu.commit.count 602359871 # Number of instructions committed
296 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
297 system.cpu.commit.refs 219173615 # Number of memory references committed
298 system.cpu.commit.loads 148952598 # Number of loads committed
299 system.cpu.commit.membars 1328 # Number of memory barriers committed
300 system.cpu.commit.branches 70828605 # Number of branches committed
301 system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
302 system.cpu.commit.int_insts 533522655 # Number of committed integer instructions.
303 system.cpu.commit.function_calls 997573 # Number of function calls committed.
304 system.cpu.commit.bw_lim_events 17054231 # number cycles where commit BW limit reached
305 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
306 system.cpu.rob.rob_reads 1044748887 # The number of ROB reads
307 system.cpu.rob.rob_writes 1447602374 # The number of ROB writes
308 system.cpu.timesIdled 36933 # Number of times that the entire CPU went into an idle state and unscheduled itself
309 system.cpu.idleCycles 875137 # Total number of cycles that the CPU has spent unscheduled due to idling
310 system.cpu.committedInsts 602359820 # Number of Instructions Simulated
311 system.cpu.committedInsts_total 602359820 # Number of Instructions Simulated
312 system.cpu.cpi 0.603216 # CPI: Cycles Per Instruction
313 system.cpu.cpi_total 0.603216 # CPI: Total CPI of All Threads
314 system.cpu.ipc 1.657781 # IPC: Instructions Per Cycle
315 system.cpu.ipc_total 1.657781 # IPC: Total IPC of All Threads
316 system.cpu.int_regfile_reads 3292742614 # number of integer regfile reads
317 system.cpu.int_regfile_writes 679039343 # number of integer regfile writes
318 system.cpu.fp_regfile_reads 16 # number of floating regfile reads
319 system.cpu.misc_regfile_reads 961073357 # number of misc regfile reads
320 system.cpu.misc_regfile_writes 2664 # number of misc regfile writes
321 system.cpu.icache.replacements 52 # number of replacements
322 system.cpu.icache.tagsinuse 658.859257 # Cycle average of tags in use
323 system.cpu.icache.total_refs 77423742 # Total number of references to valid blocks.
324 system.cpu.icache.sampled_refs 777 # Sample count of references to valid blocks.
325 system.cpu.icache.avg_refs 99644.455598 # Average number of references to valid blocks.
326 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
327 system.cpu.icache.occ_blocks::0 658.859257 # Average occupied blocks per context
328 system.cpu.icache.occ_percent::0 0.321709 # Average percentage of cache occupancy
329 system.cpu.icache.ReadReq_hits 77423742 # number of ReadReq hits
330 system.cpu.icache.demand_hits 77423742 # number of demand (read+write) hits
331 system.cpu.icache.overall_hits 77423742 # number of overall hits
332 system.cpu.icache.ReadReq_misses 1020 # number of ReadReq misses
333 system.cpu.icache.demand_misses 1020 # number of demand (read+write) misses
334 system.cpu.icache.overall_misses 1020 # number of overall misses
335 system.cpu.icache.ReadReq_miss_latency 35800500 # number of ReadReq miss cycles
336 system.cpu.icache.demand_miss_latency 35800500 # number of demand (read+write) miss cycles
337 system.cpu.icache.overall_miss_latency 35800500 # number of overall miss cycles
338 system.cpu.icache.ReadReq_accesses 77424762 # number of ReadReq accesses(hits+misses)
339 system.cpu.icache.demand_accesses 77424762 # number of demand (read+write) accesses
340 system.cpu.icache.overall_accesses 77424762 # number of overall (read+write) accesses
341 system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
342 system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses
343 system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses
344 system.cpu.icache.ReadReq_avg_miss_latency 35098.529412 # average ReadReq miss latency
345 system.cpu.icache.demand_avg_miss_latency 35098.529412 # average overall miss latency
346 system.cpu.icache.overall_avg_miss_latency 35098.529412 # average overall miss latency
347 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
348 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
349 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
350 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
351 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
352 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
353 system.cpu.icache.fast_writes 0 # number of fast writes performed
354 system.cpu.icache.cache_copies 0 # number of cache copies performed
355 system.cpu.icache.writebacks 0 # number of writebacks
356 system.cpu.icache.ReadReq_mshr_hits 243 # number of ReadReq MSHR hits
357 system.cpu.icache.demand_mshr_hits 243 # number of demand (read+write) MSHR hits
358 system.cpu.icache.overall_mshr_hits 243 # number of overall MSHR hits
359 system.cpu.icache.ReadReq_mshr_misses 777 # number of ReadReq MSHR misses
360 system.cpu.icache.demand_mshr_misses 777 # number of demand (read+write) MSHR misses
361 system.cpu.icache.overall_mshr_misses 777 # number of overall MSHR misses
362 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
363 system.cpu.icache.ReadReq_mshr_miss_latency 26636000 # number of ReadReq MSHR miss cycles
364 system.cpu.icache.demand_mshr_miss_latency 26636000 # number of demand (read+write) MSHR miss cycles
365 system.cpu.icache.overall_mshr_miss_latency 26636000 # number of overall MSHR miss cycles
366 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
367 system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
368 system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses
369 system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses
370 system.cpu.icache.ReadReq_avg_mshr_miss_latency 34280.566281 # average ReadReq mshr miss latency
371 system.cpu.icache.demand_avg_mshr_miss_latency 34280.566281 # average overall mshr miss latency
372 system.cpu.icache.overall_avg_mshr_miss_latency 34280.566281 # average overall mshr miss latency
373 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
374 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
375 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
376 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
377 system.cpu.dcache.replacements 440951 # number of replacements
378 system.cpu.dcache.tagsinuse 4094.785016 # Cycle average of tags in use
379 system.cpu.dcache.total_refs 208890975 # Total number of references to valid blocks.
380 system.cpu.dcache.sampled_refs 445047 # Sample count of references to valid blocks.
381 system.cpu.dcache.avg_refs 469.368348 # Average number of references to valid blocks.
382 system.cpu.dcache.warmup_cycle 87843000 # Cycle when the warmup percentage was hit.
383 system.cpu.dcache.occ_blocks::0 4094.785016 # Average occupied blocks per context
384 system.cpu.dcache.occ_percent::0 0.999703 # Average percentage of cache occupancy
385 system.cpu.dcache.ReadReq_hits 140815101 # number of ReadReq hits
386 system.cpu.dcache.WriteReq_hits 68073201 # number of WriteReq hits
387 system.cpu.dcache.LoadLockedReq_hits 1342 # number of LoadLockedReq hits
388 system.cpu.dcache.StoreCondReq_hits 1331 # number of StoreCondReq hits
389 system.cpu.dcache.demand_hits 208888302 # number of demand (read+write) hits
390 system.cpu.dcache.overall_hits 208888302 # number of overall hits
391 system.cpu.dcache.ReadReq_misses 248858 # number of ReadReq misses
392 system.cpu.dcache.WriteReq_misses 1344330 # number of WriteReq misses
393 system.cpu.dcache.LoadLockedReq_misses 9 # number of LoadLockedReq misses
394 system.cpu.dcache.demand_misses 1593188 # number of demand (read+write) misses
395 system.cpu.dcache.overall_misses 1593188 # number of overall misses
396 system.cpu.dcache.ReadReq_miss_latency 3280375500 # number of ReadReq miss cycles
397 system.cpu.dcache.WriteReq_miss_latency 26109782527 # number of WriteReq miss cycles
398 system.cpu.dcache.LoadLockedReq_miss_latency 194000 # number of LoadLockedReq miss cycles
399 system.cpu.dcache.demand_miss_latency 29390158027 # number of demand (read+write) miss cycles
400 system.cpu.dcache.overall_miss_latency 29390158027 # number of overall miss cycles
401 system.cpu.dcache.ReadReq_accesses 141063959 # number of ReadReq accesses(hits+misses)
402 system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
403 system.cpu.dcache.LoadLockedReq_accesses 1351 # number of LoadLockedReq accesses(hits+misses)
404 system.cpu.dcache.StoreCondReq_accesses 1331 # number of StoreCondReq accesses(hits+misses)
405 system.cpu.dcache.demand_accesses 210481490 # number of demand (read+write) accesses
406 system.cpu.dcache.overall_accesses 210481490 # number of overall (read+write) accesses
407 system.cpu.dcache.ReadReq_miss_rate 0.001764 # miss rate for ReadReq accesses
408 system.cpu.dcache.WriteReq_miss_rate 0.019366 # miss rate for WriteReq accesses
409 system.cpu.dcache.LoadLockedReq_miss_rate 0.006662 # miss rate for LoadLockedReq accesses
410 system.cpu.dcache.demand_miss_rate 0.007569 # miss rate for demand accesses
411 system.cpu.dcache.overall_miss_rate 0.007569 # miss rate for overall accesses
412 system.cpu.dcache.ReadReq_avg_miss_latency 13181.716079 # average ReadReq miss latency
413 system.cpu.dcache.WriteReq_avg_miss_latency 19422.152691 # average WriteReq miss latency
414 system.cpu.dcache.LoadLockedReq_avg_miss_latency 21555.555556 # average LoadLockedReq miss latency
415 system.cpu.dcache.demand_avg_miss_latency 18447.388524 # average overall miss latency
416 system.cpu.dcache.overall_avg_miss_latency 18447.388524 # average overall miss latency
417 system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked
418 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
419 system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked
420 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
421 system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 # average number of cycles each access was blocked
422 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
423 system.cpu.dcache.fast_writes 0 # number of fast writes performed
424 system.cpu.dcache.cache_copies 0 # number of cache copies performed
425 system.cpu.dcache.writebacks 395037 # number of writebacks
426 system.cpu.dcache.ReadReq_mshr_hits 51168 # number of ReadReq MSHR hits
427 system.cpu.dcache.WriteReq_mshr_hits 1096973 # number of WriteReq MSHR hits
428 system.cpu.dcache.LoadLockedReq_mshr_hits 9 # number of LoadLockedReq MSHR hits
429 system.cpu.dcache.demand_mshr_hits 1148141 # number of demand (read+write) MSHR hits
430 system.cpu.dcache.overall_mshr_hits 1148141 # number of overall MSHR hits
431 system.cpu.dcache.ReadReq_mshr_misses 197690 # number of ReadReq MSHR misses
432 system.cpu.dcache.WriteReq_mshr_misses 247357 # number of WriteReq MSHR misses
433 system.cpu.dcache.demand_mshr_misses 445047 # number of demand (read+write) MSHR misses
434 system.cpu.dcache.overall_mshr_misses 445047 # number of overall MSHR misses
435 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
436 system.cpu.dcache.ReadReq_mshr_miss_latency 1624799500 # number of ReadReq MSHR miss cycles
437 system.cpu.dcache.WriteReq_mshr_miss_latency 2561111027 # number of WriteReq MSHR miss cycles
438 system.cpu.dcache.demand_mshr_miss_latency 4185910527 # number of demand (read+write) MSHR miss cycles
439 system.cpu.dcache.overall_mshr_miss_latency 4185910527 # number of overall MSHR miss cycles
440 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
441 system.cpu.dcache.ReadReq_mshr_miss_rate 0.001401 # mshr miss rate for ReadReq accesses
442 system.cpu.dcache.WriteReq_mshr_miss_rate 0.003563 # mshr miss rate for WriteReq accesses
443 system.cpu.dcache.demand_mshr_miss_rate 0.002114 # mshr miss rate for demand accesses
444 system.cpu.dcache.overall_mshr_miss_rate 0.002114 # mshr miss rate for overall accesses
445 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8218.926096 # average ReadReq mshr miss latency
446 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10353.905598 # average WriteReq mshr miss latency
447 system.cpu.dcache.demand_avg_mshr_miss_latency 9405.547115 # average overall mshr miss latency
448 system.cpu.dcache.overall_avg_mshr_miss_latency 9405.547115 # average overall mshr miss latency
449 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
450 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
451 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
452 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
453 system.cpu.l2cache.replacements 72983 # number of replacements
454 system.cpu.l2cache.tagsinuse 17823.829612 # Cycle average of tags in use
455 system.cpu.l2cache.total_refs 421659 # Total number of references to valid blocks.
456 system.cpu.l2cache.sampled_refs 88508 # Sample count of references to valid blocks.
457 system.cpu.l2cache.avg_refs 4.764078 # Average number of references to valid blocks.
458 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
459 system.cpu.l2cache.occ_blocks::0 1903.131187 # Average occupied blocks per context
460 system.cpu.l2cache.occ_blocks::1 15920.698425 # Average occupied blocks per context
461 system.cpu.l2cache.occ_percent::0 0.058079 # Average percentage of cache occupancy
462 system.cpu.l2cache.occ_percent::1 0.485861 # Average percentage of cache occupancy
463 system.cpu.l2cache.ReadReq_hits 165659 # number of ReadReq hits
464 system.cpu.l2cache.Writeback_hits 395037 # number of Writeback hits
465 system.cpu.l2cache.ReadExReq_hits 188979 # number of ReadExReq hits
466 system.cpu.l2cache.demand_hits 354638 # number of demand (read+write) hits
467 system.cpu.l2cache.overall_hits 354638 # number of overall hits
468 system.cpu.l2cache.ReadReq_misses 32805 # number of ReadReq misses
469 system.cpu.l2cache.ReadExReq_misses 58381 # number of ReadExReq misses
470 system.cpu.l2cache.demand_misses 91186 # number of demand (read+write) misses
471 system.cpu.l2cache.overall_misses 91186 # number of overall misses
472 system.cpu.l2cache.ReadReq_miss_latency 1126836000 # number of ReadReq miss cycles
473 system.cpu.l2cache.ReadExReq_miss_latency 2004580000 # number of ReadExReq miss cycles
474 system.cpu.l2cache.demand_miss_latency 3131416000 # number of demand (read+write) miss cycles
475 system.cpu.l2cache.overall_miss_latency 3131416000 # number of overall miss cycles
476 system.cpu.l2cache.ReadReq_accesses 198464 # number of ReadReq accesses(hits+misses)
477 system.cpu.l2cache.Writeback_accesses 395037 # number of Writeback accesses(hits+misses)
478 system.cpu.l2cache.ReadExReq_accesses 247360 # number of ReadExReq accesses(hits+misses)
479 system.cpu.l2cache.demand_accesses 445824 # number of demand (read+write) accesses
480 system.cpu.l2cache.overall_accesses 445824 # number of overall (read+write) accesses
481 system.cpu.l2cache.ReadReq_miss_rate 0.165294 # miss rate for ReadReq accesses
482 system.cpu.l2cache.ReadExReq_miss_rate 0.236016 # miss rate for ReadExReq accesses
483 system.cpu.l2cache.demand_miss_rate 0.204534 # miss rate for demand accesses
484 system.cpu.l2cache.overall_miss_rate 0.204534 # miss rate for overall accesses
485 system.cpu.l2cache.ReadReq_avg_miss_latency 34349.519890 # average ReadReq miss latency
486 system.cpu.l2cache.ReadExReq_avg_miss_latency 34336.171015 # average ReadExReq miss latency
487 system.cpu.l2cache.demand_avg_miss_latency 34340.973395 # average overall miss latency
488 system.cpu.l2cache.overall_avg_miss_latency 34340.973395 # average overall miss latency
489 system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked
490 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
491 system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked
492 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
493 system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 # average number of cycles each access was blocked
494 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
495 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
496 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
497 system.cpu.l2cache.writebacks 58139 # number of writebacks
498 system.cpu.l2cache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits
499 system.cpu.l2cache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits
500 system.cpu.l2cache.overall_mshr_hits 9 # number of overall MSHR hits
501 system.cpu.l2cache.ReadReq_mshr_misses 32796 # number of ReadReq MSHR misses
502 system.cpu.l2cache.ReadExReq_mshr_misses 58381 # number of ReadExReq MSHR misses
503 system.cpu.l2cache.demand_mshr_misses 91177 # number of demand (read+write) MSHR misses
504 system.cpu.l2cache.overall_mshr_misses 91177 # number of overall MSHR misses
505 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
506 system.cpu.l2cache.ReadReq_mshr_miss_latency 1020208500 # number of ReadReq MSHR miss cycles
507 system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822855000 # number of ReadExReq MSHR miss cycles
508 system.cpu.l2cache.demand_mshr_miss_latency 2843063500 # number of demand (read+write) MSHR miss cycles
509 system.cpu.l2cache.overall_mshr_miss_latency 2843063500 # number of overall MSHR miss cycles
510 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
511 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165249 # mshr miss rate for ReadReq accesses
512 system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236016 # mshr miss rate for ReadExReq accesses
513 system.cpu.l2cache.demand_mshr_miss_rate 0.204513 # mshr miss rate for demand accesses
514 system.cpu.l2cache.overall_mshr_miss_rate 0.204513 # mshr miss rate for overall accesses
515 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31107.711306 # average ReadReq mshr miss latency
516 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31223.428855 # average ReadExReq mshr miss latency
517 system.cpu.l2cache.demand_avg_mshr_miss_latency 31181.805719 # average overall mshr miss latency
518 system.cpu.l2cache.overall_avg_mshr_miss_latency 31181.805719 # average overall mshr miss latency
519 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
520 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
521 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
522 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
524 ---------- End Simulation Statistics ----------
projects / gem5.git / blob