2 ---------- Begin Simulation Statistics ----------
3 global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
4 global.BPredUnit.BTBHits 181900655 # Number of BTB hits
5 global.BPredUnit.BTBLookups 205112403 # Number of BTB lookups
6 global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
7 global.BPredUnit.condIncorrect 84376140 # Number of conditional branches incorrect
8 global.BPredUnit.condPredicted 253553370 # Number of conditional branches predicted
9 global.BPredUnit.lookups 253553370 # Number of BP lookups
10 global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
11 host_inst_rate 148554 # Simulator instruction rate (inst/s)
12 host_mem_usage 214964 # Number of bytes of host memory used
13 host_seconds 9461.99 # Real time elapsed on the host
14 host_tick_rate 116526717 # Simulator tick rate (ticks/s)
15 memdepunit.memDep.conflictingLoads 445262703 # Number of conflicting loads.
16 memdepunit.memDep.conflictingStores 137431528 # Number of conflicting stores.
17 memdepunit.memDep.insertedLoads 741823023 # Number of loads inserted to the mem dependence unit.
18 memdepunit.memDep.insertedStores 303434035 # Number of stores inserted to the mem dependence unit.
19 sim_freq 1000000000000 # Frequency of simulated ticks
20 sim_insts 1405618364 # Number of instructions simulated
21 sim_seconds 1.102575 # Number of seconds simulated
22 sim_ticks 1102574586000 # Number of ticks simulated
23 system.cpu.commit.COM:branches 86248929 # Number of branches committed
24 system.cpu.commit.COM:bw_lim_events 8144949 # number cycles where commit BW limit reached
25 system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
26 system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
27 system.cpu.commit.COM:committed_per_cycle.samples 1965667914
28 system.cpu.commit.COM:committed_per_cycle.min_value 0
38 system.cpu.commit.COM:committed_per_cycle.max_value 8
39 system.cpu.commit.COM:committed_per_cycle.end_dist
41 system.cpu.commit.COM:count 1489537507 # Number of instructions committed
42 system.cpu.commit.COM:loads 402517242 # Number of loads committed
43 system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
44 system.cpu.commit.COM:refs 569375198 # Number of memory references committed
45 system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
46 system.cpu.commit.branchMispredicts 84376140 # The number of times a branch was mispredicted
47 system.cpu.commit.commitCommittedInsts 1489537507 # The number of committed instructions
48 system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
49 system.cpu.commit.commitSquashedInsts 1379626157 # The number of squashed insts skipped by commit
50 system.cpu.committedInsts 1405618364 # Number of Instructions Simulated
51 system.cpu.committedInsts_total 1405618364 # Number of Instructions Simulated
52 system.cpu.cpi 1.568811 # CPI: Cycles Per Instruction
53 system.cpu.cpi_total 1.568811 # CPI: Total CPI of All Threads
54 system.cpu.dcache.ReadReq_accesses 431515523 # number of ReadReq accesses(hits+misses)
55 system.cpu.dcache.ReadReq_avg_miss_latency 5833.098785 # average ReadReq miss latency
56 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2978.922588 # average ReadReq mshr miss latency
57 system.cpu.dcache.ReadReq_hits 430678453 # number of ReadReq hits
58 system.cpu.dcache.ReadReq_miss_latency 4882712000 # number of ReadReq miss cycles
59 system.cpu.dcache.ReadReq_miss_rate 0.001940 # miss rate for ReadReq accesses
60 system.cpu.dcache.ReadReq_misses 837070 # number of ReadReq misses
61 system.cpu.dcache.ReadReq_mshr_hits 610026 # number of ReadReq MSHR hits
62 system.cpu.dcache.ReadReq_mshr_miss_latency 676346500 # number of ReadReq MSHR miss cycles
63 system.cpu.dcache.ReadReq_mshr_miss_rate 0.000526 # mshr miss rate for ReadReq accesses
64 system.cpu.dcache.ReadReq_mshr_misses 227044 # number of ReadReq MSHR misses
65 system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
66 system.cpu.dcache.SwapReq_avg_miss_latency 9037.500000 # average SwapReq miss latency
67 system.cpu.dcache.SwapReq_avg_mshr_miss_latency 6037.500000 # average SwapReq mshr miss latency
68 system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
69 system.cpu.dcache.SwapReq_miss_latency 361500 # number of SwapReq miss cycles
70 system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
71 system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
72 system.cpu.dcache.SwapReq_mshr_miss_latency 241500 # number of SwapReq MSHR miss cycles
73 system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
74 system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
75 system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses)
76 system.cpu.dcache.WriteReq_avg_miss_latency 10313.448208 # average WriteReq miss latency
77 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7754.282564 # average WriteReq mshr miss latency
78 system.cpu.dcache.WriteReq_hits 164722472 # number of WriteReq hits
79 system.cpu.dcache.WriteReq_miss_latency 22010528000 # number of WriteReq miss cycles
80 system.cpu.dcache.WriteReq_miss_rate 0.012790 # miss rate for WriteReq accesses
81 system.cpu.dcache.WriteReq_misses 2134158 # number of WriteReq misses
82 system.cpu.dcache.WriteReq_mshr_hits 1792190 # number of WriteReq MSHR hits
83 system.cpu.dcache.WriteReq_mshr_miss_latency 2651716500 # number of WriteReq MSHR miss cycles
84 system.cpu.dcache.WriteReq_mshr_miss_rate 0.002049 # mshr miss rate for WriteReq accesses
85 system.cpu.dcache.WriteReq_mshr_misses 341968 # number of WriteReq MSHR misses
86 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
87 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
88 system.cpu.dcache.avg_refs 1192.957701 # Average number of references to valid blocks.
89 system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
90 system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
91 system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
92 system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
93 system.cpu.dcache.cache_copies 0 # number of cache copies performed
94 system.cpu.dcache.demand_accesses 598372153 # number of demand (read+write) accesses
95 system.cpu.dcache.demand_avg_miss_latency 9051.220573 # average overall miss latency
96 system.cpu.dcache.demand_avg_mshr_miss_latency 5848.845016 # average overall mshr miss latency
97 system.cpu.dcache.demand_hits 595400925 # number of demand (read+write) hits
98 system.cpu.dcache.demand_miss_latency 26893240000 # number of demand (read+write) miss cycles
99 system.cpu.dcache.demand_miss_rate 0.004966 # miss rate for demand accesses
100 system.cpu.dcache.demand_misses 2971228 # number of demand (read+write) misses
101 system.cpu.dcache.demand_mshr_hits 2402216 # number of demand (read+write) MSHR hits
102 system.cpu.dcache.demand_mshr_miss_latency 3328063000 # number of demand (read+write) MSHR miss cycles
103 system.cpu.dcache.demand_mshr_miss_rate 0.000951 # mshr miss rate for demand accesses
104 system.cpu.dcache.demand_mshr_misses 569012 # number of demand (read+write) MSHR misses
105 system.cpu.dcache.fast_writes 0 # number of fast writes performed
106 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
107 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
108 system.cpu.dcache.overall_accesses 598372153 # number of overall (read+write) accesses
109 system.cpu.dcache.overall_avg_miss_latency 9051.220573 # average overall miss latency
110 system.cpu.dcache.overall_avg_mshr_miss_latency 5848.845016 # average overall mshr miss latency
111 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
112 system.cpu.dcache.overall_hits 595400925 # number of overall hits
113 system.cpu.dcache.overall_miss_latency 26893240000 # number of overall miss cycles
114 system.cpu.dcache.overall_miss_rate 0.004966 # miss rate for overall accesses
115 system.cpu.dcache.overall_misses 2971228 # number of overall misses
116 system.cpu.dcache.overall_mshr_hits 2402216 # number of overall MSHR hits
117 system.cpu.dcache.overall_mshr_miss_latency 3328063000 # number of overall MSHR miss cycles
118 system.cpu.dcache.overall_mshr_miss_rate 0.000951 # mshr miss rate for overall accesses
119 system.cpu.dcache.overall_mshr_misses 569012 # number of overall MSHR misses
120 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
121 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
122 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
123 system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
124 system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
125 system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
126 system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
127 system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
128 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
129 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
130 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
131 system.cpu.dcache.replacements 495162 # number of replacements
132 system.cpu.dcache.sampled_refs 499258 # Sample count of references to valid blocks.
133 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
134 system.cpu.dcache.tagsinuse 4095.748023 # Cycle average of tags in use
135 system.cpu.dcache.total_refs 595593676 # Total number of references to valid blocks.
136 system.cpu.dcache.warmup_cycle 87021000 # Cycle when the warmup percentage was hit.
137 system.cpu.dcache.writebacks 338803 # number of writebacks
138 system.cpu.decode.DECODE:BlockedCycles 411671419 # Number of cycles decode is blocked
139 system.cpu.decode.DECODE:DecodedInsts 3446173364 # Number of instructions handled by decode
140 system.cpu.decode.DECODE:IdleCycles 768410177 # Number of cycles decode is idle
141 system.cpu.decode.DECODE:RunCycles 782727450 # Number of cycles decode is running
142 system.cpu.decode.DECODE:SquashCycles 239480011 # Number of cycles decode is squashing
143 system.cpu.decode.DECODE:UnblockCycles 2858868 # Number of cycles decode is unblocking
144 system.cpu.fetch.Branches 253553370 # Number of branches that fetch encountered
145 system.cpu.fetch.CacheLines 356679957 # Number of cache lines fetched
146 system.cpu.fetch.Cycles 1203446624 # Number of cycles fetch has run and was not squashing or blocked
147 system.cpu.fetch.IcacheSquashes 10248361 # Number of outstanding Icache misses that were squashed
148 system.cpu.fetch.Insts 3739591650 # Number of instructions fetch has processed
149 system.cpu.fetch.SquashCycles 90314479 # Number of cycles fetch has spent squashing
150 system.cpu.fetch.branchRate 0.114982 # Number of branch fetches per cycle
151 system.cpu.fetch.icacheStallCycles 356679957 # Number of cycles fetch is stalled on an Icache miss
152 system.cpu.fetch.predictedBranches 181900655 # Number of branches that fetch has predicted taken
153 system.cpu.fetch.rate 1.695845 # Number of inst fetches per cycle
154 system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
155 system.cpu.fetch.rateDist.samples 2205147925
156 system.cpu.fetch.rateDist.min_value 0
157 0 1358381303 6160.05%
166 system.cpu.fetch.rateDist.max_value 8
167 system.cpu.fetch.rateDist.end_dist
169 system.cpu.icache.ReadReq_accesses 356679957 # number of ReadReq accesses(hits+misses)
170 system.cpu.icache.ReadReq_avg_miss_latency 8956.578947 # average ReadReq miss latency
171 system.cpu.icache.ReadReq_avg_mshr_miss_latency 6409.949165 # average ReadReq mshr miss latency
172 system.cpu.icache.ReadReq_hits 356678437 # number of ReadReq hits
173 system.cpu.icache.ReadReq_miss_latency 13614000 # number of ReadReq miss cycles
174 system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
175 system.cpu.icache.ReadReq_misses 1520 # number of ReadReq misses
176 system.cpu.icache.ReadReq_mshr_hits 143 # number of ReadReq MSHR hits
177 system.cpu.icache.ReadReq_mshr_miss_latency 8826500 # number of ReadReq MSHR miss cycles
178 system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
179 system.cpu.icache.ReadReq_mshr_misses 1377 # number of ReadReq MSHR misses
180 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
181 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
182 system.cpu.icache.avg_refs 259025.734931 # Average number of references to valid blocks.
183 system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
184 system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
185 system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
186 system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
187 system.cpu.icache.cache_copies 0 # number of cache copies performed
188 system.cpu.icache.demand_accesses 356679957 # number of demand (read+write) accesses
189 system.cpu.icache.demand_avg_miss_latency 8956.578947 # average overall miss latency
190 system.cpu.icache.demand_avg_mshr_miss_latency 6409.949165 # average overall mshr miss latency
191 system.cpu.icache.demand_hits 356678437 # number of demand (read+write) hits
192 system.cpu.icache.demand_miss_latency 13614000 # number of demand (read+write) miss cycles
193 system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
194 system.cpu.icache.demand_misses 1520 # number of demand (read+write) misses
195 system.cpu.icache.demand_mshr_hits 143 # number of demand (read+write) MSHR hits
196 system.cpu.icache.demand_mshr_miss_latency 8826500 # number of demand (read+write) MSHR miss cycles
197 system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
198 system.cpu.icache.demand_mshr_misses 1377 # number of demand (read+write) MSHR misses
199 system.cpu.icache.fast_writes 0 # number of fast writes performed
200 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
201 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
202 system.cpu.icache.overall_accesses 356679957 # number of overall (read+write) accesses
203 system.cpu.icache.overall_avg_miss_latency 8956.578947 # average overall miss latency
204 system.cpu.icache.overall_avg_mshr_miss_latency 6409.949165 # average overall mshr miss latency
205 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
206 system.cpu.icache.overall_hits 356678437 # number of overall hits
207 system.cpu.icache.overall_miss_latency 13614000 # number of overall miss cycles
208 system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
209 system.cpu.icache.overall_misses 1520 # number of overall misses
210 system.cpu.icache.overall_mshr_hits 143 # number of overall MSHR hits
211 system.cpu.icache.overall_mshr_miss_latency 8826500 # number of overall MSHR miss cycles
212 system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
213 system.cpu.icache.overall_mshr_misses 1377 # number of overall MSHR misses
214 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
215 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
216 system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
217 system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
218 system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
219 system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
220 system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
221 system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
222 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
223 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
224 system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
225 system.cpu.icache.replacements 225 # number of replacements
226 system.cpu.icache.sampled_refs 1377 # Sample count of references to valid blocks.
227 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
228 system.cpu.icache.tagsinuse 1055.483361 # Cycle average of tags in use
229 system.cpu.icache.total_refs 356678437 # Total number of references to valid blocks.
230 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
231 system.cpu.icache.writebacks 0 # number of writebacks
232 system.cpu.idleCycles 1248 # Total number of cycles that the CPU has spent unscheduled due to idling
233 system.cpu.iew.EXEC:branches 127608554 # Number of branches executed
234 system.cpu.iew.EXEC:nop 350339648 # number of nop insts executed
235 system.cpu.iew.EXEC:rate 0.854427 # Inst execution rate
236 system.cpu.iew.EXEC:refs 751913263 # number of memory reference insts executed
237 system.cpu.iew.EXEC:stores 205327824 # Number of stores executed
238 system.cpu.iew.EXEC:swp 0 # number of swp insts executed
239 system.cpu.iew.WB:consumers 1480064020 # num instructions consuming a value
240 system.cpu.iew.WB:count 1846024853 # cumulative count of insts written-back
241 system.cpu.iew.WB:fanout 0.961974 # average fanout of values written-back
242 system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
243 system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
244 system.cpu.iew.WB:producers 1423783452 # num instructions producing a value
245 system.cpu.iew.WB:rate 0.837143 # insts written-back per cycle
246 system.cpu.iew.WB:sent 1859136578 # cumulative count of insts sent to commit
247 system.cpu.iew.branchMispredicts 92169933 # Number of branch mispredicts detected at execute
248 system.cpu.iew.iewBlockCycles 589367 # Number of cycles IEW is blocking
249 system.cpu.iew.iewDispLoadInsts 741823023 # Number of dispatched load instructions
250 system.cpu.iew.iewDispNonSpecInsts 21373777 # Number of dispatched non-speculative instructions
251 system.cpu.iew.iewDispSquashedInsts 17132653 # Number of squashed instructions skipped by dispatch
252 system.cpu.iew.iewDispStoreInsts 303434035 # Number of dispatched store instructions
253 system.cpu.iew.iewDispatchedInsts 2869227464 # Number of instructions dispatched to IQ
254 system.cpu.iew.iewExecLoadInsts 546585439 # Number of load instructions executed
255 system.cpu.iew.iewExecSquashedInsts 102564755 # Number of squashed instructions skipped in execute
256 system.cpu.iew.iewExecutedInsts 1884138731 # Number of executed instructions
257 system.cpu.iew.iewIQFullEvents 34478 # Number of times the IQ has become full, causing a stall
258 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
259 system.cpu.iew.iewLSQFullEvents 6242 # Number of times the LSQ has become full, causing a stall
260 system.cpu.iew.iewSquashCycles 239480011 # Number of cycles IEW is squashing
261 system.cpu.iew.iewUnblockCycles 64953 # Number of cycles IEW is unblocking
262 system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
263 system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
264 system.cpu.iew.lsq.thread.0.forwLoads 115050896 # Number of loads that had data forwarded from stores
265 system.cpu.iew.lsq.thread.0.ignoredResponses 46197 # Number of memory responses ignored because the instruction is squashed
266 system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
267 system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
268 system.cpu.iew.lsq.thread.0.memOrderViolation 6187252 # Number of memory ordering violations
269 system.cpu.iew.lsq.thread.0.rescheduledLoads 5 # Number of loads that were rescheduled
270 system.cpu.iew.lsq.thread.0.squashedLoads 339305781 # Number of loads squashed
271 system.cpu.iew.lsq.thread.0.squashedStores 136576079 # Number of stores squashed
272 system.cpu.iew.memOrderViolationEvents 6187252 # Number of memory order violations
273 system.cpu.iew.predictedNotTakenIncorrect 1512583 # Number of branches that were predicted not taken incorrectly
274 system.cpu.iew.predictedTakenIncorrect 90657350 # Number of branches that were predicted taken incorrectly
275 system.cpu.ipc 0.637426 # IPC: Instructions Per Cycle
276 system.cpu.ipc_total 0.637426 # IPC: Total IPC of All Threads
277 system.cpu.iq.ISSUE:FU_type_0 1986703486 # Type of FU issued
278 system.cpu.iq.ISSUE:FU_type_0.start_dist
279 No_OpClass 0 0.00% # Type of FU issued
280 IntAlu 1179878973 59.39% # Type of FU issued
281 IntMult 0 0.00% # Type of FU issued
282 IntDiv 0 0.00% # Type of FU issued
283 FloatAdd 3034527 0.15% # Type of FU issued
284 FloatCmp 0 0.00% # Type of FU issued
285 FloatCvt 0 0.00% # Type of FU issued
286 FloatMult 0 0.00% # Type of FU issued
287 FloatDiv 0 0.00% # Type of FU issued
288 FloatSqrt 0 0.00% # Type of FU issued
289 MemRead 573304663 28.86% # Type of FU issued
290 MemWrite 230485323 11.60% # Type of FU issued
291 IprAccess 0 0.00% # Type of FU issued
292 InstPrefetch 0 0.00% # Type of FU issued
293 system.cpu.iq.ISSUE:FU_type_0.end_dist
294 system.cpu.iq.ISSUE:fu_busy_cnt 3941252 # FU busy when requested
295 system.cpu.iq.ISSUE:fu_busy_rate 0.001984 # FU busy rate (busy events/executed inst)
296 system.cpu.iq.ISSUE:fu_full.start_dist
297 No_OpClass 0 0.00% # attempts to use FU when none available
298 IntAlu 143239 3.63% # attempts to use FU when none available
299 IntMult 0 0.00% # attempts to use FU when none available
300 IntDiv 0 0.00% # attempts to use FU when none available
301 FloatAdd 224135 5.69% # attempts to use FU when none available
302 FloatCmp 0 0.00% # attempts to use FU when none available
303 FloatCvt 0 0.00% # attempts to use FU when none available
304 FloatMult 0 0.00% # attempts to use FU when none available
305 FloatDiv 0 0.00% # attempts to use FU when none available
306 FloatSqrt 0 0.00% # attempts to use FU when none available
307 MemRead 3231256 81.99% # attempts to use FU when none available
308 MemWrite 342622 8.69% # attempts to use FU when none available
309 IprAccess 0 0.00% # attempts to use FU when none available
310 InstPrefetch 0 0.00% # attempts to use FU when none available
311 system.cpu.iq.ISSUE:fu_full.end_dist
312 system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
313 system.cpu.iq.ISSUE:issued_per_cycle.samples 2205147925
314 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
315 0 1087983599 4933.83%
324 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
325 system.cpu.iq.ISSUE:issued_per_cycle.end_dist
327 system.cpu.iq.ISSUE:rate 0.900938 # Inst issue rate
328 system.cpu.iq.iqInstsAdded 2497217188 # Number of instructions added to the IQ (excludes non-spec)
329 system.cpu.iq.iqInstsIssued 1986703486 # Number of instructions issued
330 system.cpu.iq.iqNonSpecInstsAdded 21670628 # Number of non-speculative instructions added to the IQ
331 system.cpu.iq.iqSquashedInstsExamined 1069660701 # Number of squashed instructions iterated over during squash; mainly for profiling
332 system.cpu.iq.iqSquashedInstsIssued 613054 # Number of squashed instructions issued
333 system.cpu.iq.iqSquashedNonSpecRemoved 19426957 # Number of squashed non-spec instructions that were removed
334 system.cpu.iq.iqSquashedOperandsExamined 1294993120 # Number of squashed operands that are examined and possibly removed from graph
335 system.cpu.l2cache.ReadExReq_accesses 272214 # number of ReadExReq accesses(hits+misses)
336 system.cpu.l2cache.ReadExReq_avg_miss_latency 5811.034701 # average ReadExReq miss latency
337 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2811.034701 # average ReadExReq mshr miss latency
338 system.cpu.l2cache.ReadExReq_miss_latency 1581845000 # number of ReadExReq miss cycles
339 system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
340 system.cpu.l2cache.ReadExReq_misses 272214 # number of ReadExReq misses
341 system.cpu.l2cache.ReadExReq_mshr_miss_latency 765203000 # number of ReadExReq MSHR miss cycles
342 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
343 system.cpu.l2cache.ReadExReq_mshr_misses 272214 # number of ReadExReq MSHR misses
344 system.cpu.l2cache.ReadReq_accesses 228421 # number of ReadReq accesses(hits+misses)
345 system.cpu.l2cache.ReadReq_avg_miss_latency 5108.517819 # average ReadReq miss latency
346 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2108.517819 # average ReadReq mshr miss latency
347 system.cpu.l2cache.ReadReq_hits 193459 # number of ReadReq hits
348 system.cpu.l2cache.ReadReq_miss_latency 178604000 # number of ReadReq miss cycles
349 system.cpu.l2cache.ReadReq_miss_rate 0.153059 # miss rate for ReadReq accesses
350 system.cpu.l2cache.ReadReq_misses 34962 # number of ReadReq misses
351 system.cpu.l2cache.ReadReq_mshr_miss_latency 73718000 # number of ReadReq MSHR miss cycles
352 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153059 # mshr miss rate for ReadReq accesses
353 system.cpu.l2cache.ReadReq_mshr_misses 34962 # number of ReadReq MSHR misses
354 system.cpu.l2cache.UpgradeReq_accesses 69801 # number of UpgradeReq accesses(hits+misses)
355 system.cpu.l2cache.UpgradeReq_avg_miss_latency 5210.620192 # average UpgradeReq miss latency
356 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2210.777783 # average UpgradeReq mshr miss latency
357 system.cpu.l2cache.UpgradeReq_miss_latency 363706500 # number of UpgradeReq miss cycles
358 system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
359 system.cpu.l2cache.UpgradeReq_misses 69801 # number of UpgradeReq misses
360 system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154314500 # number of UpgradeReq MSHR miss cycles
361 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
362 system.cpu.l2cache.UpgradeReq_mshr_misses 69801 # number of UpgradeReq MSHR misses
363 system.cpu.l2cache.Writeback_accesses 338803 # number of Writeback accesses(hits+misses)
364 system.cpu.l2cache.Writeback_hits 338803 # number of Writeback hits
365 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
366 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
367 system.cpu.l2cache.avg_refs 3.926755 # Average number of references to valid blocks.
368 system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
369 system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
370 system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
371 system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
372 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
373 system.cpu.l2cache.demand_accesses 500635 # number of demand (read+write) accesses
374 system.cpu.l2cache.demand_avg_miss_latency 5731.075996 # average overall miss latency
375 system.cpu.l2cache.demand_avg_mshr_miss_latency 2731.075996 # average overall mshr miss latency
376 system.cpu.l2cache.demand_hits 193459 # number of demand (read+write) hits
377 system.cpu.l2cache.demand_miss_latency 1760449000 # number of demand (read+write) miss cycles
378 system.cpu.l2cache.demand_miss_rate 0.613573 # miss rate for demand accesses
379 system.cpu.l2cache.demand_misses 307176 # number of demand (read+write) misses
380 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
381 system.cpu.l2cache.demand_mshr_miss_latency 838921000 # number of demand (read+write) MSHR miss cycles
382 system.cpu.l2cache.demand_mshr_miss_rate 0.613573 # mshr miss rate for demand accesses
383 system.cpu.l2cache.demand_mshr_misses 307176 # number of demand (read+write) MSHR misses
384 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
385 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
386 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
387 system.cpu.l2cache.overall_accesses 500635 # number of overall (read+write) accesses
388 system.cpu.l2cache.overall_avg_miss_latency 5731.075996 # average overall miss latency
389 system.cpu.l2cache.overall_avg_mshr_miss_latency 2731.075996 # average overall mshr miss latency
390 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
391 system.cpu.l2cache.overall_hits 193459 # number of overall hits
392 system.cpu.l2cache.overall_miss_latency 1760449000 # number of overall miss cycles
393 system.cpu.l2cache.overall_miss_rate 0.613573 # miss rate for overall accesses
394 system.cpu.l2cache.overall_misses 307176 # number of overall misses
395 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
396 system.cpu.l2cache.overall_mshr_miss_latency 838921000 # number of overall MSHR miss cycles
397 system.cpu.l2cache.overall_mshr_miss_rate 0.613573 # mshr miss rate for overall accesses
398 system.cpu.l2cache.overall_mshr_misses 307176 # number of overall MSHR misses
399 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
400 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
401 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
402 system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
403 system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
404 system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
405 system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
406 system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
407 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
408 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
409 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
410 system.cpu.l2cache.replacements 84458 # number of replacements
411 system.cpu.l2cache.sampled_refs 99911 # Sample count of references to valid blocks.
412 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
413 system.cpu.l2cache.tagsinuse 16412.598383 # Cycle average of tags in use
414 system.cpu.l2cache.total_refs 392326 # Total number of references to valid blocks.
415 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
416 system.cpu.l2cache.writebacks 61939 # number of writebacks
417 system.cpu.numCycles 2205149173 # number of cpu cycles simulated
418 system.cpu.rename.RENAME:BlockCycles 14473235 # Number of cycles rename is blocking
419 system.cpu.rename.RENAME:CommittedMaps 1244779248 # Number of HB maps that are committed
420 system.cpu.rename.RENAME:FullRegisterEvents 14 # Number of times there has been no free registers
421 system.cpu.rename.RENAME:IQFullEvents 33041 # Number of times rename has blocked due to IQ full
422 system.cpu.rename.RENAME:IdleCycles 831090066 # Number of cycles rename is idle
423 system.cpu.rename.RENAME:LSQFullEvents 23088137 # Number of times rename has blocked due to LSQ full
424 system.cpu.rename.RENAME:RenameLookups 4934375551 # Number of register rename lookups that rename has made
425 system.cpu.rename.RENAME:RenamedInsts 3102245036 # Number of instructions processed by rename
426 system.cpu.rename.RENAME:RenamedOperands 2427299354 # Number of destination operands rename has renamed
427 system.cpu.rename.RENAME:RunCycles 719533567 # Number of cycles rename is running
428 system.cpu.rename.RENAME:SquashCycles 239480011 # Number of cycles rename is squashing
429 system.cpu.rename.RENAME:UnblockCycles 32278503 # Number of cycles rename is unblocking
430 system.cpu.rename.RENAME:UndoneMaps 1182520106 # Number of HB maps that are undone due to squashing
431 system.cpu.rename.RENAME:serializeStallCycles 368292543 # count of cycles rename stalled for serializing inst
432 system.cpu.rename.RENAME:serializingInsts 22008551 # count of serializing insts renamed
433 system.cpu.rename.RENAME:skidInsts 170259176 # count of insts added to the skid buffer
434 system.cpu.rename.RENAME:tempSerializingInsts 21764852 # count of temporary serializing insts renamed
435 system.cpu.timesIdled 5225 # Number of times that the entire CPU went into an idle state and unscheduled itself
436 system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
438 ---------- End Simulation Statistics ----------
projects / gem5.git / blob