tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 time_sync_enable=false
   5 time_sync_period=100000000000
   6 time_sync_spin_threshold=100000000
   7
   8 [system]
   9 type=System
  10 children=cpu membus physmem
  11 mem_mode=atomic
  12 memories=system.physmem
  13 physmem=system.physmem
  14 work_begin_ckpt_count=0
  15 work_begin_cpu_id_exit=-1
  16 work_begin_exit_count=0
  17 work_cpus_ckpt_count=0
  18 work_end_ckpt_count=0
  19 work_end_exit_count=0
  20 work_item_id=-1
  21
  22 [system.cpu]
  23 type=DerivO3CPU
  24 children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
  25 BTBEntries=4096
  26 BTBTagSize=16
  27 LFSTSize=1024
  28 LQEntries=32
  29 LSQCheckLoads=true
  30 LSQDepCheckShift=4
  31 RASSize=16
  32 SQEntries=32
  33 SSITSize=1024
  34 activity=0
  35 backComSize=5
  36 cachePorts=200
  37 checker=Null
  38 choiceCtrBits=2
  39 choicePredictorSize=8192
  40 clock=500
  41 commitToDecodeDelay=1
  42 commitToFetchDelay=1
  43 commitToIEWDelay=1
  44 commitToRenameDelay=1
  45 commitWidth=8
  46 cpu_id=0
  47 decodeToFetchDelay=1
  48 decodeToRenameDelay=1
  49 decodeWidth=8
  50 defer_registration=false
  51 dispatchWidth=8
  52 do_checkpoint_insts=true
  53 do_statistics_insts=true
  54 dtb=system.cpu.dtb
  55 fetchToDecodeDelay=1
  56 fetchTrapLatency=1
  57 fetchWidth=8
  58 forwardComSize=5
  59 fuPool=system.cpu.fuPool
  60 function_trace=false
  61 function_trace_start=0
  62 globalCtrBits=2
  63 globalHistoryBits=13
  64 globalPredictorSize=8192
  65 iewToCommitDelay=1
  66 iewToDecodeDelay=1
  67 iewToFetchDelay=1
  68 iewToRenameDelay=1
  69 instShiftAmt=2
  70 issueToExecuteDelay=1
  71 issueWidth=8
  72 itb=system.cpu.itb
  73 localCtrBits=2
  74 localHistoryBits=11
  75 localHistoryTableSize=2048
  76 localPredictorSize=2048
  77 max_insts_all_threads=0
  78 max_insts_any_thread=0
  79 max_loads_all_threads=0
  80 max_loads_any_thread=0
  81 numIQEntries=64
  82 numPhysFloatRegs=256
  83 numPhysIntRegs=256
  84 numROBEntries=192
  85 numRobs=1
  86 numThreads=1
  87 phase=0
  88 predType=tournament
  89 progress_interval=0
  90 renameToDecodeDelay=1
  91 renameToFetchDelay=1
  92 renameToIEWDelay=2
  93 renameToROBDelay=1
  94 renameWidth=8
  95 smtCommitPolicy=RoundRobin
  96 smtFetchPolicy=SingleThread
  97 smtIQPolicy=Partitioned
  98 smtIQThreshold=100
  99 smtLSQPolicy=Partitioned
 100 smtLSQThreshold=100
 101 smtNumFetchingThreads=1
 102 smtROBPolicy=Partitioned
 103 smtROBThreshold=100
 104 squashWidth=8
 105 store_set_clear_period=250000
 106 system=system
 107 tracer=system.cpu.tracer
 108 trapLatency=13
 109 wbDepth=1
 110 wbWidth=8
 111 workload=system.cpu.workload
 112 dcache_port=system.cpu.dcache.cpu_side
 113 icache_port=system.cpu.icache.cpu_side
 114
 115 [system.cpu.dcache]
 116 type=BaseCache
 117 addr_range=0:18446744073709551615
 118 assoc=2
 119 block_size=64
 120 forward_snoops=true
 121 hash_delay=1
 122 is_top_level=true
 123 latency=1000
 124 max_miss_count=0
 125 mshrs=10
 126 num_cpus=1
 127 prefetch_data_accesses_only=false
 128 prefetch_degree=1
 129 prefetch_latency=10000
 130 prefetch_on_access=false
 131 prefetch_past_page=false
 132 prefetch_policy=none
 133 prefetch_serial_squash=false
 134 prefetch_use_cpu_id=true
 135 prefetcher_size=100
 136 prioritizeRequests=false
 137 repl=Null
 138 size=262144
 139 subblock_size=0
 140 tgts_per_mshr=20
 141 trace_addr=0
 142 two_queue=false
 143 write_buffers=8
 144 cpu_side=system.cpu.dcache_port
 145 mem_side=system.cpu.toL2Bus.port[1]
 146
 147 [system.cpu.dtb]
 148 type=X86TLB
 149 size=64
 150
 151 [system.cpu.fuPool]
 152 type=FUPool
 153 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 154 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 155
 156 [system.cpu.fuPool.FUList0]
 157 type=FUDesc
 158 children=opList
 159 count=6
 160 opList=system.cpu.fuPool.FUList0.opList
 161
 162 [system.cpu.fuPool.FUList0.opList]
 163 type=OpDesc
 164 issueLat=1
 165 opClass=IntAlu
 166 opLat=1
 167
 168 [system.cpu.fuPool.FUList1]
 169 type=FUDesc
 170 children=opList0 opList1
 171 count=2
 172 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 173
 174 [system.cpu.fuPool.FUList1.opList0]
 175 type=OpDesc
 176 issueLat=1
 177 opClass=IntMult
 178 opLat=3
 179
 180 [system.cpu.fuPool.FUList1.opList1]
 181 type=OpDesc
 182 issueLat=19
 183 opClass=IntDiv
 184 opLat=20
 185
 186 [system.cpu.fuPool.FUList2]
 187 type=FUDesc
 188 children=opList0 opList1 opList2
 189 count=4
 190 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 191
 192 [system.cpu.fuPool.FUList2.opList0]
 193 type=OpDesc
 194 issueLat=1
 195 opClass=FloatAdd
 196 opLat=2
 197
 198 [system.cpu.fuPool.FUList2.opList1]
 199 type=OpDesc
 200 issueLat=1
 201 opClass=FloatCmp
 202 opLat=2
 203
 204 [system.cpu.fuPool.FUList2.opList2]
 205 type=OpDesc
 206 issueLat=1
 207 opClass=FloatCvt
 208 opLat=2
 209
 210 [system.cpu.fuPool.FUList3]
 211 type=FUDesc
 212 children=opList0 opList1 opList2
 213 count=2
 214 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 215
 216 [system.cpu.fuPool.FUList3.opList0]
 217 type=OpDesc
 218 issueLat=1
 219 opClass=FloatMult
 220 opLat=4
 221
 222 [system.cpu.fuPool.FUList3.opList1]
 223 type=OpDesc
 224 issueLat=12
 225 opClass=FloatDiv
 226 opLat=12
 227
 228 [system.cpu.fuPool.FUList3.opList2]
 229 type=OpDesc
 230 issueLat=24
 231 opClass=FloatSqrt
 232 opLat=24
 233
 234 [system.cpu.fuPool.FUList4]
 235 type=FUDesc
 236 children=opList
 237 count=0
 238 opList=system.cpu.fuPool.FUList4.opList
 239
 240 [system.cpu.fuPool.FUList4.opList]
 241 type=OpDesc
 242 issueLat=1
 243 opClass=MemRead
 244 opLat=1
 245
 246 [system.cpu.fuPool.FUList5]
 247 type=FUDesc
 248 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 249 count=4
 250 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 251
 252 [system.cpu.fuPool.FUList5.opList00]
 253 type=OpDesc
 254 issueLat=1
 255 opClass=SimdAdd
 256 opLat=1
 257
 258 [system.cpu.fuPool.FUList5.opList01]
 259 type=OpDesc
 260 issueLat=1
 261 opClass=SimdAddAcc
 262 opLat=1
 263
 264 [system.cpu.fuPool.FUList5.opList02]
 265 type=OpDesc
 266 issueLat=1
 267 opClass=SimdAlu
 268 opLat=1
 269
 270 [system.cpu.fuPool.FUList5.opList03]
 271 type=OpDesc
 272 issueLat=1
 273 opClass=SimdCmp
 274 opLat=1
 275
 276 [system.cpu.fuPool.FUList5.opList04]
 277 type=OpDesc
 278 issueLat=1
 279 opClass=SimdCvt
 280 opLat=1
 281
 282 [system.cpu.fuPool.FUList5.opList05]
 283 type=OpDesc
 284 issueLat=1
 285 opClass=SimdMisc
 286 opLat=1
 287
 288 [system.cpu.fuPool.FUList5.opList06]
 289 type=OpDesc
 290 issueLat=1
 291 opClass=SimdMult
 292 opLat=1
 293
 294 [system.cpu.fuPool.FUList5.opList07]
 295 type=OpDesc
 296 issueLat=1
 297 opClass=SimdMultAcc
 298 opLat=1
 299
 300 [system.cpu.fuPool.FUList5.opList08]
 301 type=OpDesc
 302 issueLat=1
 303 opClass=SimdShift
 304 opLat=1
 305
 306 [system.cpu.fuPool.FUList5.opList09]
 307 type=OpDesc
 308 issueLat=1
 309 opClass=SimdShiftAcc
 310 opLat=1
 311
 312 [system.cpu.fuPool.FUList5.opList10]
 313 type=OpDesc
 314 issueLat=1
 315 opClass=SimdSqrt
 316 opLat=1
 317
 318 [system.cpu.fuPool.FUList5.opList11]
 319 type=OpDesc
 320 issueLat=1
 321 opClass=SimdFloatAdd
 322 opLat=1
 323
 324 [system.cpu.fuPool.FUList5.opList12]
 325 type=OpDesc
 326 issueLat=1
 327 opClass=SimdFloatAlu
 328 opLat=1
 329
 330 [system.cpu.fuPool.FUList5.opList13]
 331 type=OpDesc
 332 issueLat=1
 333 opClass=SimdFloatCmp
 334 opLat=1
 335
 336 [system.cpu.fuPool.FUList5.opList14]
 337 type=OpDesc
 338 issueLat=1
 339 opClass=SimdFloatCvt
 340 opLat=1
 341
 342 [system.cpu.fuPool.FUList5.opList15]
 343 type=OpDesc
 344 issueLat=1
 345 opClass=SimdFloatDiv
 346 opLat=1
 347
 348 [system.cpu.fuPool.FUList5.opList16]
 349 type=OpDesc
 350 issueLat=1
 351 opClass=SimdFloatMisc
 352 opLat=1
 353
 354 [system.cpu.fuPool.FUList5.opList17]
 355 type=OpDesc
 356 issueLat=1
 357 opClass=SimdFloatMult
 358 opLat=1
 359
 360 [system.cpu.fuPool.FUList5.opList18]
 361 type=OpDesc
 362 issueLat=1
 363 opClass=SimdFloatMultAcc
 364 opLat=1
 365
 366 [system.cpu.fuPool.FUList5.opList19]
 367 type=OpDesc
 368 issueLat=1
 369 opClass=SimdFloatSqrt
 370 opLat=1
 371
 372 [system.cpu.fuPool.FUList6]
 373 type=FUDesc
 374 children=opList
 375 count=0
 376 opList=system.cpu.fuPool.FUList6.opList
 377
 378 [system.cpu.fuPool.FUList6.opList]
 379 type=OpDesc
 380 issueLat=1
 381 opClass=MemWrite
 382 opLat=1
 383
 384 [system.cpu.fuPool.FUList7]
 385 type=FUDesc
 386 children=opList0 opList1
 387 count=4
 388 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 389
 390 [system.cpu.fuPool.FUList7.opList0]
 391 type=OpDesc
 392 issueLat=1
 393 opClass=MemRead
 394 opLat=1
 395
 396 [system.cpu.fuPool.FUList7.opList1]
 397 type=OpDesc
 398 issueLat=1
 399 opClass=MemWrite
 400 opLat=1
 401
 402 [system.cpu.fuPool.FUList8]
 403 type=FUDesc
 404 children=opList
 405 count=1
 406 opList=system.cpu.fuPool.FUList8.opList
 407
 408 [system.cpu.fuPool.FUList8.opList]
 409 type=OpDesc
 410 issueLat=3
 411 opClass=IprAccess
 412 opLat=3
 413
 414 [system.cpu.icache]
 415 type=BaseCache
 416 addr_range=0:18446744073709551615
 417 assoc=2
 418 block_size=64
 419 forward_snoops=true
 420 hash_delay=1
 421 is_top_level=true
 422 latency=1000
 423 max_miss_count=0
 424 mshrs=10
 425 num_cpus=1
 426 prefetch_data_accesses_only=false
 427 prefetch_degree=1
 428 prefetch_latency=10000
 429 prefetch_on_access=false
 430 prefetch_past_page=false
 431 prefetch_policy=none
 432 prefetch_serial_squash=false
 433 prefetch_use_cpu_id=true
 434 prefetcher_size=100
 435 prioritizeRequests=false
 436 repl=Null
 437 size=131072
 438 subblock_size=0
 439 tgts_per_mshr=20
 440 trace_addr=0
 441 two_queue=false
 442 write_buffers=8
 443 cpu_side=system.cpu.icache_port
 444 mem_side=system.cpu.toL2Bus.port[0]
 445
 446 [system.cpu.itb]
 447 type=X86TLB
 448 size=64
 449
 450 [system.cpu.l2cache]
 451 type=BaseCache
 452 addr_range=0:18446744073709551615
 453 assoc=2
 454 block_size=64
 455 forward_snoops=true
 456 hash_delay=1
 457 is_top_level=false
 458 latency=1000
 459 max_miss_count=0
 460 mshrs=10
 461 num_cpus=1
 462 prefetch_data_accesses_only=false
 463 prefetch_degree=1
 464 prefetch_latency=10000
 465 prefetch_on_access=false
 466 prefetch_past_page=false
 467 prefetch_policy=none
 468 prefetch_serial_squash=false
 469 prefetch_use_cpu_id=true
 470 prefetcher_size=100
 471 prioritizeRequests=false
 472 repl=Null
 473 size=2097152
 474 subblock_size=0
 475 tgts_per_mshr=5
 476 trace_addr=0
 477 two_queue=false
 478 write_buffers=8
 479 cpu_side=system.cpu.toL2Bus.port[2]
 480 mem_side=system.membus.port[1]
 481
 482 [system.cpu.toL2Bus]
 483 type=Bus
 484 block_size=64
 485 bus_id=0
 486 clock=1000
 487 header_cycles=1
 488 use_default_range=false
 489 width=64
 490 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 491
 492 [system.cpu.tracer]
 493 type=ExeTracer
 494
 495 [system.cpu.workload]
 496 type=LiveProcess
 497 cmd=gzip input.log 1
 498 cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
 499 egid=100
 500 env=
 501 errout=cerr
 502 euid=100
 503 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
 504 gid=100
 505 input=cin
 506 max_stack_size=67108864
 507 output=cout
 508 pid=100
 509 ppid=99
 510 simpoint=0
 511 system=system
 512 uid=100
 513
 514 [system.membus]
 515 type=Bus
 516 block_size=64
 517 bus_id=0
 518 clock=1000
 519 header_cycles=1
 520 use_default_range=false
 521 width=64
 522 port=system.physmem.port[0] system.cpu.l2cache.mem_side
 523
 524 [system.physmem]
 525 type=PhysicalMemory
 526 file=
 527 latency=30000
 528 latency_var=0
 529 null=false
 530 range=0:134217727
 531 zero=false
 532 port=system.membus.port[0]
 533