Stats: Update the x86 stats to reflect changing stupd to a store and update.
[gem5.git] / tests / long / 00.gzip / ref / x86 / linux / simple-timing / config.ini
1 [root]
2 type=Root
3 children=system
4 time_sync_enable=false
5 time_sync_period=100000000000
6 time_sync_spin_threshold=100000000
7
8 [system]
9 type=System
10 children=cpu membus physmem
11 mem_mode=atomic
12 physmem=system.physmem
13
14 [system.cpu]
15 type=TimingSimpleCPU
16 children=dcache dtb icache itb l2cache toL2Bus tracer workload
17 checker=Null
18 clock=500
19 cpu_id=0
20 defer_registration=false
21 do_checkpoint_insts=true
22 do_statistics_insts=true
23 dtb=system.cpu.dtb
24 function_trace=false
25 function_trace_start=0
26 itb=system.cpu.itb
27 max_insts_all_threads=0
28 max_insts_any_thread=0
29 max_loads_all_threads=0
30 max_loads_any_thread=0
31 numThreads=1
32 phase=0
33 progress_interval=0
34 system=system
35 tracer=system.cpu.tracer
36 workload=system.cpu.workload
37 dcache_port=system.cpu.dcache.cpu_side
38 icache_port=system.cpu.icache.cpu_side
39
40 [system.cpu.dcache]
41 type=BaseCache
42 addr_range=0:18446744073709551615
43 assoc=2
44 block_size=64
45 forward_snoops=true
46 hash_delay=1
47 latency=1000
48 max_miss_count=0
49 mshrs=10
50 num_cpus=1
51 prefetch_data_accesses_only=false
52 prefetch_degree=1
53 prefetch_latency=10000
54 prefetch_on_access=false
55 prefetch_past_page=false
56 prefetch_policy=none
57 prefetch_serial_squash=false
58 prefetch_use_cpu_id=true
59 prefetcher_size=100
60 prioritizeRequests=false
61 repl=Null
62 size=262144
63 subblock_size=0
64 tgts_per_mshr=5
65 trace_addr=0
66 two_queue=false
67 write_buffers=8
68 cpu_side=system.cpu.dcache_port
69 mem_side=system.cpu.toL2Bus.port[1]
70
71 [system.cpu.dtb]
72 type=X86TLB
73 size=64
74
75 [system.cpu.icache]
76 type=BaseCache
77 addr_range=0:18446744073709551615
78 assoc=2
79 block_size=64
80 forward_snoops=true
81 hash_delay=1
82 latency=1000
83 max_miss_count=0
84 mshrs=10
85 num_cpus=1
86 prefetch_data_accesses_only=false
87 prefetch_degree=1
88 prefetch_latency=10000
89 prefetch_on_access=false
90 prefetch_past_page=false
91 prefetch_policy=none
92 prefetch_serial_squash=false
93 prefetch_use_cpu_id=true
94 prefetcher_size=100
95 prioritizeRequests=false
96 repl=Null
97 size=131072
98 subblock_size=0
99 tgts_per_mshr=5
100 trace_addr=0
101 two_queue=false
102 write_buffers=8
103 cpu_side=system.cpu.icache_port
104 mem_side=system.cpu.toL2Bus.port[0]
105
106 [system.cpu.itb]
107 type=X86TLB
108 size=64
109
110 [system.cpu.l2cache]
111 type=BaseCache
112 addr_range=0:18446744073709551615
113 assoc=2
114 block_size=64
115 forward_snoops=true
116 hash_delay=1
117 latency=10000
118 max_miss_count=0
119 mshrs=10
120 num_cpus=1
121 prefetch_data_accesses_only=false
122 prefetch_degree=1
123 prefetch_latency=100000
124 prefetch_on_access=false
125 prefetch_past_page=false
126 prefetch_policy=none
127 prefetch_serial_squash=false
128 prefetch_use_cpu_id=true
129 prefetcher_size=100
130 prioritizeRequests=false
131 repl=Null
132 size=2097152
133 subblock_size=0
134 tgts_per_mshr=5
135 trace_addr=0
136 two_queue=false
137 write_buffers=8
138 cpu_side=system.cpu.toL2Bus.port[2]
139 mem_side=system.membus.port[1]
140
141 [system.cpu.toL2Bus]
142 type=Bus
143 block_size=64
144 bus_id=0
145 clock=1000
146 header_cycles=1
147 use_default_range=false
148 width=64
149 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
150
151 [system.cpu.tracer]
152 type=ExeTracer
153
154 [system.cpu.workload]
155 type=LiveProcess
156 cmd=gzip input.log 1
157 cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
158 egid=100
159 env=
160 errout=cerr
161 euid=100
162 executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
163 gid=100
164 input=cin
165 max_stack_size=67108864
166 output=cout
167 pid=100
168 ppid=99
169 simpoint=0
170 system=system
171 uid=100
172
173 [system.membus]
174 type=Bus
175 block_size=64
176 bus_id=0
177 clock=1000
178 header_cycles=1
179 use_default_range=false
180 width=64
181 port=system.physmem.port[0] system.cpu.l2cache.mem_side
182
183 [system.physmem]
184 type=PhysicalMemory
185 file=
186 latency=30000
187 latency_var=0
188 null=false
189 range=0:134217727
190 zero=false
191 port=system.membus.port[0]
192