2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 1099985 # Simulator instruction rate (inst/s)
4 host_mem_usage 227480 # Number of bytes of host memory used
5 host_seconds 1474.11 # Real time elapsed on the host
6 host_tick_rate 1223290364 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 1621493983 # Number of instructions simulated
9 sim_seconds 1.803259 # Number of seconds simulated
10 sim_ticks 1803258587000 # Number of ticks simulated
11 system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses)
12 system.cpu.dcache.ReadReq_avg_miss_latency 20490.305383 # average ReadReq miss latency
13 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17490.305383 # average ReadReq mshr miss latency
14 system.cpu.dcache.ReadReq_hits 418844799 # number of ReadReq hits
15 system.cpu.dcache.ReadReq_miss_latency 4043270000 # number of ReadReq miss cycles
16 system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses
17 system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses
18 system.cpu.dcache.ReadReq_mshr_miss_latency 3451292000 # number of ReadReq MSHR miss cycles
19 system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses
20 system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses
21 system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
22 system.cpu.dcache.WriteReq_avg_miss_latency 23997.572756 # average WriteReq miss latency
23 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20997.572756 # average WriteReq mshr miss latency
24 system.cpu.dcache.WriteReq_hits 187941335 # number of WriteReq hits
25 system.cpu.dcache.WriteReq_miss_latency 5872734000 # number of WriteReq miss cycles
26 system.cpu.dcache.WriteReq_miss_rate 0.001300 # miss rate for WriteReq accesses
27 system.cpu.dcache.WriteReq_misses 244722 # number of WriteReq misses
28 system.cpu.dcache.WriteReq_mshr_miss_latency 5138568000 # number of WriteReq MSHR miss cycles
29 system.cpu.dcache.WriteReq_mshr_miss_rate 0.001300 # mshr miss rate for WriteReq accesses
30 system.cpu.dcache.WriteReq_mshr_misses 244722 # number of WriteReq MSHR misses
31 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
32 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
33 system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks.
34 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
35 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
36 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
37 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
38 system.cpu.dcache.cache_copies 0 # number of cache copies performed
39 system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses
40 system.cpu.dcache.demand_avg_miss_latency 22431.962140 # average overall miss latency
41 system.cpu.dcache.demand_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency
42 system.cpu.dcache.demand_hits 606786134 # number of demand (read+write) hits
43 system.cpu.dcache.demand_miss_latency 9916004000 # number of demand (read+write) miss cycles
44 system.cpu.dcache.demand_miss_rate 0.000728 # miss rate for demand accesses
45 system.cpu.dcache.demand_misses 442048 # number of demand (read+write) misses
46 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
47 system.cpu.dcache.demand_mshr_miss_latency 8589860000 # number of demand (read+write) MSHR miss cycles
48 system.cpu.dcache.demand_mshr_miss_rate 0.000728 # mshr miss rate for demand accesses
49 system.cpu.dcache.demand_mshr_misses 442048 # number of demand (read+write) MSHR misses
50 system.cpu.dcache.fast_writes 0 # number of fast writes performed
51 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
52 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
53 system.cpu.dcache.occ_%::0 0.999731 # Average percentage of cache occupancy
54 system.cpu.dcache.occ_blocks::0 4094.896939 # Average occupied blocks per context
55 system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses
56 system.cpu.dcache.overall_avg_miss_latency 22431.962140 # average overall miss latency
57 system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency
58 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
59 system.cpu.dcache.overall_hits 606786134 # number of overall hits
60 system.cpu.dcache.overall_miss_latency 9916004000 # number of overall miss cycles
61 system.cpu.dcache.overall_miss_rate 0.000728 # miss rate for overall accesses
62 system.cpu.dcache.overall_misses 442048 # number of overall misses
63 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
64 system.cpu.dcache.overall_mshr_miss_latency 8589860000 # number of overall MSHR miss cycles
65 system.cpu.dcache.overall_mshr_miss_rate 0.000728 # mshr miss rate for overall accesses
66 system.cpu.dcache.overall_mshr_misses 442048 # number of overall MSHR misses
67 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
68 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
69 system.cpu.dcache.replacements 437952 # number of replacements
70 system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
71 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
72 system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use
73 system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks.
74 system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit.
75 system.cpu.dcache.writebacks 396372 # number of writebacks
76 system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses)
77 system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
78 system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
79 system.cpu.icache.ReadReq_hits 1186516018 # number of ReadReq hits
80 system.cpu.icache.ReadReq_miss_latency 40432000 # number of ReadReq miss cycles
81 system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
82 system.cpu.icache.ReadReq_misses 722 # number of ReadReq misses
83 system.cpu.icache.ReadReq_mshr_miss_latency 38266000 # number of ReadReq MSHR miss cycles
84 system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
85 system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses
86 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
87 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
88 system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks.
89 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
90 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
91 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
92 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
93 system.cpu.icache.cache_copies 0 # number of cache copies performed
94 system.cpu.icache.demand_accesses 1186516740 # number of demand (read+write) accesses
95 system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
96 system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
97 system.cpu.icache.demand_hits 1186516018 # number of demand (read+write) hits
98 system.cpu.icache.demand_miss_latency 40432000 # number of demand (read+write) miss cycles
99 system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
100 system.cpu.icache.demand_misses 722 # number of demand (read+write) misses
101 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
102 system.cpu.icache.demand_mshr_miss_latency 38266000 # number of demand (read+write) MSHR miss cycles
103 system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
104 system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses
105 system.cpu.icache.fast_writes 0 # number of fast writes performed
106 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
107 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
108 system.cpu.icache.occ_%::0 0.322357 # Average percentage of cache occupancy
109 system.cpu.icache.occ_blocks::0 660.186297 # Average occupied blocks per context
110 system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses
111 system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
112 system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
113 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
114 system.cpu.icache.overall_hits 1186516018 # number of overall hits
115 system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles
116 system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
117 system.cpu.icache.overall_misses 722 # number of overall misses
118 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
119 system.cpu.icache.overall_mshr_miss_latency 38266000 # number of overall MSHR miss cycles
120 system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
121 system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses
122 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
123 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
124 system.cpu.icache.replacements 4 # number of replacements
125 system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
126 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
127 system.cpu.icache.tagsinuse 660.186297 # Cycle average of tags in use
128 system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks.
129 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
130 system.cpu.icache.writebacks 0 # number of writebacks
131 system.cpu.idle_fraction 0 # Percentage of idle cycles
132 system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses)
133 system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
134 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
135 system.cpu.l2cache.ReadExReq_hits 186469 # number of ReadExReq hits
136 system.cpu.l2cache.ReadExReq_miss_latency 3029156000 # number of ReadExReq miss cycles
137 system.cpu.l2cache.ReadExReq_miss_rate 0.238037 # miss rate for ReadExReq accesses
138 system.cpu.l2cache.ReadExReq_misses 58253 # number of ReadExReq misses
139 system.cpu.l2cache.ReadExReq_mshr_miss_latency 2330120000 # number of ReadExReq MSHR miss cycles
140 system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.238037 # mshr miss rate for ReadExReq accesses
141 system.cpu.l2cache.ReadExReq_mshr_misses 58253 # number of ReadExReq MSHR misses
142 system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses)
143 system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
144 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
145 system.cpu.l2cache.ReadReq_hits 166833 # number of ReadReq hits
146 system.cpu.l2cache.ReadReq_miss_latency 1623180000 # number of ReadReq miss cycles
147 system.cpu.l2cache.ReadReq_miss_rate 0.157613 # miss rate for ReadReq accesses
148 system.cpu.l2cache.ReadReq_misses 31215 # number of ReadReq misses
149 system.cpu.l2cache.ReadReq_mshr_miss_latency 1248600000 # number of ReadReq MSHR miss cycles
150 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157613 # mshr miss rate for ReadReq accesses
151 system.cpu.l2cache.ReadReq_mshr_misses 31215 # number of ReadReq MSHR misses
152 system.cpu.l2cache.Writeback_accesses 396372 # number of Writeback accesses(hits+misses)
153 system.cpu.l2cache.Writeback_hits 396372 # number of Writeback hits
154 system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
155 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
156 system.cpu.l2cache.avg_refs 4.873826 # Average number of references to valid blocks.
157 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
158 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
159 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
160 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
161 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
162 system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses
163 system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
164 system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
165 system.cpu.l2cache.demand_hits 353302 # number of demand (read+write) hits
166 system.cpu.l2cache.demand_miss_latency 4652336000 # number of demand (read+write) miss cycles
167 system.cpu.l2cache.demand_miss_rate 0.202064 # miss rate for demand accesses
168 system.cpu.l2cache.demand_misses 89468 # number of demand (read+write) misses
169 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
170 system.cpu.l2cache.demand_mshr_miss_latency 3578720000 # number of demand (read+write) MSHR miss cycles
171 system.cpu.l2cache.demand_mshr_miss_rate 0.202064 # mshr miss rate for demand accesses
172 system.cpu.l2cache.demand_mshr_misses 89468 # number of demand (read+write) MSHR misses
173 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
174 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
175 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
176 system.cpu.l2cache.occ_%::0 0.057043 # Average percentage of cache occupancy
177 system.cpu.l2cache.occ_%::1 0.494010 # Average percentage of cache occupancy
178 system.cpu.l2cache.occ_blocks::0 1869.199731 # Average occupied blocks per context
179 system.cpu.l2cache.occ_blocks::1 16187.723361 # Average occupied blocks per context
180 system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses
181 system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
182 system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
183 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
184 system.cpu.l2cache.overall_hits 353302 # number of overall hits
185 system.cpu.l2cache.overall_miss_latency 4652336000 # number of overall miss cycles
186 system.cpu.l2cache.overall_miss_rate 0.202064 # miss rate for overall accesses
187 system.cpu.l2cache.overall_misses 89468 # number of overall misses
188 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
189 system.cpu.l2cache.overall_mshr_miss_latency 3578720000 # number of overall MSHR miss cycles
190 system.cpu.l2cache.overall_mshr_miss_rate 0.202064 # mshr miss rate for overall accesses
191 system.cpu.l2cache.overall_mshr_misses 89468 # number of overall MSHR misses
192 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
193 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
194 system.cpu.l2cache.replacements 71208 # number of replacements
195 system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks.
196 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
197 system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use
198 system.cpu.l2cache.total_refs 423014 # Total number of references to valid blocks.
199 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
200 system.cpu.l2cache.writebacks 58007 # number of writebacks
201 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
202 system.cpu.numCycles 3606517174 # number of cpu cycles simulated
203 system.cpu.num_insts 1621493983 # Number of instructions executed
204 system.cpu.num_refs 607228182 # Number of memory references
205 system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
207 ---------- End Simulation Statistics ----------
projects / gem5.git / blob