tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 time_sync_enable=false
   5 time_sync_period=100000000000
   6 time_sync_spin_threshold=100000000
   7
   8 [system]
   9 type=LinuxArmSystem
  10 children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
  11 boot_cpu_frequency=500
  12 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0
  13 init_param=0
  14 kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
  15 load_addr_mask=268435455
  16 machine_type=RealView_PBX
  17 mem_mode=timing
  18 physmem=system.physmem
  19 readfile=tests/halt.sh
  20 symbolfile=
  21 work_begin_ckpt_count=0
  22 work_begin_cpu_id_exit=-1
  23 work_begin_exit_count=0
  24 work_cpus_ckpt_count=0
  25 work_end_ckpt_count=0
  26 work_end_exit_count=0
  27 work_item_id=-1
  28
  29 [system.bridge]
  30 type=Bridge
  31 delay=50000
  32 filter_ranges_a=0:18446744073709551615
  33 filter_ranges_b=0:134217727
  34 nack_delay=4000
  35 req_size_a=16
  36 req_size_b=16
  37 resp_size_a=16
  38 resp_size_b=16
  39 write_ack=false
  40 side_a=system.iobus.port[0]
  41 side_b=system.membus.port[0]
  42
  43 [system.cpu]
  44 type=DerivO3CPU
  45 children=dcache dtb fuPool icache interrupts itb tracer
  46 BTBEntries=4096
  47 BTBTagSize=16
  48 LFSTSize=1024
  49 LQEntries=32
  50 LSQCheckLoads=true
  51 LSQDepCheckShift=4
  52 RASSize=16
  53 SQEntries=32
  54 SSITSize=1024
  55 activity=0
  56 backComSize=5
  57 cachePorts=200
  58 checker=Null
  59 choiceCtrBits=2
  60 choicePredictorSize=8192
  61 clock=500
  62 commitToDecodeDelay=1
  63 commitToFetchDelay=1
  64 commitToIEWDelay=1
  65 commitToRenameDelay=1
  66 commitWidth=8
  67 cpu_id=0
  68 decodeToFetchDelay=1
  69 decodeToRenameDelay=1
  70 decodeWidth=8
  71 defer_registration=false
  72 dispatchWidth=8
  73 do_checkpoint_insts=true
  74 do_quiesce=true
  75 do_statistics_insts=true
  76 dtb=system.cpu.dtb
  77 fetchToDecodeDelay=1
  78 fetchTrapLatency=1
  79 fetchWidth=8
  80 forwardComSize=5
  81 fuPool=system.cpu.fuPool
  82 function_trace=false
  83 function_trace_start=0
  84 globalCtrBits=2
  85 globalHistoryBits=13
  86 globalPredictorSize=8192
  87 iewToCommitDelay=1
  88 iewToDecodeDelay=1
  89 iewToFetchDelay=1
  90 iewToRenameDelay=1
  91 instShiftAmt=2
  92 interrupts=system.cpu.interrupts
  93 issueToExecuteDelay=1
  94 issueWidth=8
  95 itb=system.cpu.itb
  96 localCtrBits=2
  97 localHistoryBits=11
  98 localHistoryTableSize=2048
  99 localPredictorSize=2048
 100 max_insts_all_threads=0
 101 max_insts_any_thread=0
 102 max_loads_all_threads=0
 103 max_loads_any_thread=0
 104 numIQEntries=64
 105 numPhysFloatRegs=256
 106 numPhysIntRegs=256
 107 numROBEntries=192
 108 numRobs=1
 109 numThreads=1
 110 phase=0
 111 predType=tournament
 112 profile=0
 113 progress_interval=0
 114 renameToDecodeDelay=1
 115 renameToFetchDelay=1
 116 renameToIEWDelay=2
 117 renameToROBDelay=1
 118 renameWidth=8
 119 smtCommitPolicy=RoundRobin
 120 smtFetchPolicy=SingleThread
 121 smtIQPolicy=Partitioned
 122 smtIQThreshold=100
 123 smtLSQPolicy=Partitioned
 124 smtLSQThreshold=100
 125 smtNumFetchingThreads=1
 126 smtROBPolicy=Partitioned
 127 smtROBThreshold=100
 128 squashWidth=8
 129 system=system
 130 tracer=system.cpu.tracer
 131 trapLatency=13
 132 wbDepth=1
 133 wbWidth=8
 134 dcache_port=system.cpu.dcache.cpu_side
 135 icache_port=system.cpu.icache.cpu_side
 136
 137 [system.cpu.dcache]
 138 type=BaseCache
 139 addr_range=0:18446744073709551615
 140 assoc=4
 141 block_size=64
 142 forward_snoops=true
 143 hash_delay=1
 144 is_top_level=true
 145 latency=1000
 146 max_miss_count=0
 147 mshrs=4
 148 num_cpus=1
 149 prefetch_data_accesses_only=false
 150 prefetch_degree=1
 151 prefetch_latency=10000
 152 prefetch_on_access=false
 153 prefetch_past_page=false
 154 prefetch_policy=none
 155 prefetch_serial_squash=false
 156 prefetch_use_cpu_id=true
 157 prefetcher_size=100
 158 prioritizeRequests=false
 159 repl=Null
 160 size=32768
 161 subblock_size=0
 162 tgts_per_mshr=20
 163 trace_addr=0
 164 two_queue=false
 165 write_buffers=8
 166 cpu_side=system.cpu.dcache_port
 167 mem_side=system.toL2Bus.port[2]
 168
 169 [system.cpu.dtb]
 170 type=ArmTLB
 171 children=walker
 172 size=64
 173 walker=system.cpu.dtb.walker
 174
 175 [system.cpu.dtb.walker]
 176 type=ArmTableWalker
 177 max_backoff=100000
 178 min_backoff=0
 179 sys=system
 180 port=system.toL2Bus.port[4]
 181
 182 [system.cpu.fuPool]
 183 type=FUPool
 184 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 185 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 186
 187 [system.cpu.fuPool.FUList0]
 188 type=FUDesc
 189 children=opList
 190 count=6
 191 opList=system.cpu.fuPool.FUList0.opList
 192
 193 [system.cpu.fuPool.FUList0.opList]
 194 type=OpDesc
 195 issueLat=1
 196 opClass=IntAlu
 197 opLat=1
 198
 199 [system.cpu.fuPool.FUList1]
 200 type=FUDesc
 201 children=opList0 opList1
 202 count=2
 203 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 204
 205 [system.cpu.fuPool.FUList1.opList0]
 206 type=OpDesc
 207 issueLat=1
 208 opClass=IntMult
 209 opLat=3
 210
 211 [system.cpu.fuPool.FUList1.opList1]
 212 type=OpDesc
 213 issueLat=19
 214 opClass=IntDiv
 215 opLat=20
 216
 217 [system.cpu.fuPool.FUList2]
 218 type=FUDesc
 219 children=opList0 opList1 opList2
 220 count=4
 221 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 222
 223 [system.cpu.fuPool.FUList2.opList0]
 224 type=OpDesc
 225 issueLat=1
 226 opClass=FloatAdd
 227 opLat=2
 228
 229 [system.cpu.fuPool.FUList2.opList1]
 230 type=OpDesc
 231 issueLat=1
 232 opClass=FloatCmp
 233 opLat=2
 234
 235 [system.cpu.fuPool.FUList2.opList2]
 236 type=OpDesc
 237 issueLat=1
 238 opClass=FloatCvt
 239 opLat=2
 240
 241 [system.cpu.fuPool.FUList3]
 242 type=FUDesc
 243 children=opList0 opList1 opList2
 244 count=2
 245 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 246
 247 [system.cpu.fuPool.FUList3.opList0]
 248 type=OpDesc
 249 issueLat=1
 250 opClass=FloatMult
 251 opLat=4
 252
 253 [system.cpu.fuPool.FUList3.opList1]
 254 type=OpDesc
 255 issueLat=12
 256 opClass=FloatDiv
 257 opLat=12
 258
 259 [system.cpu.fuPool.FUList3.opList2]
 260 type=OpDesc
 261 issueLat=24
 262 opClass=FloatSqrt
 263 opLat=24
 264
 265 [system.cpu.fuPool.FUList4]
 266 type=FUDesc
 267 children=opList
 268 count=0
 269 opList=system.cpu.fuPool.FUList4.opList
 270
 271 [system.cpu.fuPool.FUList4.opList]
 272 type=OpDesc
 273 issueLat=1
 274 opClass=MemRead
 275 opLat=1
 276
 277 [system.cpu.fuPool.FUList5]
 278 type=FUDesc
 279 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 280 count=4
 281 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 282
 283 [system.cpu.fuPool.FUList5.opList00]
 284 type=OpDesc
 285 issueLat=1
 286 opClass=SimdAdd
 287 opLat=1
 288
 289 [system.cpu.fuPool.FUList5.opList01]
 290 type=OpDesc
 291 issueLat=1
 292 opClass=SimdAddAcc
 293 opLat=1
 294
 295 [system.cpu.fuPool.FUList5.opList02]
 296 type=OpDesc
 297 issueLat=1
 298 opClass=SimdAlu
 299 opLat=1
 300
 301 [system.cpu.fuPool.FUList5.opList03]
 302 type=OpDesc
 303 issueLat=1
 304 opClass=SimdCmp
 305 opLat=1
 306
 307 [system.cpu.fuPool.FUList5.opList04]
 308 type=OpDesc
 309 issueLat=1
 310 opClass=SimdCvt
 311 opLat=1
 312
 313 [system.cpu.fuPool.FUList5.opList05]
 314 type=OpDesc
 315 issueLat=1
 316 opClass=SimdMisc
 317 opLat=1
 318
 319 [system.cpu.fuPool.FUList5.opList06]
 320 type=OpDesc
 321 issueLat=1
 322 opClass=SimdMult
 323 opLat=1
 324
 325 [system.cpu.fuPool.FUList5.opList07]
 326 type=OpDesc
 327 issueLat=1
 328 opClass=SimdMultAcc
 329 opLat=1
 330
 331 [system.cpu.fuPool.FUList5.opList08]
 332 type=OpDesc
 333 issueLat=1
 334 opClass=SimdShift
 335 opLat=1
 336
 337 [system.cpu.fuPool.FUList5.opList09]
 338 type=OpDesc
 339 issueLat=1
 340 opClass=SimdShiftAcc
 341 opLat=1
 342
 343 [system.cpu.fuPool.FUList5.opList10]
 344 type=OpDesc
 345 issueLat=1
 346 opClass=SimdSqrt
 347 opLat=1
 348
 349 [system.cpu.fuPool.FUList5.opList11]
 350 type=OpDesc
 351 issueLat=1
 352 opClass=SimdFloatAdd
 353 opLat=1
 354
 355 [system.cpu.fuPool.FUList5.opList12]
 356 type=OpDesc
 357 issueLat=1
 358 opClass=SimdFloatAlu
 359 opLat=1
 360
 361 [system.cpu.fuPool.FUList5.opList13]
 362 type=OpDesc
 363 issueLat=1
 364 opClass=SimdFloatCmp
 365 opLat=1
 366
 367 [system.cpu.fuPool.FUList5.opList14]
 368 type=OpDesc
 369 issueLat=1
 370 opClass=SimdFloatCvt
 371 opLat=1
 372
 373 [system.cpu.fuPool.FUList5.opList15]
 374 type=OpDesc
 375 issueLat=1
 376 opClass=SimdFloatDiv
 377 opLat=1
 378
 379 [system.cpu.fuPool.FUList5.opList16]
 380 type=OpDesc
 381 issueLat=1
 382 opClass=SimdFloatMisc
 383 opLat=1
 384
 385 [system.cpu.fuPool.FUList5.opList17]
 386 type=OpDesc
 387 issueLat=1
 388 opClass=SimdFloatMult
 389 opLat=1
 390
 391 [system.cpu.fuPool.FUList5.opList18]
 392 type=OpDesc
 393 issueLat=1
 394 opClass=SimdFloatMultAcc
 395 opLat=1
 396
 397 [system.cpu.fuPool.FUList5.opList19]
 398 type=OpDesc
 399 issueLat=1
 400 opClass=SimdFloatSqrt
 401 opLat=1
 402
 403 [system.cpu.fuPool.FUList6]
 404 type=FUDesc
 405 children=opList
 406 count=0
 407 opList=system.cpu.fuPool.FUList6.opList
 408
 409 [system.cpu.fuPool.FUList6.opList]
 410 type=OpDesc
 411 issueLat=1
 412 opClass=MemWrite
 413 opLat=1
 414
 415 [system.cpu.fuPool.FUList7]
 416 type=FUDesc
 417 children=opList0 opList1
 418 count=4
 419 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 420
 421 [system.cpu.fuPool.FUList7.opList0]
 422 type=OpDesc
 423 issueLat=1
 424 opClass=MemRead
 425 opLat=1
 426
 427 [system.cpu.fuPool.FUList7.opList1]
 428 type=OpDesc
 429 issueLat=1
 430 opClass=MemWrite
 431 opLat=1
 432
 433 [system.cpu.fuPool.FUList8]
 434 type=FUDesc
 435 children=opList
 436 count=1
 437 opList=system.cpu.fuPool.FUList8.opList
 438
 439 [system.cpu.fuPool.FUList8.opList]
 440 type=OpDesc
 441 issueLat=3
 442 opClass=IprAccess
 443 opLat=3
 444
 445 [system.cpu.icache]
 446 type=BaseCache
 447 addr_range=0:18446744073709551615
 448 assoc=1
 449 block_size=64
 450 forward_snoops=true
 451 hash_delay=1
 452 is_top_level=true
 453 latency=1000
 454 max_miss_count=0
 455 mshrs=4
 456 num_cpus=1
 457 prefetch_data_accesses_only=false
 458 prefetch_degree=1
 459 prefetch_latency=10000
 460 prefetch_on_access=false
 461 prefetch_past_page=false
 462 prefetch_policy=none
 463 prefetch_serial_squash=false
 464 prefetch_use_cpu_id=true
 465 prefetcher_size=100
 466 prioritizeRequests=false
 467 repl=Null
 468 size=32768
 469 subblock_size=0
 470 tgts_per_mshr=20
 471 trace_addr=0
 472 two_queue=false
 473 write_buffers=8
 474 cpu_side=system.cpu.icache_port
 475 mem_side=system.toL2Bus.port[1]
 476
 477 [system.cpu.interrupts]
 478 type=ArmInterrupts
 479
 480 [system.cpu.itb]
 481 type=ArmTLB
 482 children=walker
 483 size=64
 484 walker=system.cpu.itb.walker
 485
 486 [system.cpu.itb.walker]
 487 type=ArmTableWalker
 488 max_backoff=100000
 489 min_backoff=0
 490 sys=system
 491 port=system.toL2Bus.port[3]
 492
 493 [system.cpu.tracer]
 494 type=ExeTracer
 495
 496 [system.diskmem]
 497 type=PhysicalMemory
 498 file=/chips/pd/randd/dist/disks/ael-arm.ext2
 499 latency=30000
 500 latency_var=0
 501 null=false
 502 range=134217728:268435455
 503 zero=false
 504 port=system.membus.port[1]
 505
 506 [system.intrctrl]
 507 type=IntrControl
 508 sys=system
 509
 510 [system.iobus]
 511 type=Bus
 512 block_size=64
 513 bus_id=0
 514 clock=1000
 515 header_cycles=1
 516 use_default_range=false
 517 width=64
 518 port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
 519
 520 [system.iocache]
 521 type=BaseCache
 522 addr_range=0:134217727
 523 assoc=8
 524 block_size=64
 525 forward_snoops=false
 526 hash_delay=1
 527 is_top_level=false
 528 latency=50000
 529 max_miss_count=0
 530 mshrs=20
 531 num_cpus=1
 532 prefetch_data_accesses_only=false
 533 prefetch_degree=1
 534 prefetch_latency=500000
 535 prefetch_on_access=false
 536 prefetch_past_page=false
 537 prefetch_policy=none
 538 prefetch_serial_squash=false
 539 prefetch_use_cpu_id=true
 540 prefetcher_size=100
 541 prioritizeRequests=false
 542 repl=Null
 543 size=1024
 544 subblock_size=0
 545 tgts_per_mshr=12
 546 trace_addr=0
 547 two_queue=false
 548 write_buffers=8
 549 cpu_side=system.iobus.port[25]
 550 mem_side=system.membus.port[5]
 551
 552 [system.l2c]
 553 type=BaseCache
 554 addr_range=0:18446744073709551615
 555 assoc=8
 556 block_size=64
 557 forward_snoops=true
 558 hash_delay=1
 559 is_top_level=false
 560 latency=10000
 561 max_miss_count=0
 562 mshrs=92
 563 num_cpus=1
 564 prefetch_data_accesses_only=false
 565 prefetch_degree=1
 566 prefetch_latency=100000
 567 prefetch_on_access=false
 568 prefetch_past_page=false
 569 prefetch_policy=none
 570 prefetch_serial_squash=false
 571 prefetch_use_cpu_id=true
 572 prefetcher_size=100
 573 prioritizeRequests=false
 574 repl=Null
 575 size=4194304
 576 subblock_size=0
 577 tgts_per_mshr=16
 578 trace_addr=0
 579 two_queue=false
 580 write_buffers=8
 581 cpu_side=system.toL2Bus.port[0]
 582 mem_side=system.membus.port[6]
 583
 584 [system.membus]
 585 type=Bus
 586 children=badaddr_responder
 587 block_size=64
 588 bus_id=1
 589 clock=1000
 590 header_cycles=1
 591 use_default_range=false
 592 width=64
 593 default=system.membus.badaddr_responder.pio
 594 port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side
 595
 596 [system.membus.badaddr_responder]
 597 type=IsaFake
 598 pio_addr=0
 599 pio_latency=1000
 600 pio_size=8
 601 platform=system.realview
 602 ret_bad_addr=true
 603 ret_data16=65535
 604 ret_data32=4294967295
 605 ret_data64=18446744073709551615
 606 ret_data8=255
 607 system=system
 608 update_data=false
 609 warn_access=warn
 610 pio=system.membus.default
 611
 612 [system.physmem]
 613 type=PhysicalMemory
 614 file=
 615 latency=30000
 616 latency_var=0
 617 null=false
 618 range=0:134217727
 619 zero=true
 620 port=system.membus.port[2]
 621
 622 [system.realview]
 623 type=RealView
 624 children=aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
 625 intrctrl=system.intrctrl
 626 system=system
 627
 628 [system.realview.aaci_fake]
 629 type=AmbaFake
 630 amba_id=0
 631 ignore_access=false
 632 pio_addr=268451840
 633 pio_latency=1000
 634 platform=system.realview
 635 system=system
 636 pio=system.iobus.port[21]
 637
 638 [system.realview.cf_ctrl]
 639 type=IdeController
 640 BAR0=402653184
 641 BAR0LegacyIO=true
 642 BAR0Size=16
 643 BAR1=402653440
 644 BAR1LegacyIO=true
 645 BAR1Size=1
 646 BAR2=1
 647 BAR2LegacyIO=false
 648 BAR2Size=8
 649 BAR3=1
 650 BAR3LegacyIO=false
 651 BAR3Size=4
 652 BAR4=1
 653 BAR4LegacyIO=false
 654 BAR4Size=16
 655 BAR5=1
 656 BAR5LegacyIO=false
 657 BAR5Size=0
 658 BIST=0
 659 CacheLineSize=0
 660 CardbusCIS=0
 661 ClassCode=1
 662 Command=1
 663 DeviceID=28945
 664 ExpansionROM=0
 665 HeaderType=0
 666 InterruptLine=31
 667 InterruptPin=1
 668 LatencyTimer=0
 669 MaximumLatency=0
 670 MinimumGrant=0
 671 ProgIF=133
 672 Revision=0
 673 Status=640
 674 SubClassCode=1
 675 SubsystemID=0
 676 SubsystemVendorID=0
 677 VendorID=32902
 678 config_latency=20000
 679 ctrl_offset=2
 680 disks=
 681 io_shift=1
 682 max_backoff_delay=10000000
 683 min_backoff_delay=4000
 684 pci_bus=0
 685 pci_dev=0
 686 pci_func=0
 687 pio_latency=1000
 688 platform=system.realview
 689 system=system
 690 config=system.iobus.port[26]
 691 dma=system.iobus.port[27]
 692 pio=system.iobus.port[8]
 693
 694 [system.realview.clcd]
 695 type=Pl111
 696 amba_id=1315089
 697 clock=41667
 698 gic=system.realview.gic
 699 int_num=55
 700 max_backoff_delay=10000000
 701 min_backoff_delay=4000
 702 pio_addr=268566528
 703 pio_latency=10000
 704 platform=system.realview
 705 system=system
 706 vnc=system.vncserver
 707 dma=system.iobus.port[28]
 708 pio=system.iobus.port[5]
 709
 710 [system.realview.dmac_fake]
 711 type=AmbaFake
 712 amba_id=0
 713 ignore_access=false
 714 pio_addr=268632064
 715 pio_latency=1000
 716 platform=system.realview
 717 system=system
 718 pio=system.iobus.port[9]
 719
 720 [system.realview.flash_fake]
 721 type=IsaFake
 722 pio_addr=1073741824
 723 pio_latency=1000
 724 pio_size=67108864
 725 platform=system.realview
 726 ret_bad_addr=false
 727 ret_data16=65535
 728 ret_data32=4294967295
 729 ret_data64=18446744073709551615
 730 ret_data8=255
 731 system=system
 732 update_data=false
 733 warn_access=
 734 pio=system.iobus.port[24]
 735
 736 [system.realview.gic]
 737 type=Gic
 738 cpu_addr=520093952
 739 cpu_pio_delay=10000
 740 dist_addr=520097792
 741 dist_pio_delay=10000
 742 it_lines=128
 743 platform=system.realview
 744 system=system
 745 pio=system.membus.port[3]
 746
 747 [system.realview.gpio0_fake]
 748 type=AmbaFake
 749 amba_id=0
 750 ignore_access=false
 751 pio_addr=268513280
 752 pio_latency=1000
 753 platform=system.realview
 754 system=system
 755 pio=system.iobus.port[16]
 756
 757 [system.realview.gpio1_fake]
 758 type=AmbaFake
 759 amba_id=0
 760 ignore_access=false
 761 pio_addr=268517376
 762 pio_latency=1000
 763 platform=system.realview
 764 system=system
 765 pio=system.iobus.port[17]
 766
 767 [system.realview.gpio2_fake]
 768 type=AmbaFake
 769 amba_id=0
 770 ignore_access=false
 771 pio_addr=268521472
 772 pio_latency=1000
 773 platform=system.realview
 774 system=system
 775 pio=system.iobus.port[18]
 776
 777 [system.realview.kmi0]
 778 type=Pl050
 779 amba_id=1314896
 780 gic=system.realview.gic
 781 int_delay=1000000
 782 int_num=52
 783 is_mouse=false
 784 pio_addr=268460032
 785 pio_latency=1000
 786 platform=system.realview
 787 system=system
 788 vnc=system.vncserver
 789 pio=system.iobus.port[6]
 790
 791 [system.realview.kmi1]
 792 type=Pl050
 793 amba_id=1314896
 794 gic=system.realview.gic
 795 int_delay=1000000
 796 int_num=53
 797 is_mouse=true
 798 pio_addr=268464128
 799 pio_latency=1000
 800 platform=system.realview
 801 system=system
 802 vnc=system.vncserver
 803 pio=system.iobus.port[7]
 804
 805 [system.realview.l2x0_fake]
 806 type=IsaFake
 807 pio_addr=520101888
 808 pio_latency=1000
 809 pio_size=4095
 810 platform=system.realview
 811 ret_bad_addr=false
 812 ret_data16=65535
 813 ret_data32=4294967295
 814 ret_data64=18446744073709551615
 815 ret_data8=255
 816 system=system
 817 update_data=false
 818 warn_access=
 819 pio=system.membus.port[4]
 820
 821 [system.realview.mmc_fake]
 822 type=AmbaFake
 823 amba_id=0
 824 ignore_access=false
 825 pio_addr=268455936
 826 pio_latency=1000
 827 platform=system.realview
 828 system=system
 829 pio=system.iobus.port[22]
 830
 831 [system.realview.realview_io]
 832 type=RealViewCtrl
 833 pio_addr=268435456
 834 pio_latency=1000
 835 platform=system.realview
 836 proc_id=201326592
 837 system=system
 838 pio=system.iobus.port[2]
 839
 840 [system.realview.rtc_fake]
 841 type=AmbaFake
 842 amba_id=266289
 843 ignore_access=false
 844 pio_addr=268529664
 845 pio_latency=1000
 846 platform=system.realview
 847 system=system
 848 pio=system.iobus.port[23]
 849
 850 [system.realview.sci_fake]
 851 type=AmbaFake
 852 amba_id=0
 853 ignore_access=false
 854 pio_addr=268492800
 855 pio_latency=1000
 856 platform=system.realview
 857 system=system
 858 pio=system.iobus.port[20]
 859
 860 [system.realview.smc_fake]
 861 type=AmbaFake
 862 amba_id=0
 863 ignore_access=false
 864 pio_addr=269357056
 865 pio_latency=1000
 866 platform=system.realview
 867 system=system
 868 pio=system.iobus.port[13]
 869
 870 [system.realview.sp810_fake]
 871 type=AmbaFake
 872 amba_id=0
 873 ignore_access=true
 874 pio_addr=268439552
 875 pio_latency=1000
 876 platform=system.realview
 877 system=system
 878 pio=system.iobus.port[14]
 879
 880 [system.realview.ssp_fake]
 881 type=AmbaFake
 882 amba_id=0
 883 ignore_access=false
 884 pio_addr=268488704
 885 pio_latency=1000
 886 platform=system.realview
 887 system=system
 888 pio=system.iobus.port[19]
 889
 890 [system.realview.timer0]
 891 type=Sp804
 892 amba_id=1316868
 893 clock0=1000000
 894 clock1=1000000
 895 gic=system.realview.gic
 896 int_num0=36
 897 int_num1=36
 898 pio_addr=268505088
 899 pio_latency=1000
 900 platform=system.realview
 901 system=system
 902 pio=system.iobus.port[3]
 903
 904 [system.realview.timer1]
 905 type=Sp804
 906 amba_id=1316868
 907 clock0=1000000
 908 clock1=1000000
 909 gic=system.realview.gic
 910 int_num0=37
 911 int_num1=37
 912 pio_addr=268509184
 913 pio_latency=1000
 914 platform=system.realview
 915 system=system
 916 pio=system.iobus.port[4]
 917
 918 [system.realview.uart]
 919 type=Pl011
 920 end_on_eot=false
 921 gic=system.realview.gic
 922 int_delay=100000
 923 int_num=44
 924 pio_addr=268472320
 925 pio_latency=1000
 926 platform=system.realview
 927 system=system
 928 terminal=system.terminal
 929 pio=system.iobus.port[1]
 930
 931 [system.realview.uart1_fake]
 932 type=AmbaFake
 933 amba_id=0
 934 ignore_access=false
 935 pio_addr=268476416
 936 pio_latency=1000
 937 platform=system.realview
 938 system=system
 939 pio=system.iobus.port[10]
 940
 941 [system.realview.uart2_fake]
 942 type=AmbaFake
 943 amba_id=0
 944 ignore_access=false
 945 pio_addr=268480512
 946 pio_latency=1000
 947 platform=system.realview
 948 system=system
 949 pio=system.iobus.port[11]
 950
 951 [system.realview.uart3_fake]
 952 type=AmbaFake
 953 amba_id=0
 954 ignore_access=false
 955 pio_addr=268484608
 956 pio_latency=1000
 957 platform=system.realview
 958 system=system
 959 pio=system.iobus.port[12]
 960
 961 [system.realview.watchdog_fake]
 962 type=AmbaFake
 963 amba_id=0
 964 ignore_access=false
 965 pio_addr=268500992
 966 pio_latency=1000
 967 platform=system.realview
 968 system=system
 969 pio=system.iobus.port[15]
 970
 971 [system.terminal]
 972 type=Terminal
 973 intr_control=system.intrctrl
 974 number=0
 975 output=true
 976 port=3456
 977
 978 [system.toL2Bus]
 979 type=Bus
 980 block_size=64
 981 bus_id=0
 982 clock=1000
 983 header_cycles=1
 984 use_default_range=false
 985 width=64
 986 port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 987
 988 [system.vncserver]
 989 type=VncServer
 990 number=0
 991 port=5900
 992