2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.503566 # Number of seconds simulated
4 sim_ticks 2503566110500 # Number of ticks simulated
5 sim_freq 1000000000000 # Frequency of simulated ticks
6 host_inst_rate 84156 # Simulator instruction rate (inst/s)
7 host_tick_rate 2743719152 # Simulator tick rate (ticks/s)
8 host_mem_usage 380536 # Number of bytes of host memory used
9 host_seconds 912.47 # Real time elapsed on the host
10 sim_insts 76790007 # Number of instructions simulated
11 system.l2c.replacements 119509 # number of replacements
12 system.l2c.tagsinuse 25929.897253 # Cycle average of tags in use
13 system.l2c.total_refs 1795434 # Total number of references to valid blocks.
14 system.l2c.sampled_refs 150343 # Sample count of references to valid blocks.
15 system.l2c.avg_refs 11.942252 # Average number of references to valid blocks.
16 system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
17 system.l2c.occ_blocks::0 11551.232252 # Average occupied blocks per context
18 system.l2c.occ_blocks::1 14378.665001 # Average occupied blocks per context
19 system.l2c.occ_percent::0 0.176258 # Average percentage of cache occupancy
20 system.l2c.occ_percent::1 0.219401 # Average percentage of cache occupancy
21 system.l2c.ReadReq_hits::0 1350292 # number of ReadReq hits
22 system.l2c.ReadReq_hits::1 153003 # number of ReadReq hits
23 system.l2c.ReadReq_hits::total 1503295 # number of ReadReq hits
24 system.l2c.Writeback_hits::0 629881 # number of Writeback hits
25 system.l2c.Writeback_hits::total 629881 # number of Writeback hits
26 system.l2c.UpgradeReq_hits::0 38 # number of UpgradeReq hits
27 system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits
28 system.l2c.SCUpgradeReq_hits::0 16 # number of SCUpgradeReq hits
29 system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits
30 system.l2c.ReadExReq_hits::0 105934 # number of ReadExReq hits
31 system.l2c.ReadExReq_hits::total 105934 # number of ReadExReq hits
32 system.l2c.demand_hits::0 1456226 # number of demand (read+write) hits
33 system.l2c.demand_hits::1 153003 # number of demand (read+write) hits
34 system.l2c.demand_hits::total 1609229 # number of demand (read+write) hits
35 system.l2c.overall_hits::0 1456226 # number of overall hits
36 system.l2c.overall_hits::1 153003 # number of overall hits
37 system.l2c.overall_hits::total 1609229 # number of overall hits
38 system.l2c.ReadReq_misses::0 36080 # number of ReadReq misses
39 system.l2c.ReadReq_misses::1 144 # number of ReadReq misses
40 system.l2c.ReadReq_misses::total 36224 # number of ReadReq misses
41 system.l2c.UpgradeReq_misses::0 3255 # number of UpgradeReq misses
42 system.l2c.UpgradeReq_misses::total 3255 # number of UpgradeReq misses
43 system.l2c.SCUpgradeReq_misses::0 2 # number of SCUpgradeReq misses
44 system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
45 system.l2c.ReadExReq_misses::0 140433 # number of ReadExReq misses
46 system.l2c.ReadExReq_misses::total 140433 # number of ReadExReq misses
47 system.l2c.demand_misses::0 176513 # number of demand (read+write) misses
48 system.l2c.demand_misses::1 144 # number of demand (read+write) misses
49 system.l2c.demand_misses::total 176657 # number of demand (read+write) misses
50 system.l2c.overall_misses::0 176513 # number of overall misses
51 system.l2c.overall_misses::1 144 # number of overall misses
52 system.l2c.overall_misses::total 176657 # number of overall misses
53 system.l2c.ReadReq_miss_latency 1894696500 # number of ReadReq miss cycles
54 system.l2c.UpgradeReq_miss_latency 1006500 # number of UpgradeReq miss cycles
55 system.l2c.ReadExReq_miss_latency 7384268500 # number of ReadExReq miss cycles
56 system.l2c.demand_miss_latency 9278965000 # number of demand (read+write) miss cycles
57 system.l2c.overall_miss_latency 9278965000 # number of overall miss cycles
58 system.l2c.ReadReq_accesses::0 1386372 # number of ReadReq accesses(hits+misses)
59 system.l2c.ReadReq_accesses::1 153147 # number of ReadReq accesses(hits+misses)
60 system.l2c.ReadReq_accesses::total 1539519 # number of ReadReq accesses(hits+misses)
61 system.l2c.Writeback_accesses::0 629881 # number of Writeback accesses(hits+misses)
62 system.l2c.Writeback_accesses::total 629881 # number of Writeback accesses(hits+misses)
63 system.l2c.UpgradeReq_accesses::0 3293 # number of UpgradeReq accesses(hits+misses)
64 system.l2c.UpgradeReq_accesses::total 3293 # number of UpgradeReq accesses(hits+misses)
65 system.l2c.SCUpgradeReq_accesses::0 18 # number of SCUpgradeReq accesses(hits+misses)
66 system.l2c.SCUpgradeReq_accesses::total 18 # number of SCUpgradeReq accesses(hits+misses)
67 system.l2c.ReadExReq_accesses::0 246367 # number of ReadExReq accesses(hits+misses)
68 system.l2c.ReadExReq_accesses::total 246367 # number of ReadExReq accesses(hits+misses)
69 system.l2c.demand_accesses::0 1632739 # number of demand (read+write) accesses
70 system.l2c.demand_accesses::1 153147 # number of demand (read+write) accesses
71 system.l2c.demand_accesses::total 1785886 # number of demand (read+write) accesses
72 system.l2c.overall_accesses::0 1632739 # number of overall (read+write) accesses
73 system.l2c.overall_accesses::1 153147 # number of overall (read+write) accesses
74 system.l2c.overall_accesses::total 1785886 # number of overall (read+write) accesses
75 system.l2c.ReadReq_miss_rate::0 0.026025 # miss rate for ReadReq accesses
76 system.l2c.ReadReq_miss_rate::1 0.000940 # miss rate for ReadReq accesses
77 system.l2c.ReadReq_miss_rate::total 0.026965 # miss rate for ReadReq accesses
78 system.l2c.UpgradeReq_miss_rate::0 0.988460 # miss rate for UpgradeReq accesses
79 system.l2c.SCUpgradeReq_miss_rate::0 0.111111 # miss rate for SCUpgradeReq accesses
80 system.l2c.ReadExReq_miss_rate::0 0.570015 # miss rate for ReadExReq accesses
81 system.l2c.demand_miss_rate::0 0.108109 # miss rate for demand accesses
82 system.l2c.demand_miss_rate::1 0.000940 # miss rate for demand accesses
83 system.l2c.demand_miss_rate::total 0.109049 # miss rate for demand accesses
84 system.l2c.overall_miss_rate::0 0.108109 # miss rate for overall accesses
85 system.l2c.overall_miss_rate::1 0.000940 # miss rate for overall accesses
86 system.l2c.overall_miss_rate::total 0.109049 # miss rate for overall accesses
87 system.l2c.ReadReq_avg_miss_latency::0 52513.761086 # average ReadReq miss latency
88 system.l2c.ReadReq_avg_miss_latency::1 13157614.583333 # average ReadReq miss latency
89 system.l2c.ReadReq_avg_miss_latency::total 13210128.344420 # average ReadReq miss latency
90 system.l2c.UpgradeReq_avg_miss_latency::0 309.216590 # average UpgradeReq miss latency
91 system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
92 system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
93 system.l2c.ReadExReq_avg_miss_latency::0 52582.145934 # average ReadExReq miss latency
94 system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
95 system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
96 system.l2c.demand_avg_miss_latency::0 52568.167784 # average overall miss latency
97 system.l2c.demand_avg_miss_latency::1 64437256.944444 # average overall miss latency
98 system.l2c.demand_avg_miss_latency::total 64489825.112228 # average overall miss latency
99 system.l2c.overall_avg_miss_latency::0 52568.167784 # average overall miss latency
100 system.l2c.overall_avg_miss_latency::1 64437256.944444 # average overall miss latency
101 system.l2c.overall_avg_miss_latency::total 64489825.112228 # average overall miss latency
102 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
103 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
104 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
105 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
106 system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
107 system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
108 system.l2c.fast_writes 0 # number of fast writes performed
109 system.l2c.cache_copies 0 # number of cache copies performed
110 system.l2c.writebacks 102655 # number of writebacks
111 system.l2c.ReadReq_mshr_hits 94 # number of ReadReq MSHR hits
112 system.l2c.demand_mshr_hits 94 # number of demand (read+write) MSHR hits
113 system.l2c.overall_mshr_hits 94 # number of overall MSHR hits
114 system.l2c.ReadReq_mshr_misses 36130 # number of ReadReq MSHR misses
115 system.l2c.UpgradeReq_mshr_misses 3255 # number of UpgradeReq MSHR misses
116 system.l2c.SCUpgradeReq_mshr_misses 2 # number of SCUpgradeReq MSHR misses
117 system.l2c.ReadExReq_mshr_misses 140433 # number of ReadExReq MSHR misses
118 system.l2c.demand_mshr_misses 176563 # number of demand (read+write) MSHR misses
119 system.l2c.overall_mshr_misses 176563 # number of overall MSHR misses
120 system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
121 system.l2c.ReadReq_mshr_miss_latency 1449837500 # number of ReadReq MSHR miss cycles
122 system.l2c.UpgradeReq_mshr_miss_latency 131527500 # number of UpgradeReq MSHR miss cycles
123 system.l2c.SCUpgradeReq_mshr_miss_latency 80000 # number of SCUpgradeReq MSHR miss cycles
124 system.l2c.ReadExReq_mshr_miss_latency 5640075000 # number of ReadExReq MSHR miss cycles
125 system.l2c.demand_mshr_miss_latency 7089912500 # number of demand (read+write) MSHR miss cycles
126 system.l2c.overall_mshr_miss_latency 7089912500 # number of overall MSHR miss cycles
127 system.l2c.ReadReq_mshr_uncacheable_latency 131769527500 # number of ReadReq MSHR uncacheable cycles
128 system.l2c.WriteReq_mshr_uncacheable_latency 32342636570 # number of WriteReq MSHR uncacheable cycles
129 system.l2c.overall_mshr_uncacheable_latency 164112164070 # number of overall MSHR uncacheable cycles
130 system.l2c.ReadReq_mshr_miss_rate::0 0.026061 # mshr miss rate for ReadReq accesses
131 system.l2c.ReadReq_mshr_miss_rate::1 0.235917 # mshr miss rate for ReadReq accesses
132 system.l2c.ReadReq_mshr_miss_rate::total 0.261978 # mshr miss rate for ReadReq accesses
133 system.l2c.UpgradeReq_mshr_miss_rate::0 0.988460 # mshr miss rate for UpgradeReq accesses
134 system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
135 system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
136 system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.111111 # mshr miss rate for SCUpgradeReq accesses
137 system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses
138 system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
139 system.l2c.ReadExReq_mshr_miss_rate::0 0.570015 # mshr miss rate for ReadExReq accesses
140 system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
141 system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
142 system.l2c.demand_mshr_miss_rate::0 0.108139 # mshr miss rate for demand accesses
143 system.l2c.demand_mshr_miss_rate::1 1.152899 # mshr miss rate for demand accesses
144 system.l2c.demand_mshr_miss_rate::total 1.261038 # mshr miss rate for demand accesses
145 system.l2c.overall_mshr_miss_rate::0 0.108139 # mshr miss rate for overall accesses
146 system.l2c.overall_mshr_miss_rate::1 1.152899 # mshr miss rate for overall accesses
147 system.l2c.overall_mshr_miss_rate::total 1.261038 # mshr miss rate for overall accesses
148 system.l2c.ReadReq_avg_mshr_miss_latency 40128.355937 # average ReadReq mshr miss latency
149 system.l2c.UpgradeReq_avg_mshr_miss_latency 40407.834101 # average UpgradeReq mshr miss latency
150 system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency
151 system.l2c.ReadExReq_avg_mshr_miss_latency 40162.034565 # average ReadExReq mshr miss latency
152 system.l2c.demand_avg_mshr_miss_latency 40155.142923 # average overall mshr miss latency
153 system.l2c.overall_avg_mshr_miss_latency 40155.142923 # average overall mshr miss latency
154 system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
155 system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
156 system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
157 system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
158 system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
159 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
160 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
161 system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
162 system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
163 system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
164 system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
165 system.cf0.dma_write_txs 0 # Number of DMA write transactions.
166 system.cpu.dtb.inst_hits 0 # ITB inst hits
167 system.cpu.dtb.inst_misses 0 # ITB inst misses
168 system.cpu.dtb.read_hits 52217329 # DTB read hits
169 system.cpu.dtb.read_misses 90306 # DTB read misses
170 system.cpu.dtb.write_hits 11974176 # DTB write hits
171 system.cpu.dtb.write_misses 25588 # DTB write misses
172 system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
173 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
174 system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
175 system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
176 system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB
177 system.cpu.dtb.align_faults 5563 # Number of TLB faults due to alignment restrictions
178 system.cpu.dtb.prefetch_faults 685 # Number of TLB faults due to prefetch
179 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
180 system.cpu.dtb.perms_faults 2233 # Number of TLB faults due to permissions restrictions
181 system.cpu.dtb.read_accesses 52307635 # DTB read accesses
182 system.cpu.dtb.write_accesses 11999764 # DTB write accesses
183 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
184 system.cpu.dtb.hits 64191505 # DTB hits
185 system.cpu.dtb.misses 115894 # DTB misses
186 system.cpu.dtb.accesses 64307399 # DTB accesses
187 system.cpu.itb.inst_hits 14124795 # ITB inst hits
188 system.cpu.itb.inst_misses 9853 # ITB inst misses
189 system.cpu.itb.read_hits 0 # DTB read hits
190 system.cpu.itb.read_misses 0 # DTB read misses
191 system.cpu.itb.write_hits 0 # DTB write hits
192 system.cpu.itb.write_misses 0 # DTB write misses
193 system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
194 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
195 system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
196 system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
197 system.cpu.itb.flush_entries 2606 # Number of entries that have been flushed from TLB
198 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
199 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
200 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
201 system.cpu.itb.perms_faults 7868 # Number of TLB faults due to permissions restrictions
202 system.cpu.itb.read_accesses 0 # DTB read accesses
203 system.cpu.itb.write_accesses 0 # DTB write accesses
204 system.cpu.itb.inst_accesses 14134648 # ITB inst accesses
205 system.cpu.itb.hits 14124795 # DTB hits
206 system.cpu.itb.misses 9853 # DTB misses
207 system.cpu.itb.accesses 14134648 # DTB accesses
208 system.cpu.numCycles 415912091 # number of cpu cycles simulated
209 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
210 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
211 system.cpu.BPredUnit.lookups 16206323 # Number of BP lookups
212 system.cpu.BPredUnit.condPredicted 12554772 # Number of conditional branches predicted
213 system.cpu.BPredUnit.condIncorrect 1108177 # Number of conditional branches incorrect
214 system.cpu.BPredUnit.BTBLookups 13916811 # Number of BTB lookups
215 system.cpu.BPredUnit.BTBHits 10226428 # Number of BTB hits
216 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
217 system.cpu.BPredUnit.usedRAS 1423283 # Number of times the RAS was used to get a target.
218 system.cpu.BPredUnit.RASInCorrect 227054 # Number of incorrect RAS predictions.
219 system.cpu.fetch.icacheStallCycles 32931583 # Number of cycles fetch is stalled on an Icache miss
220 system.cpu.fetch.Insts 104747250 # Number of instructions fetch has processed
221 system.cpu.fetch.Branches 16206323 # Number of branches that fetch encountered
222 system.cpu.fetch.predictedBranches 11649711 # Number of branches that fetch has predicted taken
223 system.cpu.fetch.Cycles 24460631 # Number of cycles fetch has run and was not squashing or blocked
224 system.cpu.fetch.SquashCycles 7066944 # Number of cycles fetch has spent squashing
225 system.cpu.fetch.TlbCycles 130925 # Number of cycles fetch has spent waiting for tlb
226 system.cpu.fetch.BlockedCycles 92852979 # Number of cycles fetch has spent blocked
227 system.cpu.fetch.MiscStallCycles 1378 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
228 system.cpu.fetch.PendingTrapStallCycles 144764 # Number of stall cycles due to pending traps
229 system.cpu.fetch.PendingQuiesceStallCycles 217141 # Number of stall cycles due to pending quiesce instructions
230 system.cpu.fetch.IcacheWaitRetryStallCycles 360 # Number of stall cycles due to full MSHR
231 system.cpu.fetch.CacheLines 14116150 # Number of cache lines fetched
232 system.cpu.fetch.IcacheSquashes 1044696 # Number of outstanding Icache misses that were squashed
233 system.cpu.fetch.ItlbSquashes 4826 # Number of outstanding ITLB misses that were squashed
234 system.cpu.fetch.rateDist::samples 155542524 # Number of instructions fetched each cycle (Total)
235 system.cpu.fetch.rateDist::mean 0.838034 # Number of instructions fetched each cycle (Total)
236 system.cpu.fetch.rateDist::stdev 2.183637 # Number of instructions fetched each cycle (Total)
237 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
238 system.cpu.fetch.rateDist::0 131107701 84.29% 84.29% # Number of instructions fetched each cycle (Total)
239 system.cpu.fetch.rateDist::1 1736645 1.12% 85.41% # Number of instructions fetched each cycle (Total)
240 system.cpu.fetch.rateDist::2 2606210 1.68% 87.08% # Number of instructions fetched each cycle (Total)
241 system.cpu.fetch.rateDist::3 3650547 2.35% 89.43% # Number of instructions fetched each cycle (Total)
242 system.cpu.fetch.rateDist::4 2167045 1.39% 90.82% # Number of instructions fetched each cycle (Total)
243 system.cpu.fetch.rateDist::5 1435515 0.92% 91.75% # Number of instructions fetched each cycle (Total)
244 system.cpu.fetch.rateDist::6 2626627 1.69% 93.43% # Number of instructions fetched each cycle (Total)
245 system.cpu.fetch.rateDist::7 854151 0.55% 93.98% # Number of instructions fetched each cycle (Total)
246 system.cpu.fetch.rateDist::8 9358083 6.02% 100.00% # Number of instructions fetched each cycle (Total)
247 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
248 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
249 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
250 system.cpu.fetch.rateDist::total 155542524 # Number of instructions fetched each cycle (Total)
251 system.cpu.fetch.branchRate 0.038966 # Number of branch fetches per cycle
252 system.cpu.fetch.rate 0.251849 # Number of inst fetches per cycle
253 system.cpu.decode.IdleCycles 35137982 # Number of cycles decode is idle
254 system.cpu.decode.BlockedCycles 92713675 # Number of cycles decode is blocked
255 system.cpu.decode.RunCycles 21969277 # Number of cycles decode is running
256 system.cpu.decode.UnblockCycles 1093477 # Number of cycles decode is unblocking
257 system.cpu.decode.SquashCycles 4628113 # Number of cycles decode is squashing
258 system.cpu.decode.BranchResolved 2313056 # Number of times decode resolved a branch
259 system.cpu.decode.BranchMispred 177631 # Number of times decode detected a branch misprediction
260 system.cpu.decode.DecodedInsts 122001156 # Number of instructions handled by decode
261 system.cpu.decode.SquashedInsts 574106 # Number of squashed instructions handled by decode
262 system.cpu.rename.SquashCycles 4628113 # Number of cycles rename is squashing
263 system.cpu.rename.IdleCycles 37294552 # Number of cycles rename is idle
264 system.cpu.rename.BlockCycles 36817406 # Number of cycles rename is blocking
265 system.cpu.rename.serializeStallCycles 49929047 # count of cycles rename stalled for serializing inst
266 system.cpu.rename.RunCycles 20901153 # Number of cycles rename is running
267 system.cpu.rename.UnblockCycles 5972253 # Number of cycles rename is unblocking
268 system.cpu.rename.RenamedInsts 113826701 # Number of instructions processed by rename
269 system.cpu.rename.ROBFullEvents 4400 # Number of times rename has blocked due to ROB full
270 system.cpu.rename.IQFullEvents 914485 # Number of times rename has blocked due to IQ full
271 system.cpu.rename.LSQFullEvents 3979731 # Number of times rename has blocked due to LSQ full
272 system.cpu.rename.FullRegisterEvents 42252 # Number of times there has been no free registers
273 system.cpu.rename.RenamedOperands 118358542 # Number of destination operands rename has renamed
274 system.cpu.rename.RenameLookups 523323093 # Number of register rename lookups that rename has made
275 system.cpu.rename.int_rename_lookups 523225639 # Number of integer rename lookups
276 system.cpu.rename.fp_rename_lookups 97454 # Number of floating rename lookups
277 system.cpu.rename.CommittedMaps 77492718 # Number of HB maps that are committed
278 system.cpu.rename.UndoneMaps 40865823 # Number of HB maps that are undone due to squashing
279 system.cpu.rename.serializingInsts 1204637 # count of serializing insts renamed
280 system.cpu.rename.tempSerializingInsts 1098724 # count of temporary serializing insts renamed
281 system.cpu.rename.skidInsts 12304657 # count of insts added to the skid buffer
282 system.cpu.memDep0.insertedLoads 21982315 # Number of loads inserted to the mem dependence unit.
283 system.cpu.memDep0.insertedStores 14168730 # Number of stores inserted to the mem dependence unit.
284 system.cpu.memDep0.conflictingLoads 1896802 # Number of conflicting loads.
285 system.cpu.memDep0.conflictingStores 2281380 # Number of conflicting stores.
286 system.cpu.iq.iqInstsAdded 102860212 # Number of instructions added to the IQ (excludes non-spec)
287 system.cpu.iq.iqNonSpecInstsAdded 1874615 # Number of non-speculative instructions added to the IQ
288 system.cpu.iq.iqInstsIssued 126873317 # Number of instructions issued
289 system.cpu.iq.iqSquashedInstsIssued 252471 # Number of squashed instructions issued
290 system.cpu.iq.iqSquashedInstsExamined 26973483 # Number of squashed instructions iterated over during squash; mainly for profiling
291 system.cpu.iq.iqSquashedOperandsExamined 72956952 # Number of squashed operands that are examined and possibly removed from graph
292 system.cpu.iq.iqSquashedNonSpecRemoved 374922 # Number of squashed non-spec instructions that were removed
293 system.cpu.iq.issued_per_cycle::samples 155542524 # Number of insts issued each cycle
294 system.cpu.iq.issued_per_cycle::mean 0.815683 # Number of insts issued each cycle
295 system.cpu.iq.issued_per_cycle::stdev 1.505358 # Number of insts issued each cycle
296 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
297 system.cpu.iq.issued_per_cycle::0 108919716 70.03% 70.03% # Number of insts issued each cycle
298 system.cpu.iq.issued_per_cycle::1 15115277 9.72% 79.74% # Number of insts issued each cycle
299 system.cpu.iq.issued_per_cycle::2 7538109 4.85% 84.59% # Number of insts issued each cycle
300 system.cpu.iq.issued_per_cycle::3 6517896 4.19% 88.78% # Number of insts issued each cycle
301 system.cpu.iq.issued_per_cycle::4 12766128 8.21% 96.99% # Number of insts issued each cycle
302 system.cpu.iq.issued_per_cycle::5 2735747 1.76% 98.75% # Number of insts issued each cycle
303 system.cpu.iq.issued_per_cycle::6 1395145 0.90% 99.64% # Number of insts issued each cycle
304 system.cpu.iq.issued_per_cycle::7 422031 0.27% 99.91% # Number of insts issued each cycle
305 system.cpu.iq.issued_per_cycle::8 132475 0.09% 100.00% # Number of insts issued each cycle
306 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
307 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
308 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
309 system.cpu.iq.issued_per_cycle::total 155542524 # Number of insts issued each cycle
310 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
311 system.cpu.iq.fu_full::IntAlu 45891 0.52% 0.52% # attempts to use FU when none available
312 system.cpu.iq.fu_full::IntMult 6 0.00% 0.52% # attempts to use FU when none available
313 system.cpu.iq.fu_full::IntDiv 0 0.00% 0.52% # attempts to use FU when none available
314 system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.52% # attempts to use FU when none available
315 system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.52% # attempts to use FU when none available
316 system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.52% # attempts to use FU when none available
317 system.cpu.iq.fu_full::FloatMult 0 0.00% 0.52% # attempts to use FU when none available
318 system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.52% # attempts to use FU when none available
319 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.52% # attempts to use FU when none available
320 system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.52% # attempts to use FU when none available
321 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.52% # attempts to use FU when none available
322 system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.52% # attempts to use FU when none available
323 system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.52% # attempts to use FU when none available
324 system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.52% # attempts to use FU when none available
325 system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.52% # attempts to use FU when none available
326 system.cpu.iq.fu_full::SimdMult 0 0.00% 0.52% # attempts to use FU when none available
327 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.52% # attempts to use FU when none available
328 system.cpu.iq.fu_full::SimdShift 0 0.00% 0.52% # attempts to use FU when none available
329 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.52% # attempts to use FU when none available
330 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.52% # attempts to use FU when none available
331 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.52% # attempts to use FU when none available
332 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.52% # attempts to use FU when none available
333 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.52% # attempts to use FU when none available
334 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.52% # attempts to use FU when none available
335 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.52% # attempts to use FU when none available
336 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.52% # attempts to use FU when none available
337 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.52% # attempts to use FU when none available
338 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.52% # attempts to use FU when none available
339 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.52% # attempts to use FU when none available
340 system.cpu.iq.fu_full::MemRead 8417784 94.58% 95.09% # attempts to use FU when none available
341 system.cpu.iq.fu_full::MemWrite 436630 4.91% 100.00% # attempts to use FU when none available
342 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
343 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
344 system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued
345 system.cpu.iq.FU_type_0::IntAlu 60069483 47.35% 47.43% # Type of FU issued
346 system.cpu.iq.FU_type_0::IntMult 96615 0.08% 47.51% # Type of FU issued
347 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued
348 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued
349 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued
350 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued
351 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued
352 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued
353 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued
354 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued
355 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued
356 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued
357 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued
358 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued
359 system.cpu.iq.FU_type_0::SimdMisc 8 0.00% 47.51% # Type of FU issued
360 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued
361 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued
362 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.51% # Type of FU issued
363 system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.51% # Type of FU issued
364 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued
365 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued
366 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued
367 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued
368 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued
369 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued
370 system.cpu.iq.FU_type_0::SimdFloatMisc 2251 0.00% 47.51% # Type of FU issued
371 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued
372 system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.51% # Type of FU issued
373 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued
374 system.cpu.iq.FU_type_0::MemRead 53942685 42.52% 90.02% # Type of FU issued
375 system.cpu.iq.FU_type_0::MemWrite 12655733 9.98% 100.00% # Type of FU issued
376 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
377 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
378 system.cpu.iq.FU_type_0::total 126873317 # Type of FU issued
379 system.cpu.iq.rate 0.305048 # Inst issue rate
380 system.cpu.iq.fu_busy_cnt 8900311 # FU busy when requested
381 system.cpu.iq.fu_busy_rate 0.070151 # FU busy rate (busy events/executed inst)
382 system.cpu.iq.int_inst_queue_reads 418533130 # Number of integer instruction queue reads
383 system.cpu.iq.int_inst_queue_writes 131726191 # Number of integer instruction queue writes
384 system.cpu.iq.int_inst_queue_wakeup_accesses 87292109 # Number of integer instruction queue wakeup accesses
385 system.cpu.iq.fp_inst_queue_reads 24017 # Number of floating instruction queue reads
386 system.cpu.iq.fp_inst_queue_writes 13690 # Number of floating instruction queue writes
387 system.cpu.iq.fp_inst_queue_wakeup_accesses 10446 # Number of floating instruction queue wakeup accesses
388 system.cpu.iq.int_alu_accesses 135654306 # Number of integer alu accesses
389 system.cpu.iq.fp_alu_accesses 12792 # Number of floating point alu accesses
390 system.cpu.iew.lsq.thread0.forwLoads 614767 # Number of loads that had data forwarded from stores
391 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
392 system.cpu.iew.lsq.thread0.squashedLoads 6301517 # Number of loads squashed
393 system.cpu.iew.lsq.thread0.ignoredResponses 11128 # Number of memory responses ignored because the instruction is squashed
394 system.cpu.iew.lsq.thread0.memOrderViolation 32657 # Number of memory ordering violations
395 system.cpu.iew.lsq.thread0.squashedStores 2389653 # Number of stores squashed
396 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
397 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
398 system.cpu.iew.lsq.thread0.rescheduledLoads 34061869 # Number of loads that were rescheduled
399 system.cpu.iew.lsq.thread0.cacheBlocked 1153605 # Number of times an access to memory failed due to the cache being blocked
400 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
401 system.cpu.iew.iewSquashCycles 4628113 # Number of cycles IEW is squashing
402 system.cpu.iew.iewBlockCycles 28345943 # Number of cycles IEW is blocking
403 system.cpu.iew.iewUnblockCycles 419499 # Number of cycles IEW is unblocking
404 system.cpu.iew.iewDispatchedInsts 104949442 # Number of instructions dispatched to IQ
405 system.cpu.iew.iewDispSquashedInsts 473979 # Number of squashed instructions skipped by dispatch
406 system.cpu.iew.iewDispLoadInsts 21982315 # Number of dispatched load instructions
407 system.cpu.iew.iewDispStoreInsts 14168730 # Number of dispatched store instructions
408 system.cpu.iew.iewDispNonSpecInsts 1228030 # Number of dispatched non-speculative instructions
409 system.cpu.iew.iewIQFullEvents 85187 # Number of times the IQ has become full, causing a stall
410 system.cpu.iew.iewLSQFullEvents 7556 # Number of times the LSQ has become full, causing a stall
411 system.cpu.iew.memOrderViolationEvents 32657 # Number of memory order violations
412 system.cpu.iew.predictedTakenIncorrect 850397 # Number of branches that were predicted taken incorrectly
413 system.cpu.iew.predictedNotTakenIncorrect 257130 # Number of branches that were predicted not taken incorrectly
414 system.cpu.iew.branchMispredicts 1107527 # Number of branch mispredicts detected at execute
415 system.cpu.iew.iewExecutedInsts 123429780 # Number of executed instructions
416 system.cpu.iew.iewExecLoadInsts 52914304 # Number of load instructions executed
417 system.cpu.iew.iewExecSquashedInsts 3443537 # Number of squashed instructions skipped in execute
418 system.cpu.iew.exec_swp 0 # number of swp insts executed
419 system.cpu.iew.exec_nop 214615 # number of nop insts executed
420 system.cpu.iew.exec_refs 65401525 # number of memory reference insts executed
421 system.cpu.iew.exec_branches 11705842 # Number of branches executed
422 system.cpu.iew.exec_stores 12487221 # Number of stores executed
423 system.cpu.iew.exec_rate 0.296769 # Inst execution rate
424 system.cpu.iew.wb_sent 121771134 # cumulative count of insts sent to commit
425 system.cpu.iew.wb_count 87302555 # cumulative count of insts written-back
426 system.cpu.iew.wb_producers 47043389 # num instructions producing a value
427 system.cpu.iew.wb_consumers 86638668 # num instructions consuming a value
428 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
429 system.cpu.iew.wb_rate 0.209906 # insts written-back per cycle
430 system.cpu.iew.wb_fanout 0.542984 # average fanout of values written-back
431 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
432 system.cpu.commit.commitCommittedInsts 76940388 # The number of committed instructions
433 system.cpu.commit.commitSquashedInsts 27793277 # The number of squashed insts skipped by commit
434 system.cpu.commit.commitNonSpecStalls 1499693 # The number of times commit has been forced to stall to communicate backwards
435 system.cpu.commit.branchMispredicts 977065 # The number of times a branch was mispredicted
436 system.cpu.commit.committed_per_cycle::samples 150996763 # Number of insts commited each cycle
437 system.cpu.commit.committed_per_cycle::mean 0.509550 # Number of insts commited each cycle
438 system.cpu.commit.committed_per_cycle::stdev 1.459324 # Number of insts commited each cycle
439 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
440 system.cpu.commit.committed_per_cycle::0 122144480 80.89% 80.89% # Number of insts commited each cycle
441 system.cpu.commit.committed_per_cycle::1 14839804 9.83% 90.72% # Number of insts commited each cycle
442 system.cpu.commit.committed_per_cycle::2 4110999 2.72% 93.44% # Number of insts commited each cycle
443 system.cpu.commit.committed_per_cycle::3 2181780 1.44% 94.89% # Number of insts commited each cycle
444 system.cpu.commit.committed_per_cycle::4 1788910 1.18% 96.07% # Number of insts commited each cycle
445 system.cpu.commit.committed_per_cycle::5 1360879 0.90% 96.97% # Number of insts commited each cycle
446 system.cpu.commit.committed_per_cycle::6 1262027 0.84% 97.81% # Number of insts commited each cycle
447 system.cpu.commit.committed_per_cycle::7 662023 0.44% 98.25% # Number of insts commited each cycle
448 system.cpu.commit.committed_per_cycle::8 2645861 1.75% 100.00% # Number of insts commited each cycle
449 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
450 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
451 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
452 system.cpu.commit.committed_per_cycle::total 150996763 # Number of insts commited each cycle
453 system.cpu.commit.count 76940388 # Number of instructions committed
454 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
455 system.cpu.commit.refs 27459875 # Number of memory references committed
456 system.cpu.commit.loads 15680798 # Number of loads committed
457 system.cpu.commit.membars 413062 # Number of memory barriers committed
458 system.cpu.commit.branches 9891038 # Number of branches committed
459 system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
460 system.cpu.commit.int_insts 68493475 # Number of committed integer instructions.
461 system.cpu.commit.function_calls 995603 # Number of function calls committed.
462 system.cpu.commit.bw_lim_events 2645861 # number cycles where commit BW limit reached
463 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
464 system.cpu.rob.rob_reads 251328068 # The number of ROB reads
465 system.cpu.rob.rob_writes 214226863 # The number of ROB writes
466 system.cpu.timesIdled 1877486 # Number of times that the entire CPU went into an idle state and unscheduled itself
467 system.cpu.idleCycles 260369567 # Total number of cycles that the CPU has spent unscheduled due to idling
468 system.cpu.quiesceCycles 4591132146 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
469 system.cpu.committedInsts 76790007 # Number of Instructions Simulated
470 system.cpu.committedInsts_total 76790007 # Number of Instructions Simulated
471 system.cpu.cpi 5.416227 # CPI: Cycles Per Instruction
472 system.cpu.cpi_total 5.416227 # CPI: Total CPI of All Threads
473 system.cpu.ipc 0.184630 # IPC: Instructions Per Cycle
474 system.cpu.ipc_total 0.184630 # IPC: Total IPC of All Threads
475 system.cpu.int_regfile_reads 559625789 # number of integer regfile reads
476 system.cpu.int_regfile_writes 89694790 # number of integer regfile writes
477 system.cpu.fp_regfile_reads 8322 # number of floating regfile reads
478 system.cpu.fp_regfile_writes 2832 # number of floating regfile writes
479 system.cpu.misc_regfile_reads 137256850 # number of misc regfile reads
480 system.cpu.misc_regfile_writes 912282 # number of misc regfile writes
481 system.cpu.icache.replacements 991618 # number of replacements
482 system.cpu.icache.tagsinuse 511.615309 # Cycle average of tags in use
483 system.cpu.icache.total_refs 13036767 # Total number of references to valid blocks.
484 system.cpu.icache.sampled_refs 992130 # Sample count of references to valid blocks.
485 system.cpu.icache.avg_refs 13.140180 # Average number of references to valid blocks.
486 system.cpu.icache.warmup_cycle 6445921000 # Cycle when the warmup percentage was hit.
487 system.cpu.icache.occ_blocks::0 511.615309 # Average occupied blocks per context
488 system.cpu.icache.occ_percent::0 0.999249 # Average percentage of cache occupancy
489 system.cpu.icache.ReadReq_hits::0 13036767 # number of ReadReq hits
490 system.cpu.icache.ReadReq_hits::total 13036767 # number of ReadReq hits
491 system.cpu.icache.demand_hits::0 13036767 # number of demand (read+write) hits
492 system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
493 system.cpu.icache.demand_hits::total 13036767 # number of demand (read+write) hits
494 system.cpu.icache.overall_hits::0 13036767 # number of overall hits
495 system.cpu.icache.overall_hits::1 0 # number of overall hits
496 system.cpu.icache.overall_hits::total 13036767 # number of overall hits
497 system.cpu.icache.ReadReq_misses::0 1079261 # number of ReadReq misses
498 system.cpu.icache.ReadReq_misses::total 1079261 # number of ReadReq misses
499 system.cpu.icache.demand_misses::0 1079261 # number of demand (read+write) misses
500 system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
501 system.cpu.icache.demand_misses::total 1079261 # number of demand (read+write) misses
502 system.cpu.icache.overall_misses::0 1079261 # number of overall misses
503 system.cpu.icache.overall_misses::1 0 # number of overall misses
504 system.cpu.icache.overall_misses::total 1079261 # number of overall misses
505 system.cpu.icache.ReadReq_miss_latency 15910722989 # number of ReadReq miss cycles
506 system.cpu.icache.demand_miss_latency 15910722989 # number of demand (read+write) miss cycles
507 system.cpu.icache.overall_miss_latency 15910722989 # number of overall miss cycles
508 system.cpu.icache.ReadReq_accesses::0 14116028 # number of ReadReq accesses(hits+misses)
509 system.cpu.icache.ReadReq_accesses::total 14116028 # number of ReadReq accesses(hits+misses)
510 system.cpu.icache.demand_accesses::0 14116028 # number of demand (read+write) accesses
511 system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
512 system.cpu.icache.demand_accesses::total 14116028 # number of demand (read+write) accesses
513 system.cpu.icache.overall_accesses::0 14116028 # number of overall (read+write) accesses
514 system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
515 system.cpu.icache.overall_accesses::total 14116028 # number of overall (read+write) accesses
516 system.cpu.icache.ReadReq_miss_rate::0 0.076456 # miss rate for ReadReq accesses
517 system.cpu.icache.demand_miss_rate::0 0.076456 # miss rate for demand accesses
518 system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
519 system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
520 system.cpu.icache.overall_miss_rate::0 0.076456 # miss rate for overall accesses
521 system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
522 system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
523 system.cpu.icache.ReadReq_avg_miss_latency::0 14742.238429 # average ReadReq miss latency
524 system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
525 system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
526 system.cpu.icache.demand_avg_miss_latency::0 14742.238429 # average overall miss latency
527 system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
528 system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
529 system.cpu.icache.overall_avg_miss_latency::0 14742.238429 # average overall miss latency
530 system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
531 system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
532 system.cpu.icache.blocked_cycles::no_mshrs 2475992 # number of cycles access was blocked
533 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
534 system.cpu.icache.blocked::no_mshrs 368 # number of cycles access was blocked
535 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
536 system.cpu.icache.avg_blocked_cycles::no_mshrs 6728.239130 # average number of cycles each access was blocked
537 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
538 system.cpu.icache.fast_writes 0 # number of fast writes performed
539 system.cpu.icache.cache_copies 0 # number of cache copies performed
540 system.cpu.icache.writebacks 57161 # number of writebacks
541 system.cpu.icache.ReadReq_mshr_hits 87101 # number of ReadReq MSHR hits
542 system.cpu.icache.demand_mshr_hits 87101 # number of demand (read+write) MSHR hits
543 system.cpu.icache.overall_mshr_hits 87101 # number of overall MSHR hits
544 system.cpu.icache.ReadReq_mshr_misses 992160 # number of ReadReq MSHR misses
545 system.cpu.icache.demand_mshr_misses 992160 # number of demand (read+write) MSHR misses
546 system.cpu.icache.overall_mshr_misses 992160 # number of overall MSHR misses
547 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
548 system.cpu.icache.ReadReq_mshr_miss_latency 11856676492 # number of ReadReq MSHR miss cycles
549 system.cpu.icache.demand_mshr_miss_latency 11856676492 # number of demand (read+write) MSHR miss cycles
550 system.cpu.icache.overall_mshr_miss_latency 11856676492 # number of overall MSHR miss cycles
551 system.cpu.icache.ReadReq_mshr_uncacheable_latency 6359500 # number of ReadReq MSHR uncacheable cycles
552 system.cpu.icache.overall_mshr_uncacheable_latency 6359500 # number of overall MSHR uncacheable cycles
553 system.cpu.icache.ReadReq_mshr_miss_rate::0 0.070286 # mshr miss rate for ReadReq accesses
554 system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
555 system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
556 system.cpu.icache.demand_mshr_miss_rate::0 0.070286 # mshr miss rate for demand accesses
557 system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
558 system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
559 system.cpu.icache.overall_mshr_miss_rate::0 0.070286 # mshr miss rate for overall accesses
560 system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
561 system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
562 system.cpu.icache.ReadReq_avg_mshr_miss_latency 11950.367372 # average ReadReq mshr miss latency
563 system.cpu.icache.demand_avg_mshr_miss_latency 11950.367372 # average overall mshr miss latency
564 system.cpu.icache.overall_avg_mshr_miss_latency 11950.367372 # average overall mshr miss latency
565 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
566 system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
567 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
568 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
569 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
570 system.cpu.dcache.replacements 643915 # number of replacements
571 system.cpu.dcache.tagsinuse 511.991681 # Cycle average of tags in use
572 system.cpu.dcache.total_refs 22265831 # Total number of references to valid blocks.
573 system.cpu.dcache.sampled_refs 644427 # Sample count of references to valid blocks.
574 system.cpu.dcache.avg_refs 34.551363 # Average number of references to valid blocks.
575 system.cpu.dcache.warmup_cycle 48663000 # Cycle when the warmup percentage was hit.
576 system.cpu.dcache.occ_blocks::0 511.991681 # Average occupied blocks per context
577 system.cpu.dcache.occ_percent::0 0.999984 # Average percentage of cache occupancy
578 system.cpu.dcache.ReadReq_hits::0 14412375 # number of ReadReq hits
579 system.cpu.dcache.ReadReq_hits::total 14412375 # number of ReadReq hits
580 system.cpu.dcache.WriteReq_hits::0 7264610 # number of WriteReq hits
581 system.cpu.dcache.WriteReq_hits::total 7264610 # number of WriteReq hits
582 system.cpu.dcache.LoadLockedReq_hits::0 299966 # number of LoadLockedReq hits
583 system.cpu.dcache.LoadLockedReq_hits::total 299966 # number of LoadLockedReq hits
584 system.cpu.dcache.StoreCondReq_hits::0 285484 # number of StoreCondReq hits
585 system.cpu.dcache.StoreCondReq_hits::total 285484 # number of StoreCondReq hits
586 system.cpu.dcache.demand_hits::0 21676985 # number of demand (read+write) hits
587 system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
588 system.cpu.dcache.demand_hits::total 21676985 # number of demand (read+write) hits
589 system.cpu.dcache.overall_hits::0 21676985 # number of overall hits
590 system.cpu.dcache.overall_hits::1 0 # number of overall hits
591 system.cpu.dcache.overall_hits::total 21676985 # number of overall hits
592 system.cpu.dcache.ReadReq_misses::0 724119 # number of ReadReq misses
593 system.cpu.dcache.ReadReq_misses::total 724119 # number of ReadReq misses
594 system.cpu.dcache.WriteReq_misses::0 2966647 # number of WriteReq misses
595 system.cpu.dcache.WriteReq_misses::total 2966647 # number of WriteReq misses
596 system.cpu.dcache.LoadLockedReq_misses::0 13487 # number of LoadLockedReq misses
597 system.cpu.dcache.LoadLockedReq_misses::total 13487 # number of LoadLockedReq misses
598 system.cpu.dcache.StoreCondReq_misses::0 18 # number of StoreCondReq misses
599 system.cpu.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses
600 system.cpu.dcache.demand_misses::0 3690766 # number of demand (read+write) misses
601 system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
602 system.cpu.dcache.demand_misses::total 3690766 # number of demand (read+write) misses
603 system.cpu.dcache.overall_misses::0 3690766 # number of overall misses
604 system.cpu.dcache.overall_misses::1 0 # number of overall misses
605 system.cpu.dcache.overall_misses::total 3690766 # number of overall misses
606 system.cpu.dcache.ReadReq_miss_latency 10885048500 # number of ReadReq miss cycles
607 system.cpu.dcache.WriteReq_miss_latency 110351571736 # number of WriteReq miss cycles
608 system.cpu.dcache.LoadLockedReq_miss_latency 219032000 # number of LoadLockedReq miss cycles
609 system.cpu.dcache.StoreCondReq_miss_latency 343000 # number of StoreCondReq miss cycles
610 system.cpu.dcache.demand_miss_latency 121236620236 # number of demand (read+write) miss cycles
611 system.cpu.dcache.overall_miss_latency 121236620236 # number of overall miss cycles
612 system.cpu.dcache.ReadReq_accesses::0 15136494 # number of ReadReq accesses(hits+misses)
613 system.cpu.dcache.ReadReq_accesses::total 15136494 # number of ReadReq accesses(hits+misses)
614 system.cpu.dcache.WriteReq_accesses::0 10231257 # number of WriteReq accesses(hits+misses)
615 system.cpu.dcache.WriteReq_accesses::total 10231257 # number of WriteReq accesses(hits+misses)
616 system.cpu.dcache.LoadLockedReq_accesses::0 313453 # number of LoadLockedReq accesses(hits+misses)
617 system.cpu.dcache.LoadLockedReq_accesses::total 313453 # number of LoadLockedReq accesses(hits+misses)
618 system.cpu.dcache.StoreCondReq_accesses::0 285502 # number of StoreCondReq accesses(hits+misses)
619 system.cpu.dcache.StoreCondReq_accesses::total 285502 # number of StoreCondReq accesses(hits+misses)
620 system.cpu.dcache.demand_accesses::0 25367751 # number of demand (read+write) accesses
621 system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
622 system.cpu.dcache.demand_accesses::total 25367751 # number of demand (read+write) accesses
623 system.cpu.dcache.overall_accesses::0 25367751 # number of overall (read+write) accesses
624 system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
625 system.cpu.dcache.overall_accesses::total 25367751 # number of overall (read+write) accesses
626 system.cpu.dcache.ReadReq_miss_rate::0 0.047839 # miss rate for ReadReq accesses
627 system.cpu.dcache.WriteReq_miss_rate::0 0.289959 # miss rate for WriteReq accesses
628 system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043027 # miss rate for LoadLockedReq accesses
629 system.cpu.dcache.StoreCondReq_miss_rate::0 0.000063 # miss rate for StoreCondReq accesses
630 system.cpu.dcache.demand_miss_rate::0 0.145490 # miss rate for demand accesses
631 system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
632 system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
633 system.cpu.dcache.overall_miss_rate::0 0.145490 # miss rate for overall accesses
634 system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
635 system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
636 system.cpu.dcache.ReadReq_avg_miss_latency::0 15032.126626 # average ReadReq miss latency
637 system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
638 system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
639 system.cpu.dcache.WriteReq_avg_miss_latency::0 37197.405602 # average WriteReq miss latency
640 system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
641 system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
642 system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16240.231334 # average LoadLockedReq miss latency
643 system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
644 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
645 system.cpu.dcache.StoreCondReq_avg_miss_latency::0 19055.555556 # average StoreCondReq miss latency
646 system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
647 system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
648 system.cpu.dcache.demand_avg_miss_latency::0 32848.633654 # average overall miss latency
649 system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
650 system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
651 system.cpu.dcache.overall_avg_miss_latency::0 32848.633654 # average overall miss latency
652 system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
653 system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
654 system.cpu.dcache.blocked_cycles::no_mshrs 16787932 # number of cycles access was blocked
655 system.cpu.dcache.blocked_cycles::no_targets 7490000 # number of cycles access was blocked
656 system.cpu.dcache.blocked::no_mshrs 2999 # number of cycles access was blocked
657 system.cpu.dcache.blocked::no_targets 273 # number of cycles access was blocked
658 system.cpu.dcache.avg_blocked_cycles::no_mshrs 5597.843281 # average number of cycles each access was blocked
659 system.cpu.dcache.avg_blocked_cycles::no_targets 27435.897436 # average number of cycles each access was blocked
660 system.cpu.dcache.fast_writes 0 # number of fast writes performed
661 system.cpu.dcache.cache_copies 0 # number of cache copies performed
662 system.cpu.dcache.writebacks 572720 # number of writebacks
663 system.cpu.dcache.ReadReq_mshr_hits 338008 # number of ReadReq MSHR hits
664 system.cpu.dcache.WriteReq_mshr_hits 2717083 # number of WriteReq MSHR hits
665 system.cpu.dcache.LoadLockedReq_mshr_hits 1442 # number of LoadLockedReq MSHR hits
666 system.cpu.dcache.demand_mshr_hits 3055091 # number of demand (read+write) MSHR hits
667 system.cpu.dcache.overall_mshr_hits 3055091 # number of overall MSHR hits
668 system.cpu.dcache.ReadReq_mshr_misses 386111 # number of ReadReq MSHR misses
669 system.cpu.dcache.WriteReq_mshr_misses 249564 # number of WriteReq MSHR misses
670 system.cpu.dcache.LoadLockedReq_mshr_misses 12045 # number of LoadLockedReq MSHR misses
671 system.cpu.dcache.StoreCondReq_mshr_misses 18 # number of StoreCondReq MSHR misses
672 system.cpu.dcache.demand_mshr_misses 635675 # number of demand (read+write) MSHR misses
673 system.cpu.dcache.overall_mshr_misses 635675 # number of overall MSHR misses
674 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
675 system.cpu.dcache.ReadReq_mshr_miss_latency 5247540500 # number of ReadReq MSHR miss cycles
676 system.cpu.dcache.WriteReq_mshr_miss_latency 8926098932 # number of WriteReq MSHR miss cycles
677 system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161654000 # number of LoadLockedReq MSHR miss cycles
678 system.cpu.dcache.StoreCondReq_mshr_miss_latency 282500 # number of StoreCondReq MSHR miss cycles
679 system.cpu.dcache.demand_mshr_miss_latency 14173639432 # number of demand (read+write) MSHR miss cycles
680 system.cpu.dcache.overall_mshr_miss_latency 14173639432 # number of overall MSHR miss cycles
681 system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147158749000 # number of ReadReq MSHR uncacheable cycles
682 system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42258178710 # number of WriteReq MSHR uncacheable cycles
683 system.cpu.dcache.overall_mshr_uncacheable_latency 189416927710 # number of overall MSHR uncacheable cycles
684 system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025509 # mshr miss rate for ReadReq accesses
685 system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
686 system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
687 system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024392 # mshr miss rate for WriteReq accesses
688 system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
689 system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
690 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038427 # mshr miss rate for LoadLockedReq accesses
691 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
692 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
693 system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000063 # mshr miss rate for StoreCondReq accesses
694 system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
695 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
696 system.cpu.dcache.demand_mshr_miss_rate::0 0.025058 # mshr miss rate for demand accesses
697 system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
698 system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
699 system.cpu.dcache.overall_mshr_miss_rate::0 0.025058 # mshr miss rate for overall accesses
700 system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
701 system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
702 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13590.756285 # average ReadReq mshr miss latency
703 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35766.772980 # average WriteReq mshr miss latency
704 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13420.838522 # average LoadLockedReq mshr miss latency
705 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 15694.444444 # average StoreCondReq mshr miss latency
706 system.cpu.dcache.demand_avg_mshr_miss_latency 22296.990494 # average overall mshr miss latency
707 system.cpu.dcache.overall_avg_mshr_miss_latency 22296.990494 # average overall mshr miss latency
708 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
709 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
710 system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
711 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
712 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
713 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
714 system.iocache.replacements 0 # number of replacements
715 system.iocache.tagsinuse 0 # Cycle average of tags in use
716 system.iocache.total_refs 0 # Total number of references to valid blocks.
717 system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
718 system.iocache.avg_refs no_value # Average number of references to valid blocks.
719 system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
720 system.iocache.demand_hits::0 0 # number of demand (read+write) hits
721 system.iocache.demand_hits::1 0 # number of demand (read+write) hits
722 system.iocache.demand_hits::total 0 # number of demand (read+write) hits
723 system.iocache.overall_hits::0 0 # number of overall hits
724 system.iocache.overall_hits::1 0 # number of overall hits
725 system.iocache.overall_hits::total 0 # number of overall hits
726 system.iocache.demand_misses::0 0 # number of demand (read+write) misses
727 system.iocache.demand_misses::1 0 # number of demand (read+write) misses
728 system.iocache.demand_misses::total 0 # number of demand (read+write) misses
729 system.iocache.overall_misses::0 0 # number of overall misses
730 system.iocache.overall_misses::1 0 # number of overall misses
731 system.iocache.overall_misses::total 0 # number of overall misses
732 system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
733 system.iocache.overall_miss_latency 0 # number of overall miss cycles
734 system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
735 system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
736 system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
737 system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
738 system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
739 system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
740 system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
741 system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
742 system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
743 system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
744 system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
745 system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
746 system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
747 system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
748 system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
749 system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
750 system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
751 system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
752 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
753 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
754 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
755 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
756 system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
757 system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
758 system.iocache.fast_writes 0 # number of fast writes performed
759 system.iocache.cache_copies 0 # number of cache copies performed
760 system.iocache.writebacks 0 # number of writebacks
761 system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
762 system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
763 system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
764 system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
765 system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
766 system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
767 system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
768 system.iocache.ReadReq_mshr_uncacheable_latency 1307898920918 # number of ReadReq MSHR uncacheable cycles
769 system.iocache.overall_mshr_uncacheable_latency 1307898920918 # number of overall MSHR uncacheable cycles
770 system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
771 system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
772 system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
773 system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
774 system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
775 system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
776 system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
777 system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
778 system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
779 system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
780 system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
781 system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
782 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
783 system.cpu.kern.inst.arm 0 # number of arm instructions executed
784 system.cpu.kern.inst.quiesce 87985 # number of quiesce instructions executed
786 ---------- End Simulation Statistics ----------
projects / gem5.git / blob