2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.054241 # Number of seconds simulated
4 sim_ticks 54240666000 # Number of ticks simulated
5 final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 2777644 # Simulator instruction rate (inst/s)
8 host_tick_rate 1651027932 # Simulator tick rate (ticks/s)
9 host_mem_usage 342980 # Number of bytes of host memory used
10 host_seconds 32.85 # Real time elapsed on the host
11 sim_insts 91252969 # Number of instructions simulated
12 system.physmem.bytes_read 521339715 # Number of bytes read from this memory
13 system.physmem.bytes_inst_read 431323116 # Number of instructions bytes read from this memory
14 system.physmem.bytes_written 18908138 # Number of bytes written to this memory
15 system.physmem.num_reads 130384074 # Number of read requests responded to by this memory
16 system.physmem.num_writes 4738868 # Number of write requests responded to by this memory
17 system.physmem.num_other 0 # Number of other requests responded to by this memory
18 system.physmem.bw_read 9611602391 # Total read bandwidth from this memory (bytes/s)
19 system.physmem.bw_inst_read 7952024704 # Instruction read bandwidth from this memory (bytes/s)
20 system.physmem.bw_write 348597084 # Write bandwidth from this memory (bytes/s)
21 system.physmem.bw_total 9960199475 # Total bandwidth to/from this memory (bytes/s)
22 system.cpu.dtb.inst_hits 0 # ITB inst hits
23 system.cpu.dtb.inst_misses 0 # ITB inst misses
24 system.cpu.dtb.read_hits 0 # DTB read hits
25 system.cpu.dtb.read_misses 0 # DTB read misses
26 system.cpu.dtb.write_hits 0 # DTB write hits
27 system.cpu.dtb.write_misses 0 # DTB write misses
28 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
29 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
30 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
31 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
32 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
33 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
34 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
35 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
36 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
37 system.cpu.dtb.read_accesses 0 # DTB read accesses
38 system.cpu.dtb.write_accesses 0 # DTB write accesses
39 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
40 system.cpu.dtb.hits 0 # DTB hits
41 system.cpu.dtb.misses 0 # DTB misses
42 system.cpu.dtb.accesses 0 # DTB accesses
43 system.cpu.itb.inst_hits 0 # ITB inst hits
44 system.cpu.itb.inst_misses 0 # ITB inst misses
45 system.cpu.itb.read_hits 0 # DTB read hits
46 system.cpu.itb.read_misses 0 # DTB read misses
47 system.cpu.itb.write_hits 0 # DTB write hits
48 system.cpu.itb.write_misses 0 # DTB write misses
49 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
50 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
51 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
52 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
53 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
54 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
55 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
56 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
57 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
58 system.cpu.itb.read_accesses 0 # DTB read accesses
59 system.cpu.itb.write_accesses 0 # DTB write accesses
60 system.cpu.itb.inst_accesses 0 # ITB inst accesses
61 system.cpu.itb.hits 0 # DTB hits
62 system.cpu.itb.misses 0 # DTB misses
63 system.cpu.itb.accesses 0 # DTB accesses
64 system.cpu.workload.num_syscalls 442 # Number of system calls
65 system.cpu.numCycles 108481333 # number of cpu cycles simulated
66 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
67 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
68 system.cpu.num_insts 91252969 # Number of instructions executed
69 system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
70 system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
71 system.cpu.num_func_calls 96832 # number of times a function call or return occured
72 system.cpu.num_conditional_control_insts 15127614 # number of instructions that are conditional controls
73 system.cpu.num_int_insts 72525682 # number of integer instructions
74 system.cpu.num_fp_insts 48 # number of float instructions
75 system.cpu.num_int_register_reads 396912516 # number of times the integer registers were read
76 system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written
77 system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
78 system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
79 system.cpu.num_mem_refs 27318811 # number of memory refs
80 system.cpu.num_load_insts 22573967 # Number of load instructions
81 system.cpu.num_store_insts 4744844 # Number of store instructions
82 system.cpu.num_idle_cycles 0 # Number of idle cycles
83 system.cpu.num_busy_cycles 108481333 # Number of busy cycles
84 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
85 system.cpu.idle_fraction 0 # Percentage of idle cycles
87 ---------- End Simulation Statistics ----------
projects / gem5.git / blob