tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 dummy=0
   5
   6 [system]
   7 type=System
   8 children=cpu membus physmem
   9 mem_mode=atomic
  10 physmem=system.physmem
  11
  12 [system.cpu]
  13 type=TimingSimpleCPU
  14 children=dcache dtb icache itb l2cache toL2Bus tracer workload
  15 checker=Null
  16 clock=500
  17 cpu_id=0
  18 defer_registration=false
  19 do_checkpoint_insts=true
  20 do_statistics_insts=true
  21 dtb=system.cpu.dtb
  22 function_trace=false
  23 function_trace_start=0
  24 itb=system.cpu.itb
  25 max_insts_all_threads=0
  26 max_insts_any_thread=0
  27 max_loads_all_threads=0
  28 max_loads_any_thread=0
  29 numThreads=1
  30 phase=0
  31 progress_interval=0
  32 system=system
  33 tracer=system.cpu.tracer
  34 workload=system.cpu.workload
  35 dcache_port=system.cpu.dcache.cpu_side
  36 icache_port=system.cpu.icache.cpu_side
  37
  38 [system.cpu.dcache]
  39 type=BaseCache
  40 addr_range=0:18446744073709551615
  41 assoc=2
  42 block_size=64
  43 forward_snoops=true
  44 hash_delay=1
  45 latency=1000
  46 max_miss_count=0
  47 mshrs=10
  48 num_cpus=1
  49 prefetch_data_accesses_only=false
  50 prefetch_degree=1
  51 prefetch_latency=10000
  52 prefetch_on_access=false
  53 prefetch_past_page=false
  54 prefetch_policy=none
  55 prefetch_serial_squash=false
  56 prefetch_use_cpu_id=true
  57 prefetcher_size=100
  58 prioritizeRequests=false
  59 repl=Null
  60 size=262144
  61 subblock_size=0
  62 tgts_per_mshr=5
  63 trace_addr=0
  64 two_queue=false
  65 write_buffers=8
  66 cpu_side=system.cpu.dcache_port
  67 mem_side=system.cpu.toL2Bus.port[1]
  68
  69 [system.cpu.dtb]
  70 type=ArmTLB
  71 size=64
  72
  73 [system.cpu.icache]
  74 type=BaseCache
  75 addr_range=0:18446744073709551615
  76 assoc=2
  77 block_size=64
  78 forward_snoops=true
  79 hash_delay=1
  80 latency=1000
  81 max_miss_count=0
  82 mshrs=10
  83 num_cpus=1
  84 prefetch_data_accesses_only=false
  85 prefetch_degree=1
  86 prefetch_latency=10000
  87 prefetch_on_access=false
  88 prefetch_past_page=false
  89 prefetch_policy=none
  90 prefetch_serial_squash=false
  91 prefetch_use_cpu_id=true
  92 prefetcher_size=100
  93 prioritizeRequests=false
  94 repl=Null
  95 size=131072
  96 subblock_size=0
  97 tgts_per_mshr=5
  98 trace_addr=0
  99 two_queue=false
 100 write_buffers=8
 101 cpu_side=system.cpu.icache_port
 102 mem_side=system.cpu.toL2Bus.port[0]
 103
 104 [system.cpu.itb]
 105 type=ArmTLB
 106 size=64
 107
 108 [system.cpu.l2cache]
 109 type=BaseCache
 110 addr_range=0:18446744073709551615
 111 assoc=2
 112 block_size=64
 113 forward_snoops=true
 114 hash_delay=1
 115 latency=10000
 116 max_miss_count=0
 117 mshrs=10
 118 num_cpus=1
 119 prefetch_data_accesses_only=false
 120 prefetch_degree=1
 121 prefetch_latency=100000
 122 prefetch_on_access=false
 123 prefetch_past_page=false
 124 prefetch_policy=none
 125 prefetch_serial_squash=false
 126 prefetch_use_cpu_id=true
 127 prefetcher_size=100
 128 prioritizeRequests=false
 129 repl=Null
 130 size=2097152
 131 subblock_size=0
 132 tgts_per_mshr=5
 133 trace_addr=0
 134 two_queue=false
 135 write_buffers=8
 136 cpu_side=system.cpu.toL2Bus.port[2]
 137 mem_side=system.membus.port[1]
 138
 139 [system.cpu.toL2Bus]
 140 type=Bus
 141 block_size=64
 142 bus_id=0
 143 clock=1000
 144 header_cycles=1
 145 use_default_range=false
 146 width=64
 147 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 148
 149 [system.cpu.tracer]
 150 type=ExeTracer
 151
 152 [system.cpu.workload]
 153 type=LiveProcess
 154 cmd=mcf mcf.in
 155 cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
 156 egid=100
 157 env=
 158 errout=cerr
 159 euid=100
 160 executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
 161 gid=100
 162 input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
 163 max_stack_size=67108864
 164 output=cout
 165 pid=100
 166 ppid=99
 167 simpoint=55300000000
 168 system=system
 169 uid=100
 170
 171 [system.membus]
 172 type=Bus
 173 block_size=64
 174 bus_id=0
 175 clock=1000
 176 header_cycles=1
 177 use_default_range=false
 178 width=64
 179 port=system.physmem.port[0] system.cpu.l2cache.mem_side
 180
 181 [system.physmem]
 182 type=PhysicalMemory
 183 file=
 184 latency=30000
 185 latency_var=0
 186 null=false
 187 range=0:268435455
 188 zero=false
 189 port=system.membus.port[0]
 190