2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 712663 # Simulator instruction rate (inst/s)
4 host_mem_usage 336988 # Number of bytes of host memory used
5 host_seconds 342.15 # Real time elapsed on the host
6 host_tick_rate 1070988197 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 243835278 # Number of instructions simulated
9 sim_seconds 0.366435 # Number of seconds simulated
10 sim_ticks 366435406000 # Number of ticks simulated
11 system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses)
12 system.cpu.dcache.ReadReq_avg_miss_latency 14009.690242 # average ReadReq miss latency
13 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.690242 # average ReadReq mshr miss latency
14 system.cpu.dcache.ReadReq_hits 81327577 # number of ReadReq hits
15 system.cpu.dcache.ReadReq_miss_latency 12508650000 # number of ReadReq miss cycles
16 system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses
17 system.cpu.dcache.ReadReq_misses 892857 # number of ReadReq misses
18 system.cpu.dcache.ReadReq_mshr_miss_latency 9830079000 # number of ReadReq MSHR miss cycles
19 system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses
20 system.cpu.dcache.ReadReq_mshr_misses 892857 # number of ReadReq MSHR misses
21 system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses)
22 system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
23 system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
24 system.cpu.dcache.SwapReq_hits 3878 # number of SwapReq hits
25 system.cpu.dcache.SwapReq_miss_latency 448000 # number of SwapReq miss cycles
26 system.cpu.dcache.SwapReq_miss_rate 0.002059 # miss rate for SwapReq accesses
27 system.cpu.dcache.SwapReq_misses 8 # number of SwapReq misses
28 system.cpu.dcache.SwapReq_mshr_miss_latency 424000 # number of SwapReq MSHR miss cycles
29 system.cpu.dcache.SwapReq_mshr_miss_rate 0.002059 # mshr miss rate for SwapReq accesses
30 system.cpu.dcache.SwapReq_mshr_misses 8 # number of SwapReq MSHR misses
31 system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses)
32 system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
33 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
34 system.cpu.dcache.WriteReq_hits 22806988 # number of WriteReq hits
35 system.cpu.dcache.WriteReq_miss_latency 5317928000 # number of WriteReq miss cycles
36 system.cpu.dcache.WriteReq_miss_rate 0.004147 # miss rate for WriteReq accesses
37 system.cpu.dcache.WriteReq_misses 94963 # number of WriteReq misses
38 system.cpu.dcache.WriteReq_mshr_miss_latency 5033039000 # number of WriteReq MSHR miss cycles
39 system.cpu.dcache.WriteReq_mshr_miss_rate 0.004147 # mshr miss rate for WriteReq accesses
40 system.cpu.dcache.WriteReq_mshr_misses 94963 # number of WriteReq MSHR misses
41 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
42 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
43 system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
44 system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
45 system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
46 system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
47 system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
48 system.cpu.dcache.cache_copies 0 # number of cache copies performed
49 system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses
50 system.cpu.dcache.demand_avg_miss_latency 18046.382944 # average overall miss latency
51 system.cpu.dcache.demand_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency
52 system.cpu.dcache.demand_hits 104134565 # number of demand (read+write) hits
53 system.cpu.dcache.demand_miss_latency 17826578000 # number of demand (read+write) miss cycles
54 system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses
55 system.cpu.dcache.demand_misses 987820 # number of demand (read+write) misses
56 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
57 system.cpu.dcache.demand_mshr_miss_latency 14863118000 # number of demand (read+write) MSHR miss cycles
58 system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses
59 system.cpu.dcache.demand_mshr_misses 987820 # number of demand (read+write) MSHR misses
60 system.cpu.dcache.fast_writes 0 # number of fast writes performed
61 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
62 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
63 system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses
64 system.cpu.dcache.overall_avg_miss_latency 18046.382944 # average overall miss latency
65 system.cpu.dcache.overall_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency
66 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
67 system.cpu.dcache.overall_hits 104134565 # number of overall hits
68 system.cpu.dcache.overall_miss_latency 17826578000 # number of overall miss cycles
69 system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses
70 system.cpu.dcache.overall_misses 987820 # number of overall misses
71 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
72 system.cpu.dcache.overall_mshr_miss_latency 14863118000 # number of overall MSHR miss cycles
73 system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses
74 system.cpu.dcache.overall_mshr_misses 987820 # number of overall MSHR misses
75 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
76 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
77 system.cpu.dcache.replacements 935475 # number of replacements
78 system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
79 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
80 system.cpu.dcache.tagsinuse 3569.622607 # Cycle average of tags in use
81 system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
82 system.cpu.dcache.warmup_cycle 134379688000 # Cycle when the warmup percentage was hit.
83 system.cpu.dcache.writebacks 94875 # number of writebacks
84 system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses)
85 system.cpu.icache.ReadReq_avg_miss_latency 55904.761905 # average ReadReq miss latency
86 system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905 # average ReadReq mshr miss latency
87 system.cpu.icache.ReadReq_hits 244420630 # number of ReadReq hits
88 system.cpu.icache.ReadReq_miss_latency 49308000 # number of ReadReq miss cycles
89 system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
90 system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses
91 system.cpu.icache.ReadReq_mshr_miss_latency 46662000 # number of ReadReq MSHR miss cycles
92 system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
93 system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses
94 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
95 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
96 system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks.
97 system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
98 system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
99 system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
100 system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
101 system.cpu.icache.cache_copies 0 # number of cache copies performed
102 system.cpu.icache.demand_accesses 244421512 # number of demand (read+write) accesses
103 system.cpu.icache.demand_avg_miss_latency 55904.761905 # average overall miss latency
104 system.cpu.icache.demand_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency
105 system.cpu.icache.demand_hits 244420630 # number of demand (read+write) hits
106 system.cpu.icache.demand_miss_latency 49308000 # number of demand (read+write) miss cycles
107 system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
108 system.cpu.icache.demand_misses 882 # number of demand (read+write) misses
109 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
110 system.cpu.icache.demand_mshr_miss_latency 46662000 # number of demand (read+write) MSHR miss cycles
111 system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
112 system.cpu.icache.demand_mshr_misses 882 # number of demand (read+write) MSHR misses
113 system.cpu.icache.fast_writes 0 # number of fast writes performed
114 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
115 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
116 system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses
117 system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency
118 system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency
119 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
120 system.cpu.icache.overall_hits 244420630 # number of overall hits
121 system.cpu.icache.overall_miss_latency 49308000 # number of overall miss cycles
122 system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
123 system.cpu.icache.overall_misses 882 # number of overall misses
124 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
125 system.cpu.icache.overall_mshr_miss_latency 46662000 # number of overall MSHR miss cycles
126 system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
127 system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses
128 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
129 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
130 system.cpu.icache.replacements 25 # number of replacements
131 system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
132 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
133 system.cpu.icache.tagsinuse 726.242454 # Cycle average of tags in use
134 system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks.
135 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
136 system.cpu.icache.writebacks 0 # number of writebacks
137 system.cpu.idle_fraction 0 # Percentage of idle cycles
138 system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses)
139 system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
140 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
141 system.cpu.l2cache.ReadExReq_miss_latency 2429128000 # number of ReadExReq miss cycles
142 system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
143 system.cpu.l2cache.ReadExReq_misses 46714 # number of ReadExReq misses
144 system.cpu.l2cache.ReadExReq_mshr_miss_latency 1868560000 # number of ReadExReq MSHR miss cycles
145 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
146 system.cpu.l2cache.ReadExReq_mshr_misses 46714 # number of ReadExReq MSHR misses
147 system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses)
148 system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
149 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
150 system.cpu.l2cache.ReadReq_hits 892653 # number of ReadReq hits
151 system.cpu.l2cache.ReadReq_miss_latency 56472000 # number of ReadReq miss cycles
152 system.cpu.l2cache.ReadReq_miss_rate 0.001215 # miss rate for ReadReq accesses
153 system.cpu.l2cache.ReadReq_misses 1086 # number of ReadReq misses
154 system.cpu.l2cache.ReadReq_mshr_miss_latency 43440000 # number of ReadReq MSHR miss cycles
155 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001215 # mshr miss rate for ReadReq accesses
156 system.cpu.l2cache.ReadReq_mshr_misses 1086 # number of ReadReq MSHR misses
157 system.cpu.l2cache.UpgradeReq_accesses 48257 # number of UpgradeReq accesses(hits+misses)
158 system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
159 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
160 system.cpu.l2cache.UpgradeReq_miss_latency 2509364000 # number of UpgradeReq miss cycles
161 system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
162 system.cpu.l2cache.UpgradeReq_misses 48257 # number of UpgradeReq misses
163 system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1930280000 # number of UpgradeReq MSHR miss cycles
164 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
165 system.cpu.l2cache.UpgradeReq_mshr_misses 48257 # number of UpgradeReq MSHR misses
166 system.cpu.l2cache.Writeback_accesses 94875 # number of Writeback accesses(hits+misses)
167 system.cpu.l2cache.Writeback_hits 94875 # number of Writeback hits
168 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
169 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
170 system.cpu.l2cache.avg_refs 51.559226 # Average number of references to valid blocks.
171 system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
172 system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
173 system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
174 system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
175 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
176 system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses
177 system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
178 system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
179 system.cpu.l2cache.demand_hits 892653 # number of demand (read+write) hits
180 system.cpu.l2cache.demand_miss_latency 2485600000 # number of demand (read+write) miss cycles
181 system.cpu.l2cache.demand_miss_rate 0.050827 # miss rate for demand accesses
182 system.cpu.l2cache.demand_misses 47800 # number of demand (read+write) misses
183 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
184 system.cpu.l2cache.demand_mshr_miss_latency 1912000000 # number of demand (read+write) MSHR miss cycles
185 system.cpu.l2cache.demand_mshr_miss_rate 0.050827 # mshr miss rate for demand accesses
186 system.cpu.l2cache.demand_mshr_misses 47800 # number of demand (read+write) MSHR misses
187 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
188 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
189 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
190 system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses
191 system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
192 system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
193 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
194 system.cpu.l2cache.overall_hits 892653 # number of overall hits
195 system.cpu.l2cache.overall_miss_latency 2485600000 # number of overall miss cycles
196 system.cpu.l2cache.overall_miss_rate 0.050827 # miss rate for overall accesses
197 system.cpu.l2cache.overall_misses 47800 # number of overall misses
198 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
199 system.cpu.l2cache.overall_mshr_miss_latency 1912000000 # number of overall MSHR miss cycles
200 system.cpu.l2cache.overall_mshr_miss_rate 0.050827 # mshr miss rate for overall accesses
201 system.cpu.l2cache.overall_mshr_misses 47800 # number of overall MSHR misses
202 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
203 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
204 system.cpu.l2cache.replacements 891 # number of replacements
205 system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks.
206 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
207 system.cpu.l2cache.tagsinuse 8958.837724 # Cycle average of tags in use
208 system.cpu.l2cache.total_refs 802210 # Total number of references to valid blocks.
209 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
210 system.cpu.l2cache.writebacks 41 # number of writebacks
211 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
212 system.cpu.numCycles 732870812 # number of cpu cycles simulated
213 system.cpu.num_insts 243835278 # Number of instructions executed
214 system.cpu.num_refs 105711442 # Number of memory references
215 system.cpu.workload.PROG:num_syscalls 443 # Number of system calls
217 ---------- End Simulation Statistics ----------
projects / gem5.git / blob