2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.081353 # Number of seconds simulated
4 sim_ticks 81353358500 # Number of ticks simulated
5 sim_freq 1000000000000 # Frequency of simulated ticks
6 host_inst_rate 205113 # Simulator instruction rate (inst/s)
7 host_tick_rate 59982451 # Simulator tick rate (ticks/s)
8 host_mem_usage 365084 # Number of bytes of host memory used
9 host_seconds 1356.29 # Real time elapsed on the host
10 sim_insts 278192519 # Number of instructions simulated
11 system.cpu.workload.num_syscalls 444 # Number of system calls
12 system.cpu.numCycles 162706718 # number of cpu cycles simulated
13 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
14 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
15 system.cpu.BPredUnit.lookups 43478033 # Number of BP lookups
16 system.cpu.BPredUnit.condPredicted 43478033 # Number of conditional branches predicted
17 system.cpu.BPredUnit.condIncorrect 2457578 # Number of conditional branches incorrect
18 system.cpu.BPredUnit.BTBLookups 38773202 # Number of BTB lookups
19 system.cpu.BPredUnit.BTBHits 38222212 # Number of BTB hits
20 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
21 system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
22 system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
23 system.cpu.fetch.icacheStallCycles 30836194 # Number of cycles fetch is stalled on an Icache miss
24 system.cpu.fetch.Insts 225319864 # Number of instructions fetch has processed
25 system.cpu.fetch.Branches 43478033 # Number of branches that fetch encountered
26 system.cpu.fetch.predictedBranches 38222212 # Number of branches that fetch has predicted taken
27 system.cpu.fetch.Cycles 71185003 # Number of cycles fetch has run and was not squashing or blocked
28 system.cpu.fetch.SquashCycles 2631314 # Number of cycles fetch has spent squashing
29 system.cpu.fetch.MiscStallCycles 21 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
30 system.cpu.fetch.CacheLines 30836194 # Number of cache lines fetched
31 system.cpu.fetch.IcacheSquashes 310702 # Number of outstanding Icache misses that were squashed
32 system.cpu.fetch.rateDist::samples 161537602 # Number of instructions fetched each cycle (Total)
33 system.cpu.fetch.rateDist::mean 2.462501 # Number of instructions fetched each cycle (Total)
34 system.cpu.fetch.rateDist::stdev 3.241161 # Number of instructions fetched each cycle (Total)
35 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
36 system.cpu.fetch.rateDist::0 92871455 57.49% 57.49% # Number of instructions fetched each cycle (Total)
37 system.cpu.fetch.rateDist::1 4826864 2.99% 60.48% # Number of instructions fetched each cycle (Total)
38 system.cpu.fetch.rateDist::2 3003358 1.86% 62.34% # Number of instructions fetched each cycle (Total)
39 system.cpu.fetch.rateDist::3 6248204 3.87% 66.21% # Number of instructions fetched each cycle (Total)
40 system.cpu.fetch.rateDist::4 7317456 4.53% 70.74% # Number of instructions fetched each cycle (Total)
41 system.cpu.fetch.rateDist::5 5554189 3.44% 74.18% # Number of instructions fetched each cycle (Total)
42 system.cpu.fetch.rateDist::6 8050336 4.98% 79.16% # Number of instructions fetched each cycle (Total)
43 system.cpu.fetch.rateDist::7 6460332 4.00% 83.16% # Number of instructions fetched each cycle (Total)
44 system.cpu.fetch.rateDist::8 27205408 16.84% 100.00% # Number of instructions fetched each cycle (Total)
45 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
46 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
47 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
48 system.cpu.fetch.rateDist::total 161537602 # Number of instructions fetched each cycle (Total)
49 system.cpu.fetch.branchRate 0.267217 # Number of branch fetches per cycle
50 system.cpu.fetch.rate 1.384822 # Number of inst fetches per cycle
51 system.cpu.decode.IdleCycles 68100520 # Number of cycles decode is idle
52 system.cpu.decode.BlockedCycles 13645788 # Number of cycles decode is blocked
53 system.cpu.decode.RunCycles 66107585 # Number of cycles decode is running
54 system.cpu.decode.UnblockCycles 1213655 # Number of cycles decode is unblocking
55 system.cpu.decode.SquashCycles 12470054 # Number of cycles decode is squashing
56 system.cpu.decode.DecodedInsts 390299102 # Number of instructions handled by decode
57 system.cpu.rename.SquashCycles 12470054 # Number of cycles rename is squashing
58 system.cpu.rename.IdleCycles 72027632 # Number of cycles rename is idle
59 system.cpu.rename.BlockCycles 3012062 # Number of cycles rename is blocking
60 system.cpu.rename.serializeStallCycles 6445 # count of cycles rename stalled for serializing inst
61 system.cpu.rename.RunCycles 63003531 # Number of cycles rename is running
62 system.cpu.rename.UnblockCycles 11017878 # Number of cycles rename is unblocking
63 system.cpu.rename.RenamedInsts 382954672 # Number of instructions processed by rename
64 system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full
65 system.cpu.rename.IQFullEvents 129805 # Number of times rename has blocked due to IQ full
66 system.cpu.rename.LSQFullEvents 9724942 # Number of times rename has blocked due to LSQ full
67 system.cpu.rename.RenamedOperands 343637650 # Number of destination operands rename has renamed
68 system.cpu.rename.RenameLookups 940851472 # Number of register rename lookups that rename has made
69 system.cpu.rename.int_rename_lookups 940850893 # Number of integer rename lookups
70 system.cpu.rename.fp_rename_lookups 579 # Number of floating rename lookups
71 system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed
72 system.cpu.rename.UndoneMaps 95293458 # Number of HB maps that are undone due to squashing
73 system.cpu.rename.serializingInsts 468 # count of serializing insts renamed
74 system.cpu.rename.tempSerializingInsts 462 # count of temporary serializing insts renamed
75 system.cpu.rename.skidInsts 25876087 # count of insts added to the skid buffer
76 system.cpu.memDep0.insertedLoads 121481389 # Number of loads inserted to the mem dependence unit.
77 system.cpu.memDep0.insertedStores 39633547 # Number of stores inserted to the mem dependence unit.
78 system.cpu.memDep0.conflictingLoads 49140895 # Number of conflicting loads.
79 system.cpu.memDep0.conflictingStores 10609784 # Number of conflicting stores.
80 system.cpu.iq.iqInstsAdded 366915906 # Number of instructions added to the IQ (excludes non-spec)
81 system.cpu.iq.iqNonSpecInstsAdded 465 # Number of non-speculative instructions added to the IQ
82 system.cpu.iq.iqInstsIssued 331721300 # Number of instructions issued
83 system.cpu.iq.iqSquashedInstsIssued 173691 # Number of squashed instructions issued
84 system.cpu.iq.iqSquashedInstsExamined 88480232 # Number of squashed instructions iterated over during squash; mainly for profiling
85 system.cpu.iq.iqSquashedOperandsExamined 124860059 # Number of squashed operands that are examined and possibly removed from graph
86 system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed
87 system.cpu.iq.issued_per_cycle::samples 161537602 # Number of insts issued each cycle
88 system.cpu.iq.issued_per_cycle::mean 2.053524 # Number of insts issued each cycle
89 system.cpu.iq.issued_per_cycle::stdev 1.792236 # Number of insts issued each cycle
90 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
91 system.cpu.iq.issued_per_cycle::0 44404154 27.49% 27.49% # Number of insts issued each cycle
92 system.cpu.iq.issued_per_cycle::1 26523670 16.42% 43.91% # Number of insts issued each cycle
93 system.cpu.iq.issued_per_cycle::2 27554042 17.06% 60.97% # Number of insts issued each cycle
94 system.cpu.iq.issued_per_cycle::3 26722697 16.54% 77.51% # Number of insts issued each cycle
95 system.cpu.iq.issued_per_cycle::4 19519009 12.08% 89.59% # Number of insts issued each cycle
96 system.cpu.iq.issued_per_cycle::5 11121773 6.88% 96.48% # Number of insts issued each cycle
97 system.cpu.iq.issued_per_cycle::6 3849891 2.38% 98.86% # Number of insts issued each cycle
98 system.cpu.iq.issued_per_cycle::7 1601720 0.99% 99.85% # Number of insts issued each cycle
99 system.cpu.iq.issued_per_cycle::8 240646 0.15% 100.00% # Number of insts issued each cycle
100 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
101 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
102 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
103 system.cpu.iq.issued_per_cycle::total 161537602 # Number of insts issued each cycle
104 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
105 system.cpu.iq.fu_full::IntAlu 20533 1.17% 1.17% # attempts to use FU when none available
106 system.cpu.iq.fu_full::IntMult 0 0.00% 1.17% # attempts to use FU when none available
107 system.cpu.iq.fu_full::IntDiv 0 0.00% 1.17% # attempts to use FU when none available
108 system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.17% # attempts to use FU when none available
109 system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.17% # attempts to use FU when none available
110 system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.17% # attempts to use FU when none available
111 system.cpu.iq.fu_full::FloatMult 0 0.00% 1.17% # attempts to use FU when none available
112 system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.17% # attempts to use FU when none available
113 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.17% # attempts to use FU when none available
114 system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.17% # attempts to use FU when none available
115 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.17% # attempts to use FU when none available
116 system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.17% # attempts to use FU when none available
117 system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.17% # attempts to use FU when none available
118 system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.17% # attempts to use FU when none available
119 system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.17% # attempts to use FU when none available
120 system.cpu.iq.fu_full::SimdMult 0 0.00% 1.17% # attempts to use FU when none available
121 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.17% # attempts to use FU when none available
122 system.cpu.iq.fu_full::SimdShift 0 0.00% 1.17% # attempts to use FU when none available
123 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.17% # attempts to use FU when none available
124 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.17% # attempts to use FU when none available
125 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.17% # attempts to use FU when none available
126 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.17% # attempts to use FU when none available
127 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.17% # attempts to use FU when none available
128 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.17% # attempts to use FU when none available
129 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.17% # attempts to use FU when none available
130 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.17% # attempts to use FU when none available
131 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.17% # attempts to use FU when none available
132 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.17% # attempts to use FU when none available
133 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.17% # attempts to use FU when none available
134 system.cpu.iq.fu_full::MemRead 1580184 90.40% 91.57% # attempts to use FU when none available
135 system.cpu.iq.fu_full::MemWrite 147351 8.43% 100.00% # attempts to use FU when none available
136 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
137 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
138 system.cpu.iq.FU_type_0::No_OpClass 16703 0.01% 0.01% # Type of FU issued
139 system.cpu.iq.FU_type_0::IntAlu 188283743 56.76% 56.76% # Type of FU issued
140 system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.76% # Type of FU issued
141 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued
142 system.cpu.iq.FU_type_0::FloatAdd 16 0.00% 56.76% # Type of FU issued
143 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued
144 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued
145 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued
146 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued
147 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued
148 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued
149 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued
150 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued
151 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued
152 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued
153 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.76% # Type of FU issued
154 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued
155 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued
156 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued
157 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.76% # Type of FU issued
158 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued
159 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued
160 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued
161 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued
162 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued
163 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued
164 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.76% # Type of FU issued
165 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued
166 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.76% # Type of FU issued
167 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued
168 system.cpu.iq.FU_type_0::MemRead 108606815 32.74% 89.51% # Type of FU issued
169 system.cpu.iq.FU_type_0::MemWrite 34814023 10.49% 100.00% # Type of FU issued
170 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
171 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
172 system.cpu.iq.FU_type_0::total 331721300 # Type of FU issued
173 system.cpu.iq.rate 2.038768 # Inst issue rate
174 system.cpu.iq.fu_busy_cnt 1748068 # FU busy when requested
175 system.cpu.iq.fu_busy_rate 0.005270 # FU busy rate (busy events/executed inst)
176 system.cpu.iq.int_inst_queue_reads 826901753 # Number of integer instruction queue reads
177 system.cpu.iq.int_inst_queue_writes 455618803 # Number of integer instruction queue writes
178 system.cpu.iq.int_inst_queue_wakeup_accesses 324135014 # Number of integer instruction queue wakeup accesses
179 system.cpu.iq.fp_inst_queue_reads 208 # Number of floating instruction queue reads
180 system.cpu.iq.fp_inst_queue_writes 234 # Number of floating instruction queue writes
181 system.cpu.iq.fp_inst_queue_wakeup_accesses 80 # Number of floating instruction queue wakeup accesses
182 system.cpu.iq.int_alu_accesses 333452564 # Number of integer alu accesses
183 system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses
184 system.cpu.iew.lsq.thread0.forwLoads 43811715 # Number of loads that had data forwarded from stores
185 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
186 system.cpu.iew.lsq.thread0.squashedLoads 30702001 # Number of loads squashed
187 system.cpu.iew.lsq.thread0.ignoredResponses 37170 # Number of memory responses ignored because the instruction is squashed
188 system.cpu.iew.lsq.thread0.memOrderViolation 238201 # Number of memory ordering violations
189 system.cpu.iew.lsq.thread0.squashedStores 8193796 # Number of stores squashed
190 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
191 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
192 system.cpu.iew.lsq.thread0.rescheduledLoads 3292 # Number of loads that were rescheduled
193 system.cpu.iew.lsq.thread0.cacheBlocked 14215 # Number of times an access to memory failed due to the cache being blocked
194 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
195 system.cpu.iew.iewSquashCycles 12470054 # Number of cycles IEW is squashing
196 system.cpu.iew.iewBlockCycles 739464 # Number of cycles IEW is blocking
197 system.cpu.iew.iewUnblockCycles 101352 # Number of cycles IEW is unblocking
198 system.cpu.iew.iewDispatchedInsts 366916371 # Number of instructions dispatched to IQ
199 system.cpu.iew.iewDispSquashedInsts 440258 # Number of squashed instructions skipped by dispatch
200 system.cpu.iew.iewDispLoadInsts 121481389 # Number of dispatched load instructions
201 system.cpu.iew.iewDispStoreInsts 39633547 # Number of dispatched store instructions
202 system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
203 system.cpu.iew.iewIQFullEvents 4279 # Number of times the IQ has become full, causing a stall
204 system.cpu.iew.iewLSQFullEvents 66728 # Number of times the LSQ has become full, causing a stall
205 system.cpu.iew.memOrderViolationEvents 238201 # Number of memory order violations
206 system.cpu.iew.predictedTakenIncorrect 2276962 # Number of branches that were predicted taken incorrectly
207 system.cpu.iew.predictedNotTakenIncorrect 580211 # Number of branches that were predicted not taken incorrectly
208 system.cpu.iew.branchMispredicts 2857173 # Number of branch mispredicts detected at execute
209 system.cpu.iew.iewExecutedInsts 327057192 # Number of executed instructions
210 system.cpu.iew.iewExecLoadInsts 107334804 # Number of load instructions executed
211 system.cpu.iew.iewExecSquashedInsts 4664108 # Number of squashed instructions skipped in execute
212 system.cpu.iew.exec_swp 0 # number of swp insts executed
213 system.cpu.iew.exec_nop 0 # number of nop insts executed
214 system.cpu.iew.exec_refs 141680841 # number of memory reference insts executed
215 system.cpu.iew.exec_branches 32801587 # Number of branches executed
216 system.cpu.iew.exec_stores 34346037 # Number of stores executed
217 system.cpu.iew.exec_rate 2.010103 # Inst execution rate
218 system.cpu.iew.wb_sent 325338225 # cumulative count of insts sent to commit
219 system.cpu.iew.wb_count 324135094 # cumulative count of insts written-back
220 system.cpu.iew.wb_producers 242967410 # num instructions producing a value
221 system.cpu.iew.wb_consumers 330454956 # num instructions consuming a value
222 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
223 system.cpu.iew.wb_rate 1.992143 # insts written-back per cycle
224 system.cpu.iew.wb_fanout 0.735251 # average fanout of values written-back
225 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
226 system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions
227 system.cpu.commit.commitSquashedInsts 88730028 # The number of squashed insts skipped by commit
228 system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
229 system.cpu.commit.branchMispredicts 2457587 # The number of times a branch was mispredicted
230 system.cpu.commit.committed_per_cycle::samples 149067548 # Number of insts commited each cycle
231 system.cpu.commit.committed_per_cycle::mean 1.866218 # Number of insts commited each cycle
232 system.cpu.commit.committed_per_cycle::stdev 2.482505 # Number of insts commited each cycle
233 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
234 system.cpu.commit.committed_per_cycle::0 63468061 42.58% 42.58% # Number of insts commited each cycle
235 system.cpu.commit.committed_per_cycle::1 26994600 18.11% 60.69% # Number of insts commited each cycle
236 system.cpu.commit.committed_per_cycle::2 19490262 13.07% 73.76% # Number of insts commited each cycle
237 system.cpu.commit.committed_per_cycle::3 13117480 8.80% 82.56% # Number of insts commited each cycle
238 system.cpu.commit.committed_per_cycle::4 4245570 2.85% 85.41% # Number of insts commited each cycle
239 system.cpu.commit.committed_per_cycle::5 3438248 2.31% 87.71% # Number of insts commited each cycle
240 system.cpu.commit.committed_per_cycle::6 3061065 2.05% 89.77% # Number of insts commited each cycle
241 system.cpu.commit.committed_per_cycle::7 1693051 1.14% 90.90% # Number of insts commited each cycle
242 system.cpu.commit.committed_per_cycle::8 13559211 9.10% 100.00% # Number of insts commited each cycle
243 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
244 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
245 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
246 system.cpu.commit.committed_per_cycle::total 149067548 # Number of insts commited each cycle
247 system.cpu.commit.count 278192519 # Number of instructions committed
248 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
249 system.cpu.commit.refs 122219139 # Number of memory references committed
250 system.cpu.commit.loads 90779388 # Number of loads committed
251 system.cpu.commit.membars 0 # Number of memory barriers committed
252 system.cpu.commit.branches 29309710 # Number of branches committed
253 system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
254 system.cpu.commit.int_insts 278186227 # Number of committed integer instructions.
255 system.cpu.commit.function_calls 0 # Number of function calls committed.
256 system.cpu.commit.bw_lim_events 13559211 # number cycles where commit BW limit reached
257 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
258 system.cpu.rob.rob_reads 502430884 # The number of ROB reads
259 system.cpu.rob.rob_writes 746329282 # The number of ROB writes
260 system.cpu.timesIdled 40054 # Number of times that the entire CPU went into an idle state and unscheduled itself
261 system.cpu.idleCycles 1169116 # Total number of cycles that the CPU has spent unscheduled due to idling
262 system.cpu.committedInsts 278192519 # Number of Instructions Simulated
263 system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated
264 system.cpu.cpi 0.584871 # CPI: Cycles Per Instruction
265 system.cpu.cpi_total 0.584871 # CPI: Total CPI of All Threads
266 system.cpu.ipc 1.709779 # IPC: Instructions Per Cycle
267 system.cpu.ipc_total 1.709779 # IPC: Total IPC of All Threads
268 system.cpu.int_regfile_reads 572576247 # number of integer regfile reads
269 system.cpu.int_regfile_writes 291474006 # number of integer regfile writes
270 system.cpu.fp_regfile_reads 75 # number of floating regfile reads
271 system.cpu.fp_regfile_writes 41 # number of floating regfile writes
272 system.cpu.misc_regfile_reads 211119046 # number of misc regfile reads
273 system.cpu.icache.replacements 60 # number of replacements
274 system.cpu.icache.tagsinuse 811.599985 # Cycle average of tags in use
275 system.cpu.icache.total_refs 30834919 # Total number of references to valid blocks.
276 system.cpu.icache.sampled_refs 1009 # Sample count of references to valid blocks.
277 system.cpu.icache.avg_refs 30559.880079 # Average number of references to valid blocks.
278 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
279 system.cpu.icache.occ_blocks::0 811.599985 # Average occupied blocks per context
280 system.cpu.icache.occ_percent::0 0.396289 # Average percentage of cache occupancy
281 system.cpu.icache.ReadReq_hits 30834919 # number of ReadReq hits
282 system.cpu.icache.demand_hits 30834919 # number of demand (read+write) hits
283 system.cpu.icache.overall_hits 30834919 # number of overall hits
284 system.cpu.icache.ReadReq_misses 1275 # number of ReadReq misses
285 system.cpu.icache.demand_misses 1275 # number of demand (read+write) misses
286 system.cpu.icache.overall_misses 1275 # number of overall misses
287 system.cpu.icache.ReadReq_miss_latency 46105500 # number of ReadReq miss cycles
288 system.cpu.icache.demand_miss_latency 46105500 # number of demand (read+write) miss cycles
289 system.cpu.icache.overall_miss_latency 46105500 # number of overall miss cycles
290 system.cpu.icache.ReadReq_accesses 30836194 # number of ReadReq accesses(hits+misses)
291 system.cpu.icache.demand_accesses 30836194 # number of demand (read+write) accesses
292 system.cpu.icache.overall_accesses 30836194 # number of overall (read+write) accesses
293 system.cpu.icache.ReadReq_miss_rate 0.000041 # miss rate for ReadReq accesses
294 system.cpu.icache.demand_miss_rate 0.000041 # miss rate for demand accesses
295 system.cpu.icache.overall_miss_rate 0.000041 # miss rate for overall accesses
296 system.cpu.icache.ReadReq_avg_miss_latency 36161.176471 # average ReadReq miss latency
297 system.cpu.icache.demand_avg_miss_latency 36161.176471 # average overall miss latency
298 system.cpu.icache.overall_avg_miss_latency 36161.176471 # average overall miss latency
299 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
300 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
301 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
302 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
303 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
304 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
305 system.cpu.icache.fast_writes 0 # number of fast writes performed
306 system.cpu.icache.cache_copies 0 # number of cache copies performed
307 system.cpu.icache.writebacks 0 # number of writebacks
308 system.cpu.icache.ReadReq_mshr_hits 265 # number of ReadReq MSHR hits
309 system.cpu.icache.demand_mshr_hits 265 # number of demand (read+write) MSHR hits
310 system.cpu.icache.overall_mshr_hits 265 # number of overall MSHR hits
311 system.cpu.icache.ReadReq_mshr_misses 1010 # number of ReadReq MSHR misses
312 system.cpu.icache.demand_mshr_misses 1010 # number of demand (read+write) MSHR misses
313 system.cpu.icache.overall_mshr_misses 1010 # number of overall MSHR misses
314 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
315 system.cpu.icache.ReadReq_mshr_miss_latency 35558500 # number of ReadReq MSHR miss cycles
316 system.cpu.icache.demand_mshr_miss_latency 35558500 # number of demand (read+write) MSHR miss cycles
317 system.cpu.icache.overall_mshr_miss_latency 35558500 # number of overall MSHR miss cycles
318 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
319 system.cpu.icache.ReadReq_mshr_miss_rate 0.000033 # mshr miss rate for ReadReq accesses
320 system.cpu.icache.demand_mshr_miss_rate 0.000033 # mshr miss rate for demand accesses
321 system.cpu.icache.overall_mshr_miss_rate 0.000033 # mshr miss rate for overall accesses
322 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35206.435644 # average ReadReq mshr miss latency
323 system.cpu.icache.demand_avg_mshr_miss_latency 35206.435644 # average overall mshr miss latency
324 system.cpu.icache.overall_avg_mshr_miss_latency 35206.435644 # average overall mshr miss latency
325 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
326 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
327 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
328 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
329 system.cpu.dcache.replacements 2073960 # number of replacements
330 system.cpu.dcache.tagsinuse 4075.298640 # Cycle average of tags in use
331 system.cpu.dcache.total_refs 92302253 # Total number of references to valid blocks.
332 system.cpu.dcache.sampled_refs 2078056 # Sample count of references to valid blocks.
333 system.cpu.dcache.avg_refs 44.417597 # Average number of references to valid blocks.
334 system.cpu.dcache.warmup_cycle 30307591000 # Cycle when the warmup percentage was hit.
335 system.cpu.dcache.occ_blocks::0 4075.298640 # Average occupied blocks per context
336 system.cpu.dcache.occ_percent::0 0.994946 # Average percentage of cache occupancy
337 system.cpu.dcache.ReadReq_hits 61099794 # number of ReadReq hits
338 system.cpu.dcache.WriteReq_hits 31202450 # number of WriteReq hits
339 system.cpu.dcache.demand_hits 92302244 # number of demand (read+write) hits
340 system.cpu.dcache.overall_hits 92302244 # number of overall hits
341 system.cpu.dcache.ReadReq_misses 2219212 # number of ReadReq misses
342 system.cpu.dcache.WriteReq_misses 237301 # number of WriteReq misses
343 system.cpu.dcache.demand_misses 2456513 # number of demand (read+write) misses
344 system.cpu.dcache.overall_misses 2456513 # number of overall misses
345 system.cpu.dcache.ReadReq_miss_latency 14180205500 # number of ReadReq miss cycles
346 system.cpu.dcache.WriteReq_miss_latency 4209484208 # number of WriteReq miss cycles
347 system.cpu.dcache.demand_miss_latency 18389689708 # number of demand (read+write) miss cycles
348 system.cpu.dcache.overall_miss_latency 18389689708 # number of overall miss cycles
349 system.cpu.dcache.ReadReq_accesses 63319006 # number of ReadReq accesses(hits+misses)
350 system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
351 system.cpu.dcache.demand_accesses 94758757 # number of demand (read+write) accesses
352 system.cpu.dcache.overall_accesses 94758757 # number of overall (read+write) accesses
353 system.cpu.dcache.ReadReq_miss_rate 0.035048 # miss rate for ReadReq accesses
354 system.cpu.dcache.WriteReq_miss_rate 0.007548 # miss rate for WriteReq accesses
355 system.cpu.dcache.demand_miss_rate 0.025924 # miss rate for demand accesses
356 system.cpu.dcache.overall_miss_rate 0.025924 # miss rate for overall accesses
357 system.cpu.dcache.ReadReq_avg_miss_latency 6389.748028 # average ReadReq miss latency
358 system.cpu.dcache.WriteReq_avg_miss_latency 17739.007455 # average WriteReq miss latency
359 system.cpu.dcache.demand_avg_miss_latency 7486.095009 # average overall miss latency
360 system.cpu.dcache.overall_avg_miss_latency 7486.095009 # average overall miss latency
361 system.cpu.dcache.blocked_cycles::no_mshrs 290000 # number of cycles access was blocked
362 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
363 system.cpu.dcache.blocked::no_mshrs 85 # number of cycles access was blocked
364 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
365 system.cpu.dcache.avg_blocked_cycles::no_mshrs 3411.764706 # average number of cycles each access was blocked
366 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
367 system.cpu.dcache.fast_writes 0 # number of fast writes performed
368 system.cpu.dcache.cache_copies 0 # number of cache copies performed
369 system.cpu.dcache.writebacks 1448049 # number of writebacks
370 system.cpu.dcache.ReadReq_mshr_hits 247154 # number of ReadReq MSHR hits
371 system.cpu.dcache.WriteReq_mshr_hits 131299 # number of WriteReq MSHR hits
372 system.cpu.dcache.demand_mshr_hits 378453 # number of demand (read+write) MSHR hits
373 system.cpu.dcache.overall_mshr_hits 378453 # number of overall MSHR hits
374 system.cpu.dcache.ReadReq_mshr_misses 1972058 # number of ReadReq MSHR misses
375 system.cpu.dcache.WriteReq_mshr_misses 106002 # number of WriteReq MSHR misses
376 system.cpu.dcache.demand_mshr_misses 2078060 # number of demand (read+write) MSHR misses
377 system.cpu.dcache.overall_mshr_misses 2078060 # number of overall MSHR misses
378 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
379 system.cpu.dcache.ReadReq_mshr_miss_latency 5532610500 # number of ReadReq MSHR miss cycles
380 system.cpu.dcache.WriteReq_mshr_miss_latency 1870145708 # number of WriteReq MSHR miss cycles
381 system.cpu.dcache.demand_mshr_miss_latency 7402756208 # number of demand (read+write) MSHR miss cycles
382 system.cpu.dcache.overall_mshr_miss_latency 7402756208 # number of overall MSHR miss cycles
383 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
384 system.cpu.dcache.ReadReq_mshr_miss_rate 0.031145 # mshr miss rate for ReadReq accesses
385 system.cpu.dcache.WriteReq_mshr_miss_rate 0.003372 # mshr miss rate for WriteReq accesses
386 system.cpu.dcache.demand_mshr_miss_rate 0.021930 # mshr miss rate for demand accesses
387 system.cpu.dcache.overall_mshr_miss_rate 0.021930 # mshr miss rate for overall accesses
388 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2805.500903 # average ReadReq mshr miss latency
389 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17642.551159 # average WriteReq mshr miss latency
390 system.cpu.dcache.demand_avg_mshr_miss_latency 3562.339975 # average overall mshr miss latency
391 system.cpu.dcache.overall_avg_mshr_miss_latency 3562.339975 # average overall mshr miss latency
392 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
393 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
394 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
395 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
396 system.cpu.l2cache.replacements 49058 # number of replacements
397 system.cpu.l2cache.tagsinuse 18069.203236 # Cycle average of tags in use
398 system.cpu.l2cache.total_refs 3319340 # Total number of references to valid blocks.
399 system.cpu.l2cache.sampled_refs 77063 # Sample count of references to valid blocks.
400 system.cpu.l2cache.avg_refs 43.073070 # Average number of references to valid blocks.
401 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
402 system.cpu.l2cache.occ_blocks::0 6443.195976 # Average occupied blocks per context
403 system.cpu.l2cache.occ_blocks::1 11626.007260 # Average occupied blocks per context
404 system.cpu.l2cache.occ_percent::0 0.196631 # Average percentage of cache occupancy
405 system.cpu.l2cache.occ_percent::1 0.354798 # Average percentage of cache occupancy
406 system.cpu.l2cache.ReadReq_hits 1938598 # number of ReadReq hits
407 system.cpu.l2cache.Writeback_hits 1448049 # number of Writeback hits
408 system.cpu.l2cache.ReadExReq_hits 63959 # number of ReadExReq hits
409 system.cpu.l2cache.demand_hits 2002557 # number of demand (read+write) hits
410 system.cpu.l2cache.overall_hits 2002557 # number of overall hits
411 system.cpu.l2cache.ReadReq_misses 34456 # number of ReadReq misses
412 system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
413 system.cpu.l2cache.ReadExReq_misses 42055 # number of ReadExReq misses
414 system.cpu.l2cache.demand_misses 76511 # number of demand (read+write) misses
415 system.cpu.l2cache.overall_misses 76511 # number of overall misses
416 system.cpu.l2cache.ReadReq_miss_latency 1178964000 # number of ReadReq miss cycles
417 system.cpu.l2cache.ReadExReq_miss_latency 1437688500 # number of ReadExReq miss cycles
418 system.cpu.l2cache.demand_miss_latency 2616652500 # number of demand (read+write) miss cycles
419 system.cpu.l2cache.overall_miss_latency 2616652500 # number of overall miss cycles
420 system.cpu.l2cache.ReadReq_accesses 1973054 # number of ReadReq accesses(hits+misses)
421 system.cpu.l2cache.Writeback_accesses 1448049 # number of Writeback accesses(hits+misses)
422 system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
423 system.cpu.l2cache.ReadExReq_accesses 106014 # number of ReadExReq accesses(hits+misses)
424 system.cpu.l2cache.demand_accesses 2079068 # number of demand (read+write) accesses
425 system.cpu.l2cache.overall_accesses 2079068 # number of overall (read+write) accesses
426 system.cpu.l2cache.ReadReq_miss_rate 0.017463 # miss rate for ReadReq accesses
427 system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
428 system.cpu.l2cache.ReadExReq_miss_rate 0.396693 # miss rate for ReadExReq accesses
429 system.cpu.l2cache.demand_miss_rate 0.036801 # miss rate for demand accesses
430 system.cpu.l2cache.overall_miss_rate 0.036801 # miss rate for overall accesses
431 system.cpu.l2cache.ReadReq_avg_miss_latency 34216.508010 # average ReadReq miss latency
432 system.cpu.l2cache.ReadExReq_avg_miss_latency 34185.911307 # average ReadExReq miss latency
433 system.cpu.l2cache.demand_avg_miss_latency 34199.690241 # average overall miss latency
434 system.cpu.l2cache.overall_avg_miss_latency 34199.690241 # average overall miss latency
435 system.cpu.l2cache.blocked_cycles::no_mshrs 35000 # number of cycles access was blocked
436 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
437 system.cpu.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked
438 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
439 system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked
440 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
441 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
442 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
443 system.cpu.l2cache.writebacks 29183 # number of writebacks
444 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
445 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
446 system.cpu.l2cache.ReadReq_mshr_misses 34456 # number of ReadReq MSHR misses
447 system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
448 system.cpu.l2cache.ReadExReq_mshr_misses 42055 # number of ReadExReq MSHR misses
449 system.cpu.l2cache.demand_mshr_misses 76511 # number of demand (read+write) MSHR misses
450 system.cpu.l2cache.overall_mshr_misses 76511 # number of overall MSHR misses
451 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
452 system.cpu.l2cache.ReadReq_mshr_miss_latency 1068941000 # number of ReadReq MSHR miss cycles
453 system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
454 system.cpu.l2cache.ReadExReq_mshr_miss_latency 1308447000 # number of ReadExReq MSHR miss cycles
455 system.cpu.l2cache.demand_mshr_miss_latency 2377388000 # number of demand (read+write) MSHR miss cycles
456 system.cpu.l2cache.overall_mshr_miss_latency 2377388000 # number of overall MSHR miss cycles
457 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
458 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017463 # mshr miss rate for ReadReq accesses
459 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
460 system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.396693 # mshr miss rate for ReadExReq accesses
461 system.cpu.l2cache.demand_mshr_miss_rate 0.036801 # mshr miss rate for demand accesses
462 system.cpu.l2cache.overall_mshr_miss_rate 0.036801 # mshr miss rate for overall accesses
463 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31023.363130 # average ReadReq mshr miss latency
464 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
465 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31112.757104 # average ReadExReq mshr miss latency
466 system.cpu.l2cache.demand_avg_mshr_miss_latency 31072.499379 # average overall mshr miss latency
467 system.cpu.l2cache.overall_avg_mshr_miss_latency 31072.499379 # average overall mshr miss latency
468 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
469 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
470 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
471 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
473 ---------- End Simulation Statistics ----------
projects / gem5.git / blob