2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 1130440 # Simulator instruction rate (inst/s)
4 host_mem_usage 330088 # Number of bytes of host memory used
5 host_seconds 238.58 # Real time elapsed on the host
6 host_tick_rate 1550911771 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 269696010 # Number of instructions simulated
9 sim_seconds 0.370011 # Number of seconds simulated
10 sim_ticks 370010840000 # Number of ticks simulated
11 system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses)
12 system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183 # average ReadReq miss latency
13 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183 # average ReadReq mshr miss latency
14 system.cpu.dcache.ReadReq_hits 88818730 # number of ReadReq hits
15 system.cpu.dcache.ReadReq_miss_latency 28849058000 # number of ReadReq miss cycles
16 system.cpu.dcache.ReadReq_miss_rate 0.021599 # miss rate for ReadReq accesses
17 system.cpu.dcache.ReadReq_misses 1960720 # number of ReadReq misses
18 system.cpu.dcache.ReadReq_mshr_miss_latency 22966898000 # number of ReadReq MSHR miss cycles
19 system.cpu.dcache.ReadReq_mshr_miss_rate 0.021599 # mshr miss rate for ReadReq accesses
20 system.cpu.dcache.ReadReq_mshr_misses 1960720 # number of ReadReq MSHR misses
21 system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
22 system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952 # average WriteReq miss latency
23 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815 # average WriteReq mshr miss latency
24 system.cpu.dcache.WriteReq_hits 31333642 # number of WriteReq hits
25 system.cpu.dcache.WriteReq_miss_latency 3268793000 # number of WriteReq miss cycles
26 system.cpu.dcache.WriteReq_miss_rate 0.003375 # miss rate for WriteReq accesses
27 system.cpu.dcache.WriteReq_misses 106109 # number of WriteReq misses
28 system.cpu.dcache.WriteReq_mshr_miss_latency 2950464500 # number of WriteReq MSHR miss cycles
29 system.cpu.dcache.WriteReq_mshr_miss_rate 0.003375 # mshr miss rate for WriteReq accesses
30 system.cpu.dcache.WriteReq_mshr_misses 106109 # number of WriteReq MSHR misses
31 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
32 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
33 system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks.
34 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
35 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
36 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
37 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
38 system.cpu.dcache.cache_copies 0 # number of cache copies performed
39 system.cpu.dcache.demand_accesses 122219201 # number of demand (read+write) accesses
40 system.cpu.dcache.demand_avg_miss_latency 15539.675029 # average overall miss latency
41 system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency
42 system.cpu.dcache.demand_hits 120152372 # number of demand (read+write) hits
43 system.cpu.dcache.demand_miss_latency 32117851000 # number of demand (read+write) miss cycles
44 system.cpu.dcache.demand_miss_rate 0.016911 # miss rate for demand accesses
45 system.cpu.dcache.demand_misses 2066829 # number of demand (read+write) misses
46 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
47 system.cpu.dcache.demand_mshr_miss_latency 25917362500 # number of demand (read+write) MSHR miss cycles
48 system.cpu.dcache.demand_mshr_miss_rate 0.016911 # mshr miss rate for demand accesses
49 system.cpu.dcache.demand_mshr_misses 2066829 # number of demand (read+write) MSHR misses
50 system.cpu.dcache.fast_writes 0 # number of fast writes performed
51 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
52 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
53 system.cpu.dcache.occ_%::0 0.995279 # Average percentage of cache occupancy
54 system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context
55 system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses
56 system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency
57 system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency
58 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
59 system.cpu.dcache.overall_hits 120152372 # number of overall hits
60 system.cpu.dcache.overall_miss_latency 32117851000 # number of overall miss cycles
61 system.cpu.dcache.overall_miss_rate 0.016911 # miss rate for overall accesses
62 system.cpu.dcache.overall_misses 2066829 # number of overall misses
63 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
64 system.cpu.dcache.overall_mshr_miss_latency 25917362500 # number of overall MSHR miss cycles
65 system.cpu.dcache.overall_mshr_miss_rate 0.016911 # mshr miss rate for overall accesses
66 system.cpu.dcache.overall_mshr_misses 2066829 # number of overall MSHR misses
67 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
68 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
69 system.cpu.dcache.replacements 2062733 # number of replacements
70 system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
71 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
72 system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use
73 system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks.
74 system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit.
75 system.cpu.dcache.writebacks 1437080 # number of writebacks
76 system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses)
77 system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
78 system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
79 system.cpu.icache.ReadReq_hits 217695401 # number of ReadReq hits
80 system.cpu.icache.ReadReq_miss_latency 45248000 # number of ReadReq miss cycles
81 system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
82 system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses
83 system.cpu.icache.ReadReq_mshr_miss_latency 42824000 # number of ReadReq MSHR miss cycles
84 system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
85 system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses
86 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
87 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
88 system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
89 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
90 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
91 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
92 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
93 system.cpu.icache.cache_copies 0 # number of cache copies performed
94 system.cpu.icache.demand_accesses 217696209 # number of demand (read+write) accesses
95 system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
96 system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
97 system.cpu.icache.demand_hits 217695401 # number of demand (read+write) hits
98 system.cpu.icache.demand_miss_latency 45248000 # number of demand (read+write) miss cycles
99 system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
100 system.cpu.icache.demand_misses 808 # number of demand (read+write) misses
101 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
102 system.cpu.icache.demand_mshr_miss_latency 42824000 # number of demand (read+write) MSHR miss cycles
103 system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
104 system.cpu.icache.demand_mshr_misses 808 # number of demand (read+write) MSHR misses
105 system.cpu.icache.fast_writes 0 # number of fast writes performed
106 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
107 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
108 system.cpu.icache.occ_%::0 0.325289 # Average percentage of cache occupancy
109 system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context
110 system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses
111 system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
112 system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
113 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
114 system.cpu.icache.overall_hits 217695401 # number of overall hits
115 system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles
116 system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
117 system.cpu.icache.overall_misses 808 # number of overall misses
118 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
119 system.cpu.icache.overall_mshr_miss_latency 42824000 # number of overall MSHR miss cycles
120 system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
121 system.cpu.icache.overall_mshr_misses 808 # number of overall MSHR misses
122 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
123 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
124 system.cpu.icache.replacements 24 # number of replacements
125 system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
126 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
127 system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use
128 system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks.
129 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
130 system.cpu.icache.writebacks 0 # number of writebacks
131 system.cpu.idle_fraction 0 # Percentage of idle cycles
132 system.cpu.l2cache.ReadExReq_accesses 106109 # number of ReadExReq accesses(hits+misses)
133 system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804 # average ReadExReq miss latency
134 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
135 system.cpu.l2cache.ReadExReq_hits 63651 # number of ReadExReq hits
136 system.cpu.l2cache.ReadExReq_miss_latency 2207845500 # number of ReadExReq miss cycles
137 system.cpu.l2cache.ReadExReq_miss_rate 0.400136 # miss rate for ReadExReq accesses
138 system.cpu.l2cache.ReadExReq_misses 42458 # number of ReadExReq misses
139 system.cpu.l2cache.ReadExReq_mshr_miss_latency 1698320000 # number of ReadExReq MSHR miss cycles
140 system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.400136 # mshr miss rate for ReadExReq accesses
141 system.cpu.l2cache.ReadExReq_mshr_misses 42458 # number of ReadExReq MSHR misses
142 system.cpu.l2cache.ReadReq_accesses 1961528 # number of ReadReq accesses(hits+misses)
143 system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
144 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
145 system.cpu.l2cache.ReadReq_hits 1927411 # number of ReadReq hits
146 system.cpu.l2cache.ReadReq_miss_latency 1774084000 # number of ReadReq miss cycles
147 system.cpu.l2cache.ReadReq_miss_rate 0.017393 # miss rate for ReadReq accesses
148 system.cpu.l2cache.ReadReq_misses 34117 # number of ReadReq misses
149 system.cpu.l2cache.ReadReq_mshr_miss_latency 1364680000 # number of ReadReq MSHR miss cycles
150 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017393 # mshr miss rate for ReadReq accesses
151 system.cpu.l2cache.ReadReq_mshr_misses 34117 # number of ReadReq MSHR misses
152 system.cpu.l2cache.Writeback_accesses 1437080 # number of Writeback accesses(hits+misses)
153 system.cpu.l2cache.Writeback_hits 1437080 # number of Writeback hits
154 system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
155 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
156 system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks.
157 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
158 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
159 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
160 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
161 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
162 system.cpu.l2cache.demand_accesses 2067637 # number of demand (read+write) accesses
163 system.cpu.l2cache.demand_avg_miss_latency 52000.385243 # average overall miss latency
164 system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
165 system.cpu.l2cache.demand_hits 1991062 # number of demand (read+write) hits
166 system.cpu.l2cache.demand_miss_latency 3981929500 # number of demand (read+write) miss cycles
167 system.cpu.l2cache.demand_miss_rate 0.037035 # miss rate for demand accesses
168 system.cpu.l2cache.demand_misses 76575 # number of demand (read+write) misses
169 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
170 system.cpu.l2cache.demand_mshr_miss_latency 3063000000 # number of demand (read+write) MSHR miss cycles
171 system.cpu.l2cache.demand_mshr_miss_rate 0.037035 # mshr miss rate for demand accesses
172 system.cpu.l2cache.demand_mshr_misses 76575 # number of demand (read+write) MSHR misses
173 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
174 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
175 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
176 system.cpu.l2cache.occ_%::0 0.199945 # Average percentage of cache occupancy
177 system.cpu.l2cache.occ_%::1 0.368128 # Average percentage of cache occupancy
178 system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context
179 system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context
180 system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses
181 system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency
182 system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
183 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
184 system.cpu.l2cache.overall_hits 1991062 # number of overall hits
185 system.cpu.l2cache.overall_miss_latency 3981929500 # number of overall miss cycles
186 system.cpu.l2cache.overall_miss_rate 0.037035 # miss rate for overall accesses
187 system.cpu.l2cache.overall_misses 76575 # number of overall misses
188 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
189 system.cpu.l2cache.overall_mshr_miss_latency 3063000000 # number of overall MSHR miss cycles
190 system.cpu.l2cache.overall_mshr_miss_rate 0.037035 # mshr miss rate for overall accesses
191 system.cpu.l2cache.overall_mshr_misses 76575 # number of overall MSHR misses
192 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
193 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
194 system.cpu.l2cache.replacements 49212 # number of replacements
195 system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks.
196 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
197 system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use
198 system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks.
199 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
200 system.cpu.l2cache.writebacks 29460 # number of writebacks
201 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
202 system.cpu.numCycles 740021680 # number of cpu cycles simulated
203 system.cpu.num_insts 269696010 # Number of instructions executed
204 system.cpu.num_refs 122219139 # Number of memory references
205 system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
207 ---------- End Simulation Statistics ----------
projects / gem5.git / blob