tests/long/20.parser/ref/arm/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 time_sync_enable=false
   5 time_sync_period=100000000000
   6 time_sync_spin_threshold=100000000
   7
   8 [system]
   9 type=System
  10 children=cpu membus physmem
  11 mem_mode=atomic
  12 memories=system.physmem
  13 num_work_ids=16
  14 physmem=system.physmem
  15 work_begin_ckpt_count=0
  16 work_begin_cpu_id_exit=-1
  17 work_begin_exit_count=0
  18 work_cpus_ckpt_count=0
  19 work_end_ckpt_count=0
  20 work_end_exit_count=0
  21 work_item_id=-1
  22
  23 [system.cpu]
  24 type=DerivO3CPU
  25 children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
  26 BTBEntries=4096
  27 BTBTagSize=16
  28 LFSTSize=1024
  29 LQEntries=32
  30 LSQCheckLoads=true
  31 LSQDepCheckShift=4
  32 RASSize=16
  33 SQEntries=32
  34 SSITSize=1024
  35 activity=0
  36 backComSize=5
  37 cachePorts=200
  38 checker=Null
  39 choiceCtrBits=2
  40 choicePredictorSize=8192
  41 clock=500
  42 commitToDecodeDelay=1
  43 commitToFetchDelay=1
  44 commitToIEWDelay=1
  45 commitToRenameDelay=1
  46 commitWidth=8
  47 cpu_id=0
  48 decodeToFetchDelay=1
  49 decodeToRenameDelay=1
  50 decodeWidth=8
  51 defer_registration=false
  52 dispatchWidth=8
  53 do_checkpoint_insts=true
  54 do_statistics_insts=true
  55 dtb=system.cpu.dtb
  56 fetchToDecodeDelay=1
  57 fetchTrapLatency=1
  58 fetchWidth=8
  59 forwardComSize=5
  60 fuPool=system.cpu.fuPool
  61 function_trace=false
  62 function_trace_start=0
  63 globalCtrBits=2
  64 globalHistoryBits=13
  65 globalPredictorSize=8192
  66 iewToCommitDelay=1
  67 iewToDecodeDelay=1
  68 iewToFetchDelay=1
  69 iewToRenameDelay=1
  70 instShiftAmt=2
  71 issueToExecuteDelay=1
  72 issueWidth=8
  73 itb=system.cpu.itb
  74 localCtrBits=2
  75 localHistoryBits=11
  76 localHistoryTableSize=2048
  77 localPredictorSize=2048
  78 max_insts_all_threads=0
  79 max_insts_any_thread=0
  80 max_loads_all_threads=0
  81 max_loads_any_thread=0
  82 numIQEntries=64
  83 numPhysFloatRegs=256
  84 numPhysIntRegs=256
  85 numROBEntries=192
  86 numRobs=1
  87 numThreads=1
  88 phase=0
  89 predType=tournament
  90 progress_interval=0
  91 renameToDecodeDelay=1
  92 renameToFetchDelay=1
  93 renameToIEWDelay=2
  94 renameToROBDelay=1
  95 renameWidth=8
  96 smtCommitPolicy=RoundRobin
  97 smtFetchPolicy=SingleThread
  98 smtIQPolicy=Partitioned
  99 smtIQThreshold=100
 100 smtLSQPolicy=Partitioned
 101 smtLSQThreshold=100
 102 smtNumFetchingThreads=1
 103 smtROBPolicy=Partitioned
 104 smtROBThreshold=100
 105 squashWidth=8
 106 store_set_clear_period=250000
 107 system=system
 108 tracer=system.cpu.tracer
 109 trapLatency=13
 110 wbDepth=1
 111 wbWidth=8
 112 workload=system.cpu.workload
 113 dcache_port=system.cpu.dcache.cpu_side
 114 icache_port=system.cpu.icache.cpu_side
 115
 116 [system.cpu.dcache]
 117 type=BaseCache
 118 addr_range=0:18446744073709551615
 119 assoc=2
 120 block_size=64
 121 forward_snoops=true
 122 hash_delay=1
 123 is_top_level=true
 124 latency=1000
 125 max_miss_count=0
 126 mshrs=10
 127 num_cpus=1
 128 prefetch_data_accesses_only=false
 129 prefetch_degree=1
 130 prefetch_latency=10000
 131 prefetch_on_access=false
 132 prefetch_past_page=false
 133 prefetch_policy=none
 134 prefetch_serial_squash=false
 135 prefetch_use_cpu_id=true
 136 prefetcher_size=100
 137 prioritizeRequests=false
 138 repl=Null
 139 size=262144
 140 subblock_size=0
 141 tgts_per_mshr=20
 142 trace_addr=0
 143 two_queue=false
 144 write_buffers=8
 145 cpu_side=system.cpu.dcache_port
 146 mem_side=system.cpu.toL2Bus.port[1]
 147
 148 [system.cpu.dtb]
 149 type=ArmTLB
 150 size=64
 151
 152 [system.cpu.fuPool]
 153 type=FUPool
 154 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 155 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 156
 157 [system.cpu.fuPool.FUList0]
 158 type=FUDesc
 159 children=opList
 160 count=6
 161 opList=system.cpu.fuPool.FUList0.opList
 162
 163 [system.cpu.fuPool.FUList0.opList]
 164 type=OpDesc
 165 issueLat=1
 166 opClass=IntAlu
 167 opLat=1
 168
 169 [system.cpu.fuPool.FUList1]
 170 type=FUDesc
 171 children=opList0 opList1
 172 count=2
 173 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 174
 175 [system.cpu.fuPool.FUList1.opList0]
 176 type=OpDesc
 177 issueLat=1
 178 opClass=IntMult
 179 opLat=3
 180
 181 [system.cpu.fuPool.FUList1.opList1]
 182 type=OpDesc
 183 issueLat=19
 184 opClass=IntDiv
 185 opLat=20
 186
 187 [system.cpu.fuPool.FUList2]
 188 type=FUDesc
 189 children=opList0 opList1 opList2
 190 count=4
 191 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 192
 193 [system.cpu.fuPool.FUList2.opList0]
 194 type=OpDesc
 195 issueLat=1
 196 opClass=FloatAdd
 197 opLat=2
 198
 199 [system.cpu.fuPool.FUList2.opList1]
 200 type=OpDesc
 201 issueLat=1
 202 opClass=FloatCmp
 203 opLat=2
 204
 205 [system.cpu.fuPool.FUList2.opList2]
 206 type=OpDesc
 207 issueLat=1
 208 opClass=FloatCvt
 209 opLat=2
 210
 211 [system.cpu.fuPool.FUList3]
 212 type=FUDesc
 213 children=opList0 opList1 opList2
 214 count=2
 215 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 216
 217 [system.cpu.fuPool.FUList3.opList0]
 218 type=OpDesc
 219 issueLat=1
 220 opClass=FloatMult
 221 opLat=4
 222
 223 [system.cpu.fuPool.FUList3.opList1]
 224 type=OpDesc
 225 issueLat=12
 226 opClass=FloatDiv
 227 opLat=12
 228
 229 [system.cpu.fuPool.FUList3.opList2]
 230 type=OpDesc
 231 issueLat=24
 232 opClass=FloatSqrt
 233 opLat=24
 234
 235 [system.cpu.fuPool.FUList4]
 236 type=FUDesc
 237 children=opList
 238 count=0
 239 opList=system.cpu.fuPool.FUList4.opList
 240
 241 [system.cpu.fuPool.FUList4.opList]
 242 type=OpDesc
 243 issueLat=1
 244 opClass=MemRead
 245 opLat=1
 246
 247 [system.cpu.fuPool.FUList5]
 248 type=FUDesc
 249 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 250 count=4
 251 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 252
 253 [system.cpu.fuPool.FUList5.opList00]
 254 type=OpDesc
 255 issueLat=1
 256 opClass=SimdAdd
 257 opLat=1
 258
 259 [system.cpu.fuPool.FUList5.opList01]
 260 type=OpDesc
 261 issueLat=1
 262 opClass=SimdAddAcc
 263 opLat=1
 264
 265 [system.cpu.fuPool.FUList5.opList02]
 266 type=OpDesc
 267 issueLat=1
 268 opClass=SimdAlu
 269 opLat=1
 270
 271 [system.cpu.fuPool.FUList5.opList03]
 272 type=OpDesc
 273 issueLat=1
 274 opClass=SimdCmp
 275 opLat=1
 276
 277 [system.cpu.fuPool.FUList5.opList04]
 278 type=OpDesc
 279 issueLat=1
 280 opClass=SimdCvt
 281 opLat=1
 282
 283 [system.cpu.fuPool.FUList5.opList05]
 284 type=OpDesc
 285 issueLat=1
 286 opClass=SimdMisc
 287 opLat=1
 288
 289 [system.cpu.fuPool.FUList5.opList06]
 290 type=OpDesc
 291 issueLat=1
 292 opClass=SimdMult
 293 opLat=1
 294
 295 [system.cpu.fuPool.FUList5.opList07]
 296 type=OpDesc
 297 issueLat=1
 298 opClass=SimdMultAcc
 299 opLat=1
 300
 301 [system.cpu.fuPool.FUList5.opList08]
 302 type=OpDesc
 303 issueLat=1
 304 opClass=SimdShift
 305 opLat=1
 306
 307 [system.cpu.fuPool.FUList5.opList09]
 308 type=OpDesc
 309 issueLat=1
 310 opClass=SimdShiftAcc
 311 opLat=1
 312
 313 [system.cpu.fuPool.FUList5.opList10]
 314 type=OpDesc
 315 issueLat=1
 316 opClass=SimdSqrt
 317 opLat=1
 318
 319 [system.cpu.fuPool.FUList5.opList11]
 320 type=OpDesc
 321 issueLat=1
 322 opClass=SimdFloatAdd
 323 opLat=1
 324
 325 [system.cpu.fuPool.FUList5.opList12]
 326 type=OpDesc
 327 issueLat=1
 328 opClass=SimdFloatAlu
 329 opLat=1
 330
 331 [system.cpu.fuPool.FUList5.opList13]
 332 type=OpDesc
 333 issueLat=1
 334 opClass=SimdFloatCmp
 335 opLat=1
 336
 337 [system.cpu.fuPool.FUList5.opList14]
 338 type=OpDesc
 339 issueLat=1
 340 opClass=SimdFloatCvt
 341 opLat=1
 342
 343 [system.cpu.fuPool.FUList5.opList15]
 344 type=OpDesc
 345 issueLat=1
 346 opClass=SimdFloatDiv
 347 opLat=1
 348
 349 [system.cpu.fuPool.FUList5.opList16]
 350 type=OpDesc
 351 issueLat=1
 352 opClass=SimdFloatMisc
 353 opLat=1
 354
 355 [system.cpu.fuPool.FUList5.opList17]
 356 type=OpDesc
 357 issueLat=1
 358 opClass=SimdFloatMult
 359 opLat=1
 360
 361 [system.cpu.fuPool.FUList5.opList18]
 362 type=OpDesc
 363 issueLat=1
 364 opClass=SimdFloatMultAcc
 365 opLat=1
 366
 367 [system.cpu.fuPool.FUList5.opList19]
 368 type=OpDesc
 369 issueLat=1
 370 opClass=SimdFloatSqrt
 371 opLat=1
 372
 373 [system.cpu.fuPool.FUList6]
 374 type=FUDesc
 375 children=opList
 376 count=0
 377 opList=system.cpu.fuPool.FUList6.opList
 378
 379 [system.cpu.fuPool.FUList6.opList]
 380 type=OpDesc
 381 issueLat=1
 382 opClass=MemWrite
 383 opLat=1
 384
 385 [system.cpu.fuPool.FUList7]
 386 type=FUDesc
 387 children=opList0 opList1
 388 count=4
 389 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 390
 391 [system.cpu.fuPool.FUList7.opList0]
 392 type=OpDesc
 393 issueLat=1
 394 opClass=MemRead
 395 opLat=1
 396
 397 [system.cpu.fuPool.FUList7.opList1]
 398 type=OpDesc
 399 issueLat=1
 400 opClass=MemWrite
 401 opLat=1
 402
 403 [system.cpu.fuPool.FUList8]
 404 type=FUDesc
 405 children=opList
 406 count=1
 407 opList=system.cpu.fuPool.FUList8.opList
 408
 409 [system.cpu.fuPool.FUList8.opList]
 410 type=OpDesc
 411 issueLat=3
 412 opClass=IprAccess
 413 opLat=3
 414
 415 [system.cpu.icache]
 416 type=BaseCache
 417 addr_range=0:18446744073709551615
 418 assoc=2
 419 block_size=64
 420 forward_snoops=true
 421 hash_delay=1
 422 is_top_level=true
 423 latency=1000
 424 max_miss_count=0
 425 mshrs=10
 426 num_cpus=1
 427 prefetch_data_accesses_only=false
 428 prefetch_degree=1
 429 prefetch_latency=10000
 430 prefetch_on_access=false
 431 prefetch_past_page=false
 432 prefetch_policy=none
 433 prefetch_serial_squash=false
 434 prefetch_use_cpu_id=true
 435 prefetcher_size=100
 436 prioritizeRequests=false
 437 repl=Null
 438 size=131072
 439 subblock_size=0
 440 tgts_per_mshr=20
 441 trace_addr=0
 442 two_queue=false
 443 write_buffers=8
 444 cpu_side=system.cpu.icache_port
 445 mem_side=system.cpu.toL2Bus.port[0]
 446
 447 [system.cpu.itb]
 448 type=ArmTLB
 449 size=64
 450
 451 [system.cpu.l2cache]
 452 type=BaseCache
 453 addr_range=0:18446744073709551615
 454 assoc=2
 455 block_size=64
 456 forward_snoops=true
 457 hash_delay=1
 458 is_top_level=false
 459 latency=1000
 460 max_miss_count=0
 461 mshrs=10
 462 num_cpus=1
 463 prefetch_data_accesses_only=false
 464 prefetch_degree=1
 465 prefetch_latency=10000
 466 prefetch_on_access=false
 467 prefetch_past_page=false
 468 prefetch_policy=none
 469 prefetch_serial_squash=false
 470 prefetch_use_cpu_id=true
 471 prefetcher_size=100
 472 prioritizeRequests=false
 473 repl=Null
 474 size=2097152
 475 subblock_size=0
 476 tgts_per_mshr=5
 477 trace_addr=0
 478 two_queue=false
 479 write_buffers=8
 480 cpu_side=system.cpu.toL2Bus.port[2]
 481 mem_side=system.membus.port[1]
 482
 483 [system.cpu.toL2Bus]
 484 type=Bus
 485 block_size=64
 486 bus_id=0
 487 clock=1000
 488 header_cycles=1
 489 use_default_range=false
 490 width=64
 491 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 492
 493 [system.cpu.tracer]
 494 type=ExeTracer
 495
 496 [system.cpu.workload]
 497 type=LiveProcess
 498 cmd=parser 2.1.dict -batch
 499 cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
 500 egid=100
 501 env=
 502 errout=cerr
 503 euid=100
 504 executable=/dist/m5/cpu2000/binaries/arm/linux/parser
 505 gid=100
 506 input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 507 max_stack_size=67108864
 508 output=cout
 509 pid=100
 510 ppid=99
 511 simpoint=114600000000
 512 system=system
 513 uid=100
 514
 515 [system.membus]
 516 type=Bus
 517 block_size=64
 518 bus_id=0
 519 clock=1000
 520 header_cycles=1
 521 use_default_range=false
 522 width=64
 523 port=system.physmem.port[0] system.cpu.l2cache.mem_side
 524
 525 [system.physmem]
 526 type=PhysicalMemory
 527 file=
 528 latency=30000
 529 latency_var=0
 530 null=false
 531 range=0:134217727
 532 zero=false
 533 port=system.membus.port[0]
 534