2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 588841 # Simulator instruction rate (inst/s)
4 host_mem_usage 206816 # Number of bytes of host memory used
5 host_seconds 2539.72 # Real time elapsed on the host
6 host_tick_rate 941590971 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 1495492697 # Number of instructions simulated
9 sim_seconds 2.391380 # Number of seconds simulated
10 sim_ticks 2391380378000 # Number of ticks simulated
11 system.cpu.dcache.ReadReq_accesses 384102203 # number of ReadReq accesses(hits+misses)
12 system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency
13 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency
14 system.cpu.dcache.ReadReq_hits 382375390 # number of ReadReq hits
15 system.cpu.dcache.ReadReq_miss_latency 41698498000 # number of ReadReq miss cycles
16 system.cpu.dcache.ReadReq_miss_rate 0.004496 # miss rate for ReadReq accesses
17 system.cpu.dcache.ReadReq_misses 1726813 # number of ReadReq misses
18 system.cpu.dcache.ReadReq_mshr_miss_latency 36518057000 # number of ReadReq MSHR miss cycles
19 system.cpu.dcache.ReadReq_mshr_miss_rate 0.004496 # mshr miss rate for ReadReq accesses
20 system.cpu.dcache.ReadReq_mshr_misses 1726813 # number of ReadReq MSHR misses
21 system.cpu.dcache.WriteReq_accesses 149160208 # number of WriteReq accesses(hits+misses)
22 system.cpu.dcache.WriteReq_avg_miss_latency 55999.912355 # average WriteReq miss latency
23 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.912355 # average WriteReq mshr miss latency
24 system.cpu.dcache.WriteReq_hits 147694060 # number of WriteReq hits
25 system.cpu.dcache.WriteReq_miss_latency 82104159500 # number of WriteReq miss cycles
26 system.cpu.dcache.WriteReq_miss_rate 0.009829 # miss rate for WriteReq accesses
27 system.cpu.dcache.WriteReq_misses 1466148 # number of WriteReq misses
28 system.cpu.dcache.WriteReq_mshr_miss_latency 77705715500 # number of WriteReq MSHR miss cycles
29 system.cpu.dcache.WriteReq_mshr_miss_rate 0.009829 # mshr miss rate for WriteReq accesses
30 system.cpu.dcache.WriteReq_mshr_misses 1466148 # number of WriteReq MSHR misses
31 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
32 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
33 system.cpu.dcache.avg_refs 210.782586 # Average number of references to valid blocks.
34 system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
35 system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
36 system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
37 system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
38 system.cpu.dcache.cache_copies 0 # number of cache copies performed
39 system.cpu.dcache.demand_accesses 533262411 # number of demand (read+write) accesses
40 system.cpu.dcache.demand_avg_miss_latency 38773.620317 # average overall miss latency
41 system.cpu.dcache.demand_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency
42 system.cpu.dcache.demand_hits 530069450 # number of demand (read+write) hits
43 system.cpu.dcache.demand_miss_latency 123802657500 # number of demand (read+write) miss cycles
44 system.cpu.dcache.demand_miss_rate 0.005988 # miss rate for demand accesses
45 system.cpu.dcache.demand_misses 3192961 # number of demand (read+write) misses
46 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
47 system.cpu.dcache.demand_mshr_miss_latency 114223772500 # number of demand (read+write) MSHR miss cycles
48 system.cpu.dcache.demand_mshr_miss_rate 0.005988 # mshr miss rate for demand accesses
49 system.cpu.dcache.demand_mshr_misses 3192961 # number of demand (read+write) MSHR misses
50 system.cpu.dcache.fast_writes 0 # number of fast writes performed
51 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
52 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
53 system.cpu.dcache.overall_accesses 533262411 # number of overall (read+write) accesses
54 system.cpu.dcache.overall_avg_miss_latency 38773.620317 # average overall miss latency
55 system.cpu.dcache.overall_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency
56 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
57 system.cpu.dcache.overall_hits 530069450 # number of overall hits
58 system.cpu.dcache.overall_miss_latency 123802657500 # number of overall miss cycles
59 system.cpu.dcache.overall_miss_rate 0.005988 # miss rate for overall accesses
60 system.cpu.dcache.overall_misses 3192961 # number of overall misses
61 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
62 system.cpu.dcache.overall_mshr_miss_latency 114223772500 # number of overall MSHR miss cycles
63 system.cpu.dcache.overall_mshr_miss_rate 0.005988 # mshr miss rate for overall accesses
64 system.cpu.dcache.overall_mshr_misses 3192961 # number of overall MSHR misses
65 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
66 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
67 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
68 system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
69 system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
70 system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
71 system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
72 system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
73 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
74 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
75 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
76 system.cpu.dcache.replacements 2513875 # number of replacements
77 system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks.
78 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
79 system.cpu.dcache.tagsinuse 4086.151092 # Cycle average of tags in use
80 system.cpu.dcache.total_refs 530744440 # Total number of references to valid blocks.
81 system.cpu.dcache.warmup_cycle 12270587000 # Cycle when the warmup percentage was hit.
82 system.cpu.dcache.writebacks 1463913 # number of writebacks
83 system.cpu.icache.ReadReq_accesses 1737374915 # number of ReadReq accesses(hits+misses)
84 system.cpu.icache.ReadReq_avg_miss_latency 48415.215073 # average ReadReq miss latency
85 system.cpu.icache.ReadReq_avg_mshr_miss_latency 45415.215073 # average ReadReq mshr miss latency
86 system.cpu.icache.ReadReq_hits 1737372102 # number of ReadReq hits
87 system.cpu.icache.ReadReq_miss_latency 136192000 # number of ReadReq miss cycles
88 system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses
89 system.cpu.icache.ReadReq_misses 2813 # number of ReadReq misses
90 system.cpu.icache.ReadReq_mshr_miss_latency 127753000 # number of ReadReq MSHR miss cycles
91 system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
92 system.cpu.icache.ReadReq_mshr_misses 2813 # number of ReadReq MSHR misses
93 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
94 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
95 system.cpu.icache.avg_refs 617622.503377 # Average number of references to valid blocks.
96 system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
97 system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
98 system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
99 system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
100 system.cpu.icache.cache_copies 0 # number of cache copies performed
101 system.cpu.icache.demand_accesses 1737374915 # number of demand (read+write) accesses
102 system.cpu.icache.demand_avg_miss_latency 48415.215073 # average overall miss latency
103 system.cpu.icache.demand_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency
104 system.cpu.icache.demand_hits 1737372102 # number of demand (read+write) hits
105 system.cpu.icache.demand_miss_latency 136192000 # number of demand (read+write) miss cycles
106 system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses
107 system.cpu.icache.demand_misses 2813 # number of demand (read+write) misses
108 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
109 system.cpu.icache.demand_mshr_miss_latency 127753000 # number of demand (read+write) MSHR miss cycles
110 system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
111 system.cpu.icache.demand_mshr_misses 2813 # number of demand (read+write) MSHR misses
112 system.cpu.icache.fast_writes 0 # number of fast writes performed
113 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
114 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
115 system.cpu.icache.overall_accesses 1737374915 # number of overall (read+write) accesses
116 system.cpu.icache.overall_avg_miss_latency 48415.215073 # average overall miss latency
117 system.cpu.icache.overall_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency
118 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
119 system.cpu.icache.overall_hits 1737372102 # number of overall hits
120 system.cpu.icache.overall_miss_latency 136192000 # number of overall miss cycles
121 system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses
122 system.cpu.icache.overall_misses 2813 # number of overall misses
123 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
124 system.cpu.icache.overall_mshr_miss_latency 127753000 # number of overall MSHR miss cycles
125 system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
126 system.cpu.icache.overall_mshr_misses 2813 # number of overall MSHR misses
127 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
128 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
129 system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
130 system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
131 system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
132 system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
133 system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
134 system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
135 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
136 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
137 system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
138 system.cpu.icache.replacements 1253 # number of replacements
139 system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks.
140 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
141 system.cpu.icache.tagsinuse 873.848519 # Cycle average of tags in use
142 system.cpu.icache.total_refs 1737372102 # Total number of references to valid blocks.
143 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
144 system.cpu.icache.writebacks 0 # number of writebacks
145 system.cpu.idle_fraction 0 # Percentage of idle cycles
146 system.cpu.l2cache.ReadExReq_accesses 791158 # number of ReadExReq accesses(hits+misses)
147 system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014536 # average ReadExReq miss latency
148 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
149 system.cpu.l2cache.ReadExReq_miss_latency 41140227500 # number of ReadExReq miss cycles
150 system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
151 system.cpu.l2cache.ReadExReq_misses 791158 # number of ReadExReq misses
152 system.cpu.l2cache.ReadExReq_mshr_miss_latency 31646320000 # number of ReadExReq MSHR miss cycles
153 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
154 system.cpu.l2cache.ReadExReq_mshr_misses 791158 # number of ReadExReq MSHR misses
155 system.cpu.l2cache.ReadReq_accesses 1729626 # number of ReadReq accesses(hits+misses)
156 system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
157 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
158 system.cpu.l2cache.ReadReq_hits 1310104 # number of ReadReq hits
159 system.cpu.l2cache.ReadReq_miss_latency 21815144000 # number of ReadReq miss cycles
160 system.cpu.l2cache.ReadReq_miss_rate 0.242551 # miss rate for ReadReq accesses
161 system.cpu.l2cache.ReadReq_misses 419522 # number of ReadReq misses
162 system.cpu.l2cache.ReadReq_mshr_miss_latency 16780880000 # number of ReadReq MSHR miss cycles
163 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242551 # mshr miss rate for ReadReq accesses
164 system.cpu.l2cache.ReadReq_mshr_misses 419522 # number of ReadReq MSHR misses
165 system.cpu.l2cache.UpgradeReq_accesses 674990 # number of UpgradeReq accesses(hits+misses)
166 system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.214655 # average UpgradeReq miss latency
167 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
168 system.cpu.l2cache.UpgradeReq_miss_latency 35092200000 # number of UpgradeReq miss cycles
169 system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
170 system.cpu.l2cache.UpgradeReq_misses 674990 # number of UpgradeReq misses
171 system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26999600000 # number of UpgradeReq MSHR miss cycles
172 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
173 system.cpu.l2cache.UpgradeReq_mshr_misses 674990 # number of UpgradeReq MSHR misses
174 system.cpu.l2cache.Writeback_accesses 1463913 # number of Writeback accesses(hits+misses)
175 system.cpu.l2cache.Writeback_hits 1463913 # number of Writeback hits
176 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
177 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
178 system.cpu.l2cache.avg_refs 3.428071 # Average number of references to valid blocks.
179 system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
180 system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
181 system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
182 system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
183 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
184 system.cpu.l2cache.demand_accesses 2520784 # number of demand (read+write) accesses
185 system.cpu.l2cache.demand_avg_miss_latency 52000.009499 # average overall miss latency
186 system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
187 system.cpu.l2cache.demand_hits 1310104 # number of demand (read+write) hits
188 system.cpu.l2cache.demand_miss_latency 62955371500 # number of demand (read+write) miss cycles
189 system.cpu.l2cache.demand_miss_rate 0.480279 # miss rate for demand accesses
190 system.cpu.l2cache.demand_misses 1210680 # number of demand (read+write) misses
191 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
192 system.cpu.l2cache.demand_mshr_miss_latency 48427200000 # number of demand (read+write) MSHR miss cycles
193 system.cpu.l2cache.demand_mshr_miss_rate 0.480279 # mshr miss rate for demand accesses
194 system.cpu.l2cache.demand_mshr_misses 1210680 # number of demand (read+write) MSHR misses
195 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
196 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
197 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
198 system.cpu.l2cache.overall_accesses 2520784 # number of overall (read+write) accesses
199 system.cpu.l2cache.overall_avg_miss_latency 52000.009499 # average overall miss latency
200 system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
201 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
202 system.cpu.l2cache.overall_hits 1310104 # number of overall hits
203 system.cpu.l2cache.overall_miss_latency 62955371500 # number of overall miss cycles
204 system.cpu.l2cache.overall_miss_rate 0.480279 # miss rate for overall accesses
205 system.cpu.l2cache.overall_misses 1210680 # number of overall misses
206 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
207 system.cpu.l2cache.overall_mshr_miss_latency 48427200000 # number of overall MSHR miss cycles
208 system.cpu.l2cache.overall_mshr_miss_rate 0.480279 # mshr miss rate for overall accesses
209 system.cpu.l2cache.overall_mshr_misses 1210680 # number of overall MSHR misses
210 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
211 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
212 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
213 system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
214 system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
215 system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
216 system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
217 system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
218 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
219 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
220 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
221 system.cpu.l2cache.replacements 663512 # number of replacements
222 system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks.
223 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
224 system.cpu.l2cache.tagsinuse 17171.686632 # Cycle average of tags in use
225 system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks.
226 system.cpu.l2cache.warmup_cycle 1313099811000 # Cycle when the warmup percentage was hit.
227 system.cpu.l2cache.writebacks 481430 # number of writebacks
228 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
229 system.cpu.numCycles 4782760756 # number of cpu cycles simulated
230 system.cpu.num_insts 1495492697 # Number of instructions executed
231 system.cpu.num_refs 533549000 # Number of memory references
232 system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
234 ---------- End Simulation Statistics ----------
projects / gem5.git / blob