2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 80651 # Simulator instruction rate (inst/s)
4 host_mem_usage 263088 # Number of bytes of host memory used
5 host_seconds 22860.92 # Real time elapsed on the host
6 host_tick_rate 48422649 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 1843755906 # Number of instructions simulated
9 sim_seconds 1.106986 # Number of seconds simulated
10 sim_ticks 1106986295500 # Number of ticks simulated
11 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
12 system.cpu.BPredUnit.BTBHits 334577290 # Number of BTB hits
13 system.cpu.BPredUnit.BTBLookups 553224059 # Number of BTB lookups
14 system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
15 system.cpu.BPredUnit.condIncorrect 46883846 # Number of conditional branches incorrect
16 system.cpu.BPredUnit.condPredicted 562377080 # Number of conditional branches predicted
17 system.cpu.BPredUnit.lookups 562377080 # Number of BP lookups
18 system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
19 system.cpu.commit.COM:branches 258172659 # Number of branches committed
20 system.cpu.commit.COM:bw_lim_events 41405243 # number cycles where commit BW limit reached
21 system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
22 system.cpu.commit.COM:committed_per_cycle::samples 2026424997 # Number of insts commited each cycle
23 system.cpu.commit.COM:committed_per_cycle::mean 0.909862 # Number of insts commited each cycle
24 system.cpu.commit.COM:committed_per_cycle::stdev 1.566343 # Number of insts commited each cycle
25 system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
26 system.cpu.commit.COM:committed_per_cycle::0 1126460027 55.59% 55.59% # Number of insts commited each cycle
27 system.cpu.commit.COM:committed_per_cycle::1 528416767 26.08% 81.66% # Number of insts commited each cycle
28 system.cpu.commit.COM:committed_per_cycle::2 168171926 8.30% 89.96% # Number of insts commited each cycle
29 system.cpu.commit.COM:committed_per_cycle::3 70727286 3.49% 93.45% # Number of insts commited each cycle
30 system.cpu.commit.COM:committed_per_cycle::4 47338473 2.34% 95.79% # Number of insts commited each cycle
31 system.cpu.commit.COM:committed_per_cycle::5 23657956 1.17% 96.96% # Number of insts commited each cycle
32 system.cpu.commit.COM:committed_per_cycle::6 13792404 0.68% 97.64% # Number of insts commited each cycle
33 system.cpu.commit.COM:committed_per_cycle::7 6454915 0.32% 97.96% # Number of insts commited each cycle
34 system.cpu.commit.COM:committed_per_cycle::8 41405243 2.04% 100.00% # Number of insts commited each cycle
35 system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
36 system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
37 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
38 system.cpu.commit.COM:committed_per_cycle::total 2026424997 # Number of insts commited each cycle
39 system.cpu.commit.COM:count 1843766922 # Number of instructions committed
40 system.cpu.commit.COM:fp_insts 52289415 # Number of committed floating point instructions.
41 system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
42 system.cpu.commit.COM:int_insts 1619025870 # Number of committed integer instructions.
43 system.cpu.commit.COM:loads 631405848 # Number of loads committed
44 system.cpu.commit.COM:membars 0 # Number of memory barriers committed
45 system.cpu.commit.COM:refs 908401145 # Number of memory references committed
46 system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
47 system.cpu.commit.branchMispredicts 84212929 # The number of times a branch was mispredicted
48 system.cpu.commit.commitCommittedInsts 1843766922 # The number of committed instructions
49 system.cpu.commit.commitNonSpecStalls 188261 # The number of times commit has been forced to stall to communicate backwards
50 system.cpu.commit.commitSquashedInsts 1168824477 # The number of squashed insts skipped by commit
51 system.cpu.committedInsts 1843755906 # Number of Instructions Simulated
52 system.cpu.committedInsts_total 1843755906 # Number of Instructions Simulated
53 system.cpu.cpi 1.200795 # CPI: Cycles Per Instruction
54 system.cpu.cpi_total 1.200795 # CPI: Total CPI of All Threads
55 system.cpu.dcache.ReadReq_accesses 714254563 # number of ReadReq accesses(hits+misses)
56 system.cpu.dcache.ReadReq_avg_miss_latency 34305.782527 # average ReadReq miss latency
57 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34068.836467 # average ReadReq mshr miss latency
58 system.cpu.dcache.ReadReq_hits 712322726 # number of ReadReq hits
59 system.cpu.dcache.ReadReq_miss_latency 66273180000 # number of ReadReq miss cycles
60 system.cpu.dcache.ReadReq_miss_rate 0.002705 # miss rate for ReadReq accesses
61 system.cpu.dcache.ReadReq_misses 1931837 # number of ReadReq misses
62 system.cpu.dcache.ReadReq_mshr_hits 467831 # number of ReadReq MSHR hits
63 system.cpu.dcache.ReadReq_mshr_miss_latency 49876981000 # number of ReadReq MSHR miss cycles
64 system.cpu.dcache.ReadReq_mshr_miss_rate 0.002050 # mshr miss rate for ReadReq accesses
65 system.cpu.dcache.ReadReq_mshr_misses 1464006 # number of ReadReq MSHR misses
66 system.cpu.dcache.WriteReq_accesses 276945664 # number of WriteReq accesses(hits+misses)
67 system.cpu.dcache.WriteReq_avg_miss_latency 35173.008313 # average WriteReq miss latency
68 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32580.155094 # average WriteReq mshr miss latency
69 system.cpu.dcache.WriteReq_hits 276142350 # number of WriteReq hits
70 system.cpu.dcache.WriteReq_miss_latency 28254970000 # number of WriteReq miss cycles
71 system.cpu.dcache.WriteReq_miss_rate 0.002901 # miss rate for WriteReq accesses
72 system.cpu.dcache.WriteReq_misses 803314 # number of WriteReq misses
73 system.cpu.dcache.WriteReq_mshr_hits 730842 # number of WriteReq MSHR hits
74 system.cpu.dcache.WriteReq_mshr_miss_latency 2361149000 # number of WriteReq MSHR miss cycles
75 system.cpu.dcache.WriteReq_mshr_miss_rate 0.000262 # mshr miss rate for WriteReq accesses
76 system.cpu.dcache.WriteReq_mshr_misses 72472 # number of WriteReq MSHR misses
77 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
78 system.cpu.dcache.avg_blocked_cycles::no_targets 10666.666667 # average number of cycles each access was blocked
79 system.cpu.dcache.avg_refs 643.332595 # Average number of references to valid blocks.
80 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
81 system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked
82 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
83 system.cpu.dcache.blocked_cycles::no_targets 32000 # number of cycles access was blocked
84 system.cpu.dcache.cache_copies 0 # number of cache copies performed
85 system.cpu.dcache.demand_accesses 991200227 # number of demand (read+write) accesses
86 system.cpu.dcache.demand_avg_miss_latency 34560.486788 # average overall miss latency
87 system.cpu.dcache.demand_avg_mshr_miss_latency 33998.618919 # average overall mshr miss latency
88 system.cpu.dcache.demand_hits 988465076 # number of demand (read+write) hits
89 system.cpu.dcache.demand_miss_latency 94528150000 # number of demand (read+write) miss cycles
90 system.cpu.dcache.demand_miss_rate 0.002759 # miss rate for demand accesses
91 system.cpu.dcache.demand_misses 2735151 # number of demand (read+write) misses
92 system.cpu.dcache.demand_mshr_hits 1198673 # number of demand (read+write) MSHR hits
93 system.cpu.dcache.demand_mshr_miss_latency 52238130000 # number of demand (read+write) MSHR miss cycles
94 system.cpu.dcache.demand_mshr_miss_rate 0.001550 # mshr miss rate for demand accesses
95 system.cpu.dcache.demand_mshr_misses 1536478 # number of demand (read+write) MSHR misses
96 system.cpu.dcache.fast_writes 0 # number of fast writes performed
97 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
98 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
99 system.cpu.dcache.occ_%::0 0.999786 # Average percentage of cache occupancy
100 system.cpu.dcache.occ_blocks::0 4095.125005 # Average occupied blocks per context
101 system.cpu.dcache.overall_accesses 991200227 # number of overall (read+write) accesses
102 system.cpu.dcache.overall_avg_miss_latency 34560.486788 # average overall miss latency
103 system.cpu.dcache.overall_avg_mshr_miss_latency 33998.618919 # average overall mshr miss latency
104 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
105 system.cpu.dcache.overall_hits 988465076 # number of overall hits
106 system.cpu.dcache.overall_miss_latency 94528150000 # number of overall miss cycles
107 system.cpu.dcache.overall_miss_rate 0.002759 # miss rate for overall accesses
108 system.cpu.dcache.overall_misses 2735151 # number of overall misses
109 system.cpu.dcache.overall_mshr_hits 1198673 # number of overall MSHR hits
110 system.cpu.dcache.overall_mshr_miss_latency 52238130000 # number of overall MSHR miss cycles
111 system.cpu.dcache.overall_mshr_miss_rate 0.001550 # mshr miss rate for overall accesses
112 system.cpu.dcache.overall_mshr_misses 1536478 # number of overall MSHR misses
113 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
114 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
115 system.cpu.dcache.replacements 1532380 # number of replacements
116 system.cpu.dcache.sampled_refs 1536476 # Sample count of references to valid blocks.
117 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
118 system.cpu.dcache.tagsinuse 4095.125005 # Cycle average of tags in use
119 system.cpu.dcache.total_refs 988465092 # Total number of references to valid blocks.
120 system.cpu.dcache.warmup_cycle 341948000 # Cycle when the warmup percentage was hit.
121 system.cpu.dcache.writebacks 106863 # number of writebacks
122 system.cpu.decode.DECODE:BlockedCycles 223702819 # Number of cycles decode is blocked
123 system.cpu.decode.DECODE:DecodedInsts 3748475941 # Number of instructions handled by decode
124 system.cpu.decode.DECODE:IdleCycles 853302516 # Number of cycles decode is idle
125 system.cpu.decode.DECODE:RunCycles 949015542 # Number of cycles decode is running
126 system.cpu.decode.DECODE:SquashCycles 187283447 # Number of cycles decode is squashing
127 system.cpu.decode.DECODE:UnblockCycles 404118 # Number of cycles decode is unblocking
128 system.cpu.dtb.accesses 0 # DTB accesses
129 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
130 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
131 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
132 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
133 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
134 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
135 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
136 system.cpu.dtb.hits 0 # DTB hits
137 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
138 system.cpu.dtb.inst_hits 0 # ITB inst hits
139 system.cpu.dtb.inst_misses 0 # ITB inst misses
140 system.cpu.dtb.misses 0 # DTB misses
141 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
142 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
143 system.cpu.dtb.read_accesses 0 # DTB read accesses
144 system.cpu.dtb.read_hits 0 # DTB read hits
145 system.cpu.dtb.read_misses 0 # DTB read misses
146 system.cpu.dtb.write_accesses 0 # DTB write accesses
147 system.cpu.dtb.write_hits 0 # DTB write hits
148 system.cpu.dtb.write_misses 0 # DTB write misses
149 system.cpu.fetch.Branches 562377080 # Number of branches that fetch encountered
150 system.cpu.fetch.CacheLines 400588374 # Number of cache lines fetched
151 system.cpu.fetch.Cycles 1002800662 # Number of cycles fetch has run and was not squashing or blocked
152 system.cpu.fetch.IcacheSquashes 11586077 # Number of outstanding Icache misses that were squashed
153 system.cpu.fetch.Insts 2972268197 # Number of instructions fetch has processed
154 system.cpu.fetch.MiscStallCycles 34317 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
155 system.cpu.fetch.SquashCycles 86966870 # Number of cycles fetch has spent squashing
156 system.cpu.fetch.branchRate 0.254013 # Number of branch fetches per cycle
157 system.cpu.fetch.icacheStallCycles 400588374 # Number of cycles fetch is stalled on an Icache miss
158 system.cpu.fetch.predictedBranches 334577290 # Number of branches that fetch has predicted taken
159 system.cpu.fetch.rate 1.342505 # Number of inst fetches per cycle
160 system.cpu.fetch.rateDist::samples 2213708442 # Number of instructions fetched each cycle (Total)
161 system.cpu.fetch.rateDist::mean 1.777306 # Number of instructions fetched each cycle (Total)
162 system.cpu.fetch.rateDist::stdev 2.798612 # Number of instructions fetched each cycle (Total)
163 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
164 system.cpu.fetch.rateDist::0 1213776792 54.83% 54.83% # Number of instructions fetched each cycle (Total)
165 system.cpu.fetch.rateDist::1 388415260 17.55% 72.38% # Number of instructions fetched each cycle (Total)
166 system.cpu.fetch.rateDist::2 93122307 4.21% 76.58% # Number of instructions fetched each cycle (Total)
167 system.cpu.fetch.rateDist::3 48895921 2.21% 78.79% # Number of instructions fetched each cycle (Total)
168 system.cpu.fetch.rateDist::4 60943546 2.75% 81.54% # Number of instructions fetched each cycle (Total)
169 system.cpu.fetch.rateDist::5 76981670 3.48% 85.02% # Number of instructions fetched each cycle (Total)
170 system.cpu.fetch.rateDist::6 16173405 0.73% 85.75% # Number of instructions fetched each cycle (Total)
171 system.cpu.fetch.rateDist::7 35829919 1.62% 87.37% # Number of instructions fetched each cycle (Total)
172 system.cpu.fetch.rateDist::8 279569622 12.63% 100.00% # Number of instructions fetched each cycle (Total)
173 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
174 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
175 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
176 system.cpu.fetch.rateDist::total 2213708442 # Number of instructions fetched each cycle (Total)
177 system.cpu.fp_regfile_reads 66048246 # number of floating regfile reads
178 system.cpu.fp_regfile_writes 52282096 # number of floating regfile writes
179 system.cpu.icache.ReadReq_accesses 400588374 # number of ReadReq accesses(hits+misses)
180 system.cpu.icache.ReadReq_avg_miss_latency 8967.427082 # average ReadReq miss latency
181 system.cpu.icache.ReadReq_avg_mshr_miss_latency 5871.293987 # average ReadReq mshr miss latency
182 system.cpu.icache.ReadReq_hits 400557689 # number of ReadReq hits
183 system.cpu.icache.ReadReq_miss_latency 275165500 # number of ReadReq miss cycles
184 system.cpu.icache.ReadReq_miss_rate 0.000077 # miss rate for ReadReq accesses
185 system.cpu.icache.ReadReq_misses 30685 # number of ReadReq misses
186 system.cpu.icache.ReadReq_mshr_hits 1813 # number of ReadReq MSHR hits
187 system.cpu.icache.ReadReq_mshr_miss_latency 169516000 # number of ReadReq MSHR miss cycles
188 system.cpu.icache.ReadReq_mshr_miss_rate 0.000072 # mshr miss rate for ReadReq accesses
189 system.cpu.icache.ReadReq_mshr_misses 28872 # number of ReadReq MSHR misses
190 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
191 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
192 system.cpu.icache.avg_refs 13875.010877 # Average number of references to valid blocks.
193 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
194 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
195 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
196 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
197 system.cpu.icache.cache_copies 0 # number of cache copies performed
198 system.cpu.icache.demand_accesses 400588374 # number of demand (read+write) accesses
199 system.cpu.icache.demand_avg_miss_latency 8967.427082 # average overall miss latency
200 system.cpu.icache.demand_avg_mshr_miss_latency 5871.293987 # average overall mshr miss latency
201 system.cpu.icache.demand_hits 400557689 # number of demand (read+write) hits
202 system.cpu.icache.demand_miss_latency 275165500 # number of demand (read+write) miss cycles
203 system.cpu.icache.demand_miss_rate 0.000077 # miss rate for demand accesses
204 system.cpu.icache.demand_misses 30685 # number of demand (read+write) misses
205 system.cpu.icache.demand_mshr_hits 1813 # number of demand (read+write) MSHR hits
206 system.cpu.icache.demand_mshr_miss_latency 169516000 # number of demand (read+write) MSHR miss cycles
207 system.cpu.icache.demand_mshr_miss_rate 0.000072 # mshr miss rate for demand accesses
208 system.cpu.icache.demand_mshr_misses 28872 # number of demand (read+write) MSHR misses
209 system.cpu.icache.fast_writes 0 # number of fast writes performed
210 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
211 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
212 system.cpu.icache.occ_%::0 0.814790 # Average percentage of cache occupancy
213 system.cpu.icache.occ_blocks::0 1668.688980 # Average occupied blocks per context
214 system.cpu.icache.overall_accesses 400588374 # number of overall (read+write) accesses
215 system.cpu.icache.overall_avg_miss_latency 8967.427082 # average overall miss latency
216 system.cpu.icache.overall_avg_mshr_miss_latency 5871.293987 # average overall mshr miss latency
217 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
218 system.cpu.icache.overall_hits 400557689 # number of overall hits
219 system.cpu.icache.overall_miss_latency 275165500 # number of overall miss cycles
220 system.cpu.icache.overall_miss_rate 0.000077 # miss rate for overall accesses
221 system.cpu.icache.overall_misses 30685 # number of overall misses
222 system.cpu.icache.overall_mshr_hits 1813 # number of overall MSHR hits
223 system.cpu.icache.overall_mshr_miss_latency 169516000 # number of overall MSHR miss cycles
224 system.cpu.icache.overall_mshr_miss_rate 0.000072 # mshr miss rate for overall accesses
225 system.cpu.icache.overall_mshr_misses 28872 # number of overall MSHR misses
226 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
227 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
228 system.cpu.icache.replacements 27162 # number of replacements
229 system.cpu.icache.sampled_refs 28869 # Sample count of references to valid blocks.
230 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
231 system.cpu.icache.tagsinuse 1668.688980 # Cycle average of tags in use
232 system.cpu.icache.total_refs 400557689 # Total number of references to valid blocks.
233 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
234 system.cpu.icache.writebacks 0 # number of writebacks
235 system.cpu.idleCycles 264150 # Total number of cycles that the CPU has spent unscheduled due to idling
236 system.cpu.iew.EXEC:branches 328211891 # Number of branches executed
237 system.cpu.iew.EXEC:nop 104784 # number of nop insts executed
238 system.cpu.iew.EXEC:rate 1.050105 # Inst execution rate
239 system.cpu.iew.EXEC:refs 1122138306 # number of memory reference insts executed
240 system.cpu.iew.EXEC:stores 367853547 # Number of stores executed
241 system.cpu.iew.EXEC:swp 0 # number of swp insts executed
242 system.cpu.iew.WB:consumers 2149736970 # num instructions consuming a value
243 system.cpu.iew.WB:count 2244737126 # cumulative count of insts written-back
244 system.cpu.iew.WB:fanout 0.548413 # average fanout of values written-back
245 system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
246 system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
247 system.cpu.iew.WB:producers 1178943946 # num instructions producing a value
248 system.cpu.iew.WB:rate 1.013896 # insts written-back per cycle
249 system.cpu.iew.WB:sent 2266943895 # cumulative count of insts sent to commit
250 system.cpu.iew.branchMispredicts 93876953 # Number of branch mispredicts detected at execute
251 system.cpu.iew.iewBlockCycles 4821399 # Number of cycles IEW is blocking
252 system.cpu.iew.iewDispLoadInsts 976823889 # Number of dispatched load instructions
253 system.cpu.iew.iewDispNonSpecInsts 9835077 # Number of dispatched non-speculative instructions
254 system.cpu.iew.iewDispSquashedInsts 65011197 # Number of squashed instructions skipped by dispatch
255 system.cpu.iew.iewDispStoreInsts 487070109 # Number of dispatched store instructions
256 system.cpu.iew.iewDispatchedInsts 3012606198 # Number of instructions dispatched to IQ
257 system.cpu.iew.iewExecLoadInsts 754284759 # Number of load instructions executed
258 system.cpu.iew.iewExecSquashedInsts 120224771 # Number of squashed instructions skipped in execute
259 system.cpu.iew.iewExecutedInsts 2324903771 # Number of executed instructions
260 system.cpu.iew.iewIQFullEvents 971459 # Number of times the IQ has become full, causing a stall
261 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
262 system.cpu.iew.iewLSQFullEvents 242 # Number of times the LSQ has become full, causing a stall
263 system.cpu.iew.iewSquashCycles 187283447 # Number of cycles IEW is squashing
264 system.cpu.iew.iewUnblockCycles 1560865 # Number of cycles IEW is unblocking
265 system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
266 system.cpu.iew.lsq.thread.0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked
267 system.cpu.iew.lsq.thread.0.forwLoads 12454380 # Number of loads that had data forwarded from stores
268 system.cpu.iew.lsq.thread.0.ignoredResponses 4593 # Number of memory responses ignored because the instruction is squashed
269 system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
270 system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
271 system.cpu.iew.lsq.thread.0.memOrderViolation 2755264 # Number of memory ordering violations
272 system.cpu.iew.lsq.thread.0.rescheduledLoads 1382 # Number of loads that were rescheduled
273 system.cpu.iew.lsq.thread.0.squashedLoads 345418040 # Number of loads squashed
274 system.cpu.iew.lsq.thread.0.squashedStores 210074812 # Number of stores squashed
275 system.cpu.iew.memOrderViolationEvents 2755264 # Number of memory order violations
276 system.cpu.iew.predictedNotTakenIncorrect 45729465 # Number of branches that were predicted not taken incorrectly
277 system.cpu.iew.predictedTakenIncorrect 48147488 # Number of branches that were predicted taken incorrectly
278 system.cpu.int_regfile_reads 5403649891 # number of integer regfile reads
279 system.cpu.int_regfile_writes 1668305360 # number of integer regfile writes
280 system.cpu.ipc 0.832782 # IPC: Instructions Per Cycle
281 system.cpu.ipc_total 0.832782 # IPC: Total IPC of All Threads
282 system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
283 system.cpu.iq.ISSUE:FU_type_0::IntAlu 1195859034 48.91% 48.91% # Type of FU issued
284 system.cpu.iq.ISSUE:FU_type_0::IntMult 11168379 0.46% 49.36% # Type of FU issued
285 system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 49.36% # Type of FU issued
286 system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 49.36% # Type of FU issued
287 system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 49.36% # Type of FU issued
288 system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 49.36% # Type of FU issued
289 system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 49.36% # Type of FU issued
290 system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 49.36% # Type of FU issued
291 system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 49.36% # Type of FU issued
292 system.cpu.iq.ISSUE:FU_type_0::SimdAdd 16846 0.00% 49.37% # Type of FU issued
293 system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 49.37% # Type of FU issued
294 system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 49.37% # Type of FU issued
295 system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 49.37% # Type of FU issued
296 system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 49.37% # Type of FU issued
297 system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 49.37% # Type of FU issued
298 system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 49.37% # Type of FU issued
299 system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 49.37% # Type of FU issued
300 system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 49.37% # Type of FU issued
301 system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 49.37% # Type of FU issued
302 system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 49.37% # Type of FU issued
303 system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 1375289 0.06% 49.42% # Type of FU issued
304 system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 49.42% # Type of FU issued
305 system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 6876473 0.28% 49.70% # Type of FU issued
306 system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 5501179 0.22% 49.93% # Type of FU issued
307 system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 49.93% # Type of FU issued
308 system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 23390230 0.96% 50.88% # Type of FU issued
309 system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 50.88% # Type of FU issued
310 system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 50.88% # Type of FU issued
311 system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 50.88% # Type of FU issued
312 system.cpu.iq.ISSUE:FU_type_0::MemRead 793077280 32.43% 83.32% # Type of FU issued
313 system.cpu.iq.ISSUE:FU_type_0::MemWrite 407863832 16.68% 100.00% # Type of FU issued
314 system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
315 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
316 system.cpu.iq.ISSUE:FU_type_0::total 2445128542 # Type of FU issued
317 system.cpu.iq.ISSUE:fu_busy_cnt 60724253 # FU busy when requested
318 system.cpu.iq.ISSUE:fu_busy_rate 0.024835 # FU busy rate (busy events/executed inst)
319 system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
320 system.cpu.iq.ISSUE:fu_full::IntAlu 336 0.00% 0.00% # attempts to use FU when none available
321 system.cpu.iq.ISSUE:fu_full::IntMult 24113 0.04% 0.04% # attempts to use FU when none available
322 system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available
323 system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available
324 system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.04% # attempts to use FU when none available
325 system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.04% # attempts to use FU when none available
326 system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.04% # attempts to use FU when none available
327 system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.04% # attempts to use FU when none available
328 system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.04% # attempts to use FU when none available
329 system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.04% # attempts to use FU when none available
330 system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.04% # attempts to use FU when none available
331 system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.04% # attempts to use FU when none available
332 system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.04% # attempts to use FU when none available
333 system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.04% # attempts to use FU when none available
334 system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.04% # attempts to use FU when none available
335 system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.04% # attempts to use FU when none available
336 system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.04% # attempts to use FU when none available
337 system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available
338 system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available
339 system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available
340 system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.04% # attempts to use FU when none available
341 system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.04% # attempts to use FU when none available
342 system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.04% # attempts to use FU when none available
343 system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.04% # attempts to use FU when none available
344 system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.04% # attempts to use FU when none available
345 system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.04% # attempts to use FU when none available
346 system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.04% # attempts to use FU when none available
347 system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.04% # attempts to use FU when none available
348 system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.04% # attempts to use FU when none available
349 system.cpu.iq.ISSUE:fu_full::MemRead 44167441 72.73% 72.77% # attempts to use FU when none available
350 system.cpu.iq.ISSUE:fu_full::MemWrite 16532363 27.23% 100.00% # attempts to use FU when none available
351 system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
352 system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
353 system.cpu.iq.ISSUE:issued_per_cycle::samples 2213708442 # Number of insts issued each cycle
354 system.cpu.iq.ISSUE:issued_per_cycle::mean 1.104540 # Number of insts issued each cycle
355 system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.422226 # Number of insts issued each cycle
356 system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
357 system.cpu.iq.ISSUE:issued_per_cycle::0 1044209874 47.17% 47.17% # Number of insts issued each cycle
358 system.cpu.iq.ISSUE:issued_per_cycle::1 536089548 24.22% 71.39% # Number of insts issued each cycle
359 system.cpu.iq.ISSUE:issued_per_cycle::2 282659967 12.77% 84.16% # Number of insts issued each cycle
360 system.cpu.iq.ISSUE:issued_per_cycle::3 162995448 7.36% 91.52% # Number of insts issued each cycle
361 system.cpu.iq.ISSUE:issued_per_cycle::4 122130271 5.52% 97.04% # Number of insts issued each cycle
362 system.cpu.iq.ISSUE:issued_per_cycle::5 40278652 1.82% 98.86% # Number of insts issued each cycle
363 system.cpu.iq.ISSUE:issued_per_cycle::6 15378668 0.69% 99.55% # Number of insts issued each cycle
364 system.cpu.iq.ISSUE:issued_per_cycle::7 7181748 0.32% 99.87% # Number of insts issued each cycle
365 system.cpu.iq.ISSUE:issued_per_cycle::8 2784266 0.13% 100.00% # Number of insts issued each cycle
366 system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
367 system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
368 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
369 system.cpu.iq.ISSUE:issued_per_cycle::total 2213708442 # Number of insts issued each cycle
370 system.cpu.iq.ISSUE:rate 1.104408 # Inst issue rate
371 system.cpu.iq.fp_alu_accesses 64689412 # Number of floating point alu accesses
372 system.cpu.iq.fp_inst_queue_reads 126628637 # Number of floating instruction queue reads
373 system.cpu.iq.fp_inst_queue_wakeup_accesses 56420382 # Number of floating instruction queue wakeup accesses
374 system.cpu.iq.fp_inst_queue_writes 101846831 # Number of floating instruction queue writes
375 system.cpu.iq.int_alu_accesses 2441163383 # Number of integer alu accesses
376 system.cpu.iq.int_inst_queue_reads 7046405646 # Number of integer instruction queue reads
377 system.cpu.iq.int_inst_queue_wakeup_accesses 2188316744 # Number of integer instruction queue wakeup accesses
378 system.cpu.iq.int_inst_queue_writes 4055199620 # Number of integer instruction queue writes
379 system.cpu.iq.iqInstsAdded 3002666337 # Number of instructions added to the IQ (excludes non-spec)
380 system.cpu.iq.iqInstsIssued 2445128542 # Number of instructions issued
381 system.cpu.iq.iqNonSpecInstsAdded 9835077 # Number of non-speculative instructions added to the IQ
382 system.cpu.iq.iqSquashedInstsExamined 1141792420 # Number of squashed instructions iterated over during squash; mainly for profiling
383 system.cpu.iq.iqSquashedInstsIssued 8344504 # Number of squashed instructions issued
384 system.cpu.iq.iqSquashedNonSpecRemoved 9646816 # Number of squashed non-spec instructions that were removed
385 system.cpu.iq.iqSquashedOperandsExamined 2082844826 # Number of squashed operands that are examined and possibly removed from graph
386 system.cpu.itb.accesses 0 # DTB accesses
387 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
388 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
389 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
390 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
391 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
392 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
393 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
394 system.cpu.itb.hits 0 # DTB hits
395 system.cpu.itb.inst_accesses 0 # ITB inst accesses
396 system.cpu.itb.inst_hits 0 # ITB inst hits
397 system.cpu.itb.inst_misses 0 # ITB inst misses
398 system.cpu.itb.misses 0 # DTB misses
399 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
400 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
401 system.cpu.itb.read_accesses 0 # DTB read accesses
402 system.cpu.itb.read_hits 0 # DTB read hits
403 system.cpu.itb.read_misses 0 # DTB read misses
404 system.cpu.itb.write_accesses 0 # DTB write accesses
405 system.cpu.itb.write_hits 0 # DTB write hits
406 system.cpu.itb.write_misses 0 # DTB write misses
407 system.cpu.l2cache.ReadExReq_accesses 72470 # number of ReadExReq accesses(hits+misses)
408 system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.335527 # average ReadExReq miss latency
409 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.225657 # average ReadExReq mshr miss latency
410 system.cpu.l2cache.ReadExReq_hits 6383 # number of ReadExReq hits
411 system.cpu.l2cache.ReadExReq_miss_latency 2279891500 # number of ReadExReq miss cycles
412 system.cpu.l2cache.ReadExReq_miss_rate 0.911922 # miss rate for ReadExReq accesses
413 system.cpu.l2cache.ReadExReq_misses 66087 # number of ReadExReq misses
414 system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048778000 # number of ReadExReq MSHR miss cycles
415 system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.911922 # mshr miss rate for ReadExReq accesses
416 system.cpu.l2cache.ReadExReq_mshr_misses 66087 # number of ReadExReq MSHR misses
417 system.cpu.l2cache.ReadReq_accesses 1492876 # number of ReadReq accesses(hits+misses)
418 system.cpu.l2cache.ReadReq_avg_miss_latency 34237.383587 # average ReadReq miss latency
419 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.264277 # average ReadReq mshr miss latency
420 system.cpu.l2cache.ReadReq_hits 77656 # number of ReadReq hits
421 system.cpu.l2cache.ReadReq_miss_latency 48453430000 # number of ReadReq miss cycles
422 system.cpu.l2cache.ReadReq_miss_rate 0.947982 # miss rate for ReadReq accesses
423 system.cpu.l2cache.ReadReq_misses 1415220 # number of ReadReq misses
424 system.cpu.l2cache.ReadReq_mshr_hits 39 # number of ReadReq MSHR hits
425 system.cpu.l2cache.ReadReq_mshr_miss_latency 43870985000 # number of ReadReq MSHR miss cycles
426 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.947956 # mshr miss rate for ReadReq accesses
427 system.cpu.l2cache.ReadReq_mshr_misses 1415181 # number of ReadReq MSHR misses
428 system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses)
429 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
430 system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
431 system.cpu.l2cache.UpgradeReq_misses 2 # number of UpgradeReq misses
432 system.cpu.l2cache.UpgradeReq_mshr_miss_latency 62000 # number of UpgradeReq MSHR miss cycles
433 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
434 system.cpu.l2cache.UpgradeReq_mshr_misses 2 # number of UpgradeReq MSHR misses
435 system.cpu.l2cache.Writeback_accesses 106863 # number of Writeback accesses(hits+misses)
436 system.cpu.l2cache.Writeback_hits 106863 # number of Writeback hits
437 system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
438 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
439 system.cpu.l2cache.avg_refs 0.056843 # Average number of references to valid blocks.
440 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
441 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
442 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
443 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
444 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
445 system.cpu.l2cache.demand_accesses 1565346 # number of demand (read+write) accesses
446 system.cpu.l2cache.demand_avg_miss_latency 34249.025692 # average overall miss latency
447 system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.307169 # average overall mshr miss latency
448 system.cpu.l2cache.demand_hits 84039 # number of demand (read+write) hits
449 system.cpu.l2cache.demand_miss_latency 50733321500 # number of demand (read+write) miss cycles
450 system.cpu.l2cache.demand_miss_rate 0.946313 # miss rate for demand accesses
451 system.cpu.l2cache.demand_misses 1481307 # number of demand (read+write) misses
452 system.cpu.l2cache.demand_mshr_hits 39 # number of demand (read+write) MSHR hits
453 system.cpu.l2cache.demand_mshr_miss_latency 45919763000 # number of demand (read+write) MSHR miss cycles
454 system.cpu.l2cache.demand_mshr_miss_rate 0.946288 # mshr miss rate for demand accesses
455 system.cpu.l2cache.demand_mshr_misses 1481268 # number of demand (read+write) MSHR misses
456 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
457 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
458 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
459 system.cpu.l2cache.occ_%::0 0.884785 # Average percentage of cache occupancy
460 system.cpu.l2cache.occ_%::1 0.091201 # Average percentage of cache occupancy
461 system.cpu.l2cache.occ_blocks::0 28992.645122 # Average occupied blocks per context
462 system.cpu.l2cache.occ_blocks::1 2988.461105 # Average occupied blocks per context
463 system.cpu.l2cache.overall_accesses 1565346 # number of overall (read+write) accesses
464 system.cpu.l2cache.overall_avg_miss_latency 34249.025692 # average overall miss latency
465 system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.307169 # average overall mshr miss latency
466 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
467 system.cpu.l2cache.overall_hits 84039 # number of overall hits
468 system.cpu.l2cache.overall_miss_latency 50733321500 # number of overall miss cycles
469 system.cpu.l2cache.overall_miss_rate 0.946313 # miss rate for overall accesses
470 system.cpu.l2cache.overall_misses 1481307 # number of overall misses
471 system.cpu.l2cache.overall_mshr_hits 39 # number of overall MSHR hits
472 system.cpu.l2cache.overall_mshr_miss_latency 45919763000 # number of overall MSHR miss cycles
473 system.cpu.l2cache.overall_mshr_miss_rate 0.946288 # mshr miss rate for overall accesses
474 system.cpu.l2cache.overall_mshr_misses 1481268 # number of overall MSHR misses
475 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
476 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
477 system.cpu.l2cache.replacements 1479999 # number of replacements
478 system.cpu.l2cache.sampled_refs 1512721 # Sample count of references to valid blocks.
479 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
480 system.cpu.l2cache.tagsinuse 31981.106227 # Cycle average of tags in use
481 system.cpu.l2cache.total_refs 85987 # Total number of references to valid blocks.
482 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
483 system.cpu.l2cache.writebacks 66099 # number of writebacks
484 system.cpu.memDep0.conflictingLoads 48375882 # Number of conflicting loads.
485 system.cpu.memDep0.conflictingStores 167873780 # Number of conflicting stores.
486 system.cpu.memDep0.insertedLoads 976823889 # Number of loads inserted to the mem dependence unit.
487 system.cpu.memDep0.insertedStores 487070109 # Number of stores inserted to the mem dependence unit.
488 system.cpu.misc_regfile_reads 4207984132 # number of misc regfile reads
489 system.cpu.misc_regfile_writes 14227476 # number of misc regfile writes
490 system.cpu.numCycles 2213972592 # number of cpu cycles simulated
491 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
492 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
493 system.cpu.rename.RENAME:BlockCycles 17658494 # Number of cycles rename is blocking
494 system.cpu.rename.RENAME:CommittedMaps 1482327508 # Number of HB maps that are committed
495 system.cpu.rename.RENAME:IQFullEvents 4825678 # Number of times rename has blocked due to IQ full
496 system.cpu.rename.RENAME:IdleCycles 919120367 # Number of cycles rename is idle
497 system.cpu.rename.RENAME:LSQFullEvents 8406320 # Number of times rename has blocked due to LSQ full
498 system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full
499 system.cpu.rename.RENAME:RenameLookups 9255846830 # Number of register rename lookups that rename has made
500 system.cpu.rename.RENAME:RenamedInsts 3353421825 # Number of instructions processed by rename
501 system.cpu.rename.RENAME:RenamedOperands 2685986513 # Number of destination operands rename has renamed
502 system.cpu.rename.RENAME:RunCycles 880460594 # Number of cycles rename is running
503 system.cpu.rename.RENAME:SquashCycles 187283447 # Number of cycles rename is squashing
504 system.cpu.rename.RENAME:UnblockCycles 23975324 # Number of cycles rename is unblocking
505 system.cpu.rename.RENAME:UndoneMaps 1203659002 # Number of HB maps that are undone due to squashing
506 system.cpu.rename.RENAME:fp_rename_lookups 485863672 # Number of floating rename lookups
507 system.cpu.rename.RENAME:int_rename_lookups 8769983158 # Number of integer rename lookups
508 system.cpu.rename.RENAME:serializeStallCycles 185210216 # count of cycles rename stalled for serializing inst
509 system.cpu.rename.RENAME:serializingInsts 19466962 # count of serializing insts renamed
510 system.cpu.rename.RENAME:skidInsts 226114383 # count of insts added to the skid buffer
511 system.cpu.rename.RENAME:tempSerializingInsts 13965391 # count of temporary serializing insts renamed
512 system.cpu.rob.rob_reads 4997592808 # The number of ROB reads
513 system.cpu.rob.rob_writes 6212468368 # The number of ROB writes
514 system.cpu.timesIdled 87017 # Number of times that the entire CPU went into an idle state and unscheduled itself
515 system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls
517 ---------- End Simulation Statistics ----------
projects / gem5.git / blob