ARM: Add regression tests
[gem5.git] / tests / long / 40.perlbmk / ref / arm / linux / simple-atomic / stats.txt
1
2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 2704949 # Simulator instruction rate (inst/s)
4 host_mem_usage 202656 # Number of bytes of host memory used
5 host_seconds 680.13 # Real time elapsed on the host
6 host_tick_rate 1356804201 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 1839728999 # Number of instructions simulated
9 sim_seconds 0.922809 # Number of seconds simulated
10 sim_ticks 922809447000 # Number of ticks simulated
11 system.cpu.dtb.accesses 0 # DTB accesses
12 system.cpu.dtb.hits 0 # DTB hits
13 system.cpu.dtb.misses 0 # DTB misses
14 system.cpu.dtb.read_accesses 0 # DTB read accesses
15 system.cpu.dtb.read_hits 0 # DTB read hits
16 system.cpu.dtb.read_misses 0 # DTB read misses
17 system.cpu.dtb.write_accesses 0 # DTB write accesses
18 system.cpu.dtb.write_hits 0 # DTB write hits
19 system.cpu.dtb.write_misses 0 # DTB write misses
20 system.cpu.idle_fraction 0 # Percentage of idle cycles
21 system.cpu.itb.accesses 0 # DTB accesses
22 system.cpu.itb.hits 0 # DTB hits
23 system.cpu.itb.misses 0 # DTB misses
24 system.cpu.itb.read_accesses 0 # DTB read accesses
25 system.cpu.itb.read_hits 0 # DTB read hits
26 system.cpu.itb.read_misses 0 # DTB read misses
27 system.cpu.itb.write_accesses 0 # DTB write accesses
28 system.cpu.itb.write_hits 0 # DTB write hits
29 system.cpu.itb.write_misses 0 # DTB write misses
30 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
31 system.cpu.numCycles 1845618895 # number of cpu cycles simulated
32 system.cpu.num_insts 1839728999 # Number of instructions executed
33 system.cpu.num_refs 908401146 # Number of memory references
34 system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls
35
36 ---------- End Simulation Statistics ----------