2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 933614 # Simulator instruction rate (inst/s)
4 host_mem_usage 266072 # Number of bytes of host memory used
5 host_seconds 2007.52 # Real time elapsed on the host
6 host_tick_rate 1180515097 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 1874244950 # Number of instructions simulated
9 sim_seconds 2.369902 # Number of seconds simulated
10 sim_ticks 2369901960000 # Number of ticks simulated
11 system.cpu.dcache.LoadLockedReq_accesses 9985 # number of LoadLockedReq accesses(hits+misses)
12 system.cpu.dcache.LoadLockedReq_hits 9985 # number of LoadLockedReq hits
13 system.cpu.dcache.ReadReq_accesses 620335414 # number of ReadReq accesses(hits+misses)
14 system.cpu.dcache.ReadReq_avg_miss_latency 54574.204602 # average ReadReq miss latency
15 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51574.204602 # average ReadReq mshr miss latency
16 system.cpu.dcache.ReadReq_hits 618874541 # number of ReadReq hits
17 system.cpu.dcache.ReadReq_miss_latency 79725982000 # number of ReadReq miss cycles
18 system.cpu.dcache.ReadReq_miss_rate 0.002355 # miss rate for ReadReq accesses
19 system.cpu.dcache.ReadReq_misses 1460873 # number of ReadReq misses
20 system.cpu.dcache.ReadReq_mshr_miss_latency 75343363000 # number of ReadReq MSHR miss cycles
21 system.cpu.dcache.ReadReq_mshr_miss_rate 0.002355 # mshr miss rate for ReadReq accesses
22 system.cpu.dcache.ReadReq_mshr_misses 1460873 # number of ReadReq MSHR misses
23 system.cpu.dcache.StoreCondReq_accesses 9985 # number of StoreCondReq accesses(hits+misses)
24 system.cpu.dcache.StoreCondReq_hits 9985 # number of StoreCondReq hits
25 system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses)
26 system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235 # average WriteReq miss latency
27 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235 # average WriteReq mshr miss latency
28 system.cpu.dcache.WriteReq_hits 276862898 # number of WriteReq hits
29 system.cpu.dcache.WriteReq_miss_latency 3794826000 # number of WriteReq miss cycles
30 system.cpu.dcache.WriteReq_miss_rate 0.000263 # miss rate for WriteReq accesses
31 system.cpu.dcache.WriteReq_misses 72780 # number of WriteReq misses
32 system.cpu.dcache.WriteReq_mshr_miss_latency 3576486000 # number of WriteReq MSHR miss cycles
33 system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses
34 system.cpu.dcache.WriteReq_mshr_misses 72780 # number of WriteReq MSHR misses
35 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
36 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
37 system.cpu.dcache.avg_refs 584.067849 # Average number of references to valid blocks.
38 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
39 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
40 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
41 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
42 system.cpu.dcache.cache_copies 0 # number of cache copies performed
43 system.cpu.dcache.demand_accesses 897271092 # number of demand (read+write) accesses
44 system.cpu.dcache.demand_avg_miss_latency 54458.738711 # average overall miss latency
45 system.cpu.dcache.demand_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency
46 system.cpu.dcache.demand_hits 895737439 # number of demand (read+write) hits
47 system.cpu.dcache.demand_miss_latency 83520808000 # number of demand (read+write) miss cycles
48 system.cpu.dcache.demand_miss_rate 0.001709 # miss rate for demand accesses
49 system.cpu.dcache.demand_misses 1533653 # number of demand (read+write) misses
50 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
51 system.cpu.dcache.demand_mshr_miss_latency 78919849000 # number of demand (read+write) MSHR miss cycles
52 system.cpu.dcache.demand_mshr_miss_rate 0.001709 # mshr miss rate for demand accesses
53 system.cpu.dcache.demand_mshr_misses 1533653 # number of demand (read+write) MSHR misses
54 system.cpu.dcache.fast_writes 0 # number of fast writes performed
55 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
56 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
57 system.cpu.dcache.occ_blocks::0 4094.960333 # Average occupied blocks per context
58 system.cpu.dcache.occ_percent::0 0.999746 # Average percentage of cache occupancy
59 system.cpu.dcache.overall_accesses 897271092 # number of overall (read+write) accesses
60 system.cpu.dcache.overall_avg_miss_latency 54458.738711 # average overall miss latency
61 system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency
62 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
63 system.cpu.dcache.overall_hits 895737439 # number of overall hits
64 system.cpu.dcache.overall_miss_latency 83520808000 # number of overall miss cycles
65 system.cpu.dcache.overall_miss_rate 0.001709 # miss rate for overall accesses
66 system.cpu.dcache.overall_misses 1533653 # number of overall misses
67 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
68 system.cpu.dcache.overall_mshr_miss_latency 78919849000 # number of overall MSHR miss cycles
69 system.cpu.dcache.overall_mshr_miss_rate 0.001709 # mshr miss rate for overall accesses
70 system.cpu.dcache.overall_mshr_misses 1533653 # number of overall MSHR misses
71 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
72 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
73 system.cpu.dcache.replacements 1529557 # number of replacements
74 system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks.
75 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
76 system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use
77 system.cpu.dcache.total_refs 895757409 # Total number of references to valid blocks.
78 system.cpu.dcache.warmup_cycle 997882000 # Cycle when the warmup percentage was hit.
79 system.cpu.dcache.writebacks 107259 # number of writebacks
80 system.cpu.dtb.accesses 0 # DTB accesses
81 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
82 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
83 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
84 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
85 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
86 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
87 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
88 system.cpu.dtb.hits 0 # DTB hits
89 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
90 system.cpu.dtb.inst_hits 0 # ITB inst hits
91 system.cpu.dtb.inst_misses 0 # ITB inst misses
92 system.cpu.dtb.misses 0 # DTB misses
93 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
94 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
95 system.cpu.dtb.read_accesses 0 # DTB read accesses
96 system.cpu.dtb.read_hits 0 # DTB read hits
97 system.cpu.dtb.read_misses 0 # DTB read misses
98 system.cpu.dtb.write_accesses 0 # DTB write accesses
99 system.cpu.dtb.write_hits 0 # DTB write hits
100 system.cpu.dtb.write_misses 0 # DTB write misses
101 system.cpu.icache.ReadReq_accesses 1390271511 # number of ReadReq accesses(hits+misses)
102 system.cpu.icache.ReadReq_avg_miss_latency 18786.850477 # average ReadReq miss latency
103 system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477 # average ReadReq mshr miss latency
104 system.cpu.icache.ReadReq_hits 1390251708 # number of ReadReq hits
105 system.cpu.icache.ReadReq_miss_latency 372036000 # number of ReadReq miss cycles
106 system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
107 system.cpu.icache.ReadReq_misses 19803 # number of ReadReq misses
108 system.cpu.icache.ReadReq_mshr_miss_latency 312627000 # number of ReadReq MSHR miss cycles
109 system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
110 system.cpu.icache.ReadReq_mshr_misses 19803 # number of ReadReq MSHR misses
111 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
112 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
113 system.cpu.icache.avg_refs 70204.095743 # Average number of references to valid blocks.
114 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
115 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
116 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
117 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
118 system.cpu.icache.cache_copies 0 # number of cache copies performed
119 system.cpu.icache.demand_accesses 1390271511 # number of demand (read+write) accesses
120 system.cpu.icache.demand_avg_miss_latency 18786.850477 # average overall miss latency
121 system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency
122 system.cpu.icache.demand_hits 1390251708 # number of demand (read+write) hits
123 system.cpu.icache.demand_miss_latency 372036000 # number of demand (read+write) miss cycles
124 system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses
125 system.cpu.icache.demand_misses 19803 # number of demand (read+write) misses
126 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
127 system.cpu.icache.demand_mshr_miss_latency 312627000 # number of demand (read+write) MSHR miss cycles
128 system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
129 system.cpu.icache.demand_mshr_misses 19803 # number of demand (read+write) MSHR misses
130 system.cpu.icache.fast_writes 0 # number of fast writes performed
131 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
132 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
133 system.cpu.icache.occ_blocks::0 1392.324437 # Average occupied blocks per context
134 system.cpu.icache.occ_percent::0 0.679846 # Average percentage of cache occupancy
135 system.cpu.icache.overall_accesses 1390271511 # number of overall (read+write) accesses
136 system.cpu.icache.overall_avg_miss_latency 18786.850477 # average overall miss latency
137 system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency
138 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
139 system.cpu.icache.overall_hits 1390251708 # number of overall hits
140 system.cpu.icache.overall_miss_latency 372036000 # number of overall miss cycles
141 system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses
142 system.cpu.icache.overall_misses 19803 # number of overall misses
143 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
144 system.cpu.icache.overall_mshr_miss_latency 312627000 # number of overall MSHR miss cycles
145 system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
146 system.cpu.icache.overall_mshr_misses 19803 # number of overall MSHR misses
147 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
148 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
149 system.cpu.icache.replacements 18364 # number of replacements
150 system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks.
151 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
152 system.cpu.icache.tagsinuse 1392.324437 # Cycle average of tags in use
153 system.cpu.icache.total_refs 1390251708 # Total number of references to valid blocks.
154 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
155 system.cpu.icache.writebacks 0 # number of writebacks
156 system.cpu.idle_fraction 0 # Percentage of idle cycles
157 system.cpu.itb.accesses 0 # DTB accesses
158 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
159 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
160 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
161 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
162 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
163 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
164 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
165 system.cpu.itb.hits 0 # DTB hits
166 system.cpu.itb.inst_accesses 0 # ITB inst accesses
167 system.cpu.itb.inst_hits 0 # ITB inst hits
168 system.cpu.itb.inst_misses 0 # ITB inst misses
169 system.cpu.itb.misses 0 # DTB misses
170 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
171 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
172 system.cpu.itb.read_accesses 0 # DTB read accesses
173 system.cpu.itb.read_hits 0 # DTB read hits
174 system.cpu.itb.read_misses 0 # DTB read misses
175 system.cpu.itb.write_accesses 0 # DTB write accesses
176 system.cpu.itb.write_hits 0 # DTB write hits
177 system.cpu.itb.write_misses 0 # DTB write misses
178 system.cpu.l2cache.ReadExReq_accesses 72780 # number of ReadExReq accesses(hits+misses)
179 system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
180 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
181 system.cpu.l2cache.ReadExReq_hits 6687 # number of ReadExReq hits
182 system.cpu.l2cache.ReadExReq_miss_latency 3436836000 # number of ReadExReq miss cycles
183 system.cpu.l2cache.ReadExReq_miss_rate 0.908120 # miss rate for ReadExReq accesses
184 system.cpu.l2cache.ReadExReq_misses 66093 # number of ReadExReq misses
185 system.cpu.l2cache.ReadExReq_mshr_miss_latency 2643720000 # number of ReadExReq MSHR miss cycles
186 system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908120 # mshr miss rate for ReadExReq accesses
187 system.cpu.l2cache.ReadExReq_mshr_misses 66093 # number of ReadExReq MSHR misses
188 system.cpu.l2cache.ReadReq_accesses 1480676 # number of ReadReq accesses(hits+misses)
189 system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
190 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
191 system.cpu.l2cache.ReadReq_hits 67139 # number of ReadReq hits
192 system.cpu.l2cache.ReadReq_miss_latency 73503924000 # number of ReadReq miss cycles
193 system.cpu.l2cache.ReadReq_miss_rate 0.954657 # miss rate for ReadReq accesses
194 system.cpu.l2cache.ReadReq_misses 1413537 # number of ReadReq misses
195 system.cpu.l2cache.ReadReq_mshr_miss_latency 56541480000 # number of ReadReq MSHR miss cycles
196 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.954657 # mshr miss rate for ReadReq accesses
197 system.cpu.l2cache.ReadReq_mshr_misses 1413537 # number of ReadReq MSHR misses
198 system.cpu.l2cache.Writeback_accesses 107259 # number of Writeback accesses(hits+misses)
199 system.cpu.l2cache.Writeback_hits 107259 # number of Writeback hits
200 system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
201 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
202 system.cpu.l2cache.avg_refs 0.049920 # Average number of references to valid blocks.
203 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
204 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
205 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
206 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
207 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
208 system.cpu.l2cache.demand_accesses 1553456 # number of demand (read+write) accesses
209 system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
210 system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
211 system.cpu.l2cache.demand_hits 73826 # number of demand (read+write) hits
212 system.cpu.l2cache.demand_miss_latency 76940760000 # number of demand (read+write) miss cycles
213 system.cpu.l2cache.demand_miss_rate 0.952476 # miss rate for demand accesses
214 system.cpu.l2cache.demand_misses 1479630 # number of demand (read+write) misses
215 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
216 system.cpu.l2cache.demand_mshr_miss_latency 59185200000 # number of demand (read+write) MSHR miss cycles
217 system.cpu.l2cache.demand_mshr_miss_rate 0.952476 # mshr miss rate for demand accesses
218 system.cpu.l2cache.demand_mshr_misses 1479630 # number of demand (read+write) MSHR misses
219 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
220 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
221 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
222 system.cpu.l2cache.occ_blocks::0 28893.420796 # Average occupied blocks per context
223 system.cpu.l2cache.occ_blocks::1 3041.423322 # Average occupied blocks per context
224 system.cpu.l2cache.occ_percent::0 0.881757 # Average percentage of cache occupancy
225 system.cpu.l2cache.occ_percent::1 0.092817 # Average percentage of cache occupancy
226 system.cpu.l2cache.overall_accesses 1553456 # number of overall (read+write) accesses
227 system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
228 system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
229 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
230 system.cpu.l2cache.overall_hits 73826 # number of overall hits
231 system.cpu.l2cache.overall_miss_latency 76940760000 # number of overall miss cycles
232 system.cpu.l2cache.overall_miss_rate 0.952476 # miss rate for overall accesses
233 system.cpu.l2cache.overall_misses 1479630 # number of overall misses
234 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
235 system.cpu.l2cache.overall_mshr_miss_latency 59185200000 # number of overall MSHR miss cycles
236 system.cpu.l2cache.overall_mshr_miss_rate 0.952476 # mshr miss rate for overall accesses
237 system.cpu.l2cache.overall_mshr_misses 1479630 # number of overall MSHR misses
238 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
239 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
240 system.cpu.l2cache.replacements 1478755 # number of replacements
241 system.cpu.l2cache.sampled_refs 1511475 # Sample count of references to valid blocks.
242 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
243 system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use
244 system.cpu.l2cache.total_refs 75453 # Total number of references to valid blocks.
245 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
246 system.cpu.l2cache.writebacks 66099 # number of writebacks
247 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
248 system.cpu.numCycles 4739803920 # number of cpu cycles simulated
249 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
250 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
251 system.cpu.num_busy_cycles 4739803920 # Number of busy cycles
252 system.cpu.num_conditional_control_insts 223625914 # number of instructions that are conditional controls
253 system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
254 system.cpu.num_fp_insts 52289415 # number of float instructions
255 system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read
256 system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written
257 system.cpu.num_func_calls 80344203 # number of times a function call or return occured
258 system.cpu.num_idle_cycles 0 # Number of idle cycles
259 system.cpu.num_insts 1874244950 # Number of instructions executed
260 system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses
261 system.cpu.num_int_insts 1653698876 # number of integer instructions
262 system.cpu.num_int_register_reads 10466679954 # number of times the integer registers were read
263 system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written
264 system.cpu.num_load_insts 631387182 # Number of load instructions
265 system.cpu.num_mem_refs 908382480 # number of memory refs
266 system.cpu.num_store_insts 276995298 # Number of store instructions
267 system.cpu.workload.num_syscalls 1411 # Number of system calls
269 ---------- End Simulation Statistics ----------
projects / gem5.git / blob