2 ---------- Begin Simulation Statistics ----------
3 global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
4 global.BPredUnit.BTBHits 13144986 # Number of BTB hits
5 global.BPredUnit.BTBLookups 21876990 # Number of BTB lookups
6 global.BPredUnit.RASInCorrect 30485 # Number of incorrect RAS predictions.
7 global.BPredUnit.condIncorrect 454636 # Number of conditional branches incorrect
8 global.BPredUnit.condPredicted 16268422 # Number of conditional branches predicted
9 global.BPredUnit.lookups 26797394 # Number of BP lookups
10 global.BPredUnit.usedRAS 4858022 # Number of times the RAS was used to get a target.
11 host_inst_rate 52852 # Simulator instruction rate (inst/s)
12 host_mem_usage 259420 # Number of bytes of host memory used
13 host_seconds 1506.34 # Real time elapsed on the host
14 host_tick_rate 744190 # Simulator tick rate (ticks/s)
15 memdepunit.memDep.conflictingLoads 14725219 # Number of conflicting loads.
16 memdepunit.memDep.conflictingStores 11320400 # Number of conflicting stores.
17 memdepunit.memDep.insertedLoads 28503669 # Number of loads inserted to the mem dependence unit.
18 memdepunit.memDep.insertedStores 16218894 # Number of stores inserted to the mem dependence unit.
19 sim_freq 1000000000000 # Frequency of simulated ticks
20 sim_insts 79613339 # Number of instructions simulated
21 sim_seconds 0.001121 # Number of seconds simulated
22 sim_ticks 1121005014 # Number of ticks simulated
23 system.cpu.commit.COM:branches 13759853 # Number of branches committed
24 system.cpu.commit.COM:bw_lim_events 3902181 # number cycles where commit BW limit reached
25 system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
26 system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
27 system.cpu.commit.COM:committed_per_cycle.samples 88439527
28 system.cpu.commit.COM:committed_per_cycle.min_value 0
38 system.cpu.commit.COM:committed_per_cycle.max_value 8
39 system.cpu.commit.COM:committed_per_cycle.end_dist
41 system.cpu.commit.COM:count 88361897 # Number of instructions committed
42 system.cpu.commit.COM:loads 20383045 # Number of loads committed
43 system.cpu.commit.COM:membars 0 # Number of memory barriers committed
44 system.cpu.commit.COM:refs 35229375 # Number of memory references committed
45 system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
46 system.cpu.commit.branchMispredicts 360073 # The number of times a branch was mispredicted
47 system.cpu.commit.commitCommittedInsts 88361897 # The number of committed instructions
48 system.cpu.commit.commitNonSpecStalls 4706 # The number of times commit has been forced to stall to communicate backwards
49 system.cpu.commit.commitSquashedInsts 20725845 # The number of squashed insts skipped by commit
50 system.cpu.committedInsts 79613339 # Number of Instructions Simulated
51 system.cpu.committedInsts_total 79613339 # Number of Instructions Simulated
52 system.cpu.cpi 14.080618 # CPI: Cycles Per Instruction
53 system.cpu.cpi_total 14.080618 # CPI: Total CPI of All Threads
54 system.cpu.dcache.ReadReq_accesses 19542402 # number of ReadReq accesses(hits+misses)
55 system.cpu.dcache.ReadReq_avg_miss_latency 4437.586724 # average ReadReq miss latency
56 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3280.646620 # average ReadReq mshr miss latency
57 system.cpu.dcache.ReadReq_hits 19388897 # number of ReadReq hits
58 system.cpu.dcache.ReadReq_miss_latency 681191750 # number of ReadReq miss cycles
59 system.cpu.dcache.ReadReq_miss_rate 0.007855 # miss rate for ReadReq accesses
60 system.cpu.dcache.ReadReq_misses 153505 # number of ReadReq misses
61 system.cpu.dcache.ReadReq_mshr_hits 94427 # number of ReadReq MSHR hits
62 system.cpu.dcache.ReadReq_mshr_miss_latency 193814041 # number of ReadReq MSHR miss cycles
63 system.cpu.dcache.ReadReq_mshr_miss_rate 0.003023 # mshr miss rate for ReadReq accesses
64 system.cpu.dcache.ReadReq_mshr_misses 59078 # number of ReadReq MSHR misses
65 system.cpu.dcache.WriteReq_accesses 14615683 # number of WriteReq accesses(hits+misses)
66 system.cpu.dcache.WriteReq_avg_miss_latency 4852.594089 # average WriteReq miss latency
67 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4028.169523 # average WriteReq mshr miss latency
68 system.cpu.dcache.WriteReq_hits 13950409 # number of WriteReq hits
69 system.cpu.dcache.WriteReq_miss_latency 3228304680 # number of WriteReq miss cycles
70 system.cpu.dcache.WriteReq_miss_rate 0.045518 # miss rate for WriteReq accesses
71 system.cpu.dcache.WriteReq_misses 665274 # number of WriteReq misses
72 system.cpu.dcache.WriteReq_mshr_hits 523305 # number of WriteReq MSHR hits
73 system.cpu.dcache.WriteReq_mshr_miss_latency 571875199 # number of WriteReq MSHR miss cycles
74 system.cpu.dcache.WriteReq_mshr_miss_rate 0.009713 # mshr miss rate for WriteReq accesses
75 system.cpu.dcache.WriteReq_mshr_misses 141969 # number of WriteReq MSHR misses
76 system.cpu.dcache.avg_blocked_cycles_no_mshrs 3068.165217 # average number of cycles each access was blocked
77 system.cpu.dcache.avg_blocked_cycles_no_targets 3779.642588 # average number of cycles each access was blocked
78 system.cpu.dcache.avg_refs 165.828418 # Average number of references to valid blocks.
79 system.cpu.dcache.blocked_no_mshrs 115 # number of cycles access was blocked
80 system.cpu.dcache.blocked_no_targets 125189 # number of cycles access was blocked
81 system.cpu.dcache.blocked_cycles_no_mshrs 352839 # number of cycles access was blocked
82 system.cpu.dcache.blocked_cycles_no_targets 473169676 # number of cycles access was blocked
83 system.cpu.dcache.cache_copies 0 # number of cache copies performed
84 system.cpu.dcache.demand_accesses 34158085 # number of demand (read+write) accesses
85 system.cpu.dcache.demand_avg_miss_latency 4774.788349 # average overall miss latency
86 system.cpu.dcache.demand_avg_mshr_miss_latency 3808.508657 # average overall mshr miss latency
87 system.cpu.dcache.demand_hits 33339306 # number of demand (read+write) hits
88 system.cpu.dcache.demand_miss_latency 3909496430 # number of demand (read+write) miss cycles
89 system.cpu.dcache.demand_miss_rate 0.023970 # miss rate for demand accesses
90 system.cpu.dcache.demand_misses 818779 # number of demand (read+write) misses
91 system.cpu.dcache.demand_mshr_hits 617732 # number of demand (read+write) MSHR hits
92 system.cpu.dcache.demand_mshr_miss_latency 765689240 # number of demand (read+write) MSHR miss cycles
93 system.cpu.dcache.demand_mshr_miss_rate 0.005886 # mshr miss rate for demand accesses
94 system.cpu.dcache.demand_mshr_misses 201047 # number of demand (read+write) MSHR misses
95 system.cpu.dcache.fast_writes 0 # number of fast writes performed
96 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
97 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
98 system.cpu.dcache.overall_accesses 34158085 # number of overall (read+write) accesses
99 system.cpu.dcache.overall_avg_miss_latency 4774.788349 # average overall miss latency
100 system.cpu.dcache.overall_avg_mshr_miss_latency 3808.508657 # average overall mshr miss latency
101 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
102 system.cpu.dcache.overall_hits 33339306 # number of overall hits
103 system.cpu.dcache.overall_miss_latency 3909496430 # number of overall miss cycles
104 system.cpu.dcache.overall_miss_rate 0.023970 # miss rate for overall accesses
105 system.cpu.dcache.overall_misses 818779 # number of overall misses
106 system.cpu.dcache.overall_mshr_hits 617732 # number of overall MSHR hits
107 system.cpu.dcache.overall_mshr_miss_latency 765689240 # number of overall MSHR miss cycles
108 system.cpu.dcache.overall_mshr_miss_rate 0.005886 # mshr miss rate for overall accesses
109 system.cpu.dcache.overall_mshr_misses 201047 # number of overall MSHR misses
110 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
111 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
112 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
113 system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
114 system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
115 system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
116 system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
117 system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
118 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
119 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
120 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
121 system.cpu.dcache.replacements 196951 # number of replacements
122 system.cpu.dcache.sampled_refs 201047 # Sample count of references to valid blocks.
123 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
124 system.cpu.dcache.tagsinuse 4057.206862 # Cycle average of tags in use
125 system.cpu.dcache.total_refs 33339306 # Total number of references to valid blocks.
126 system.cpu.dcache.warmup_cycle 27763000 # Cycle when the warmup percentage was hit.
127 system.cpu.dcache.writebacks 147199 # number of writebacks
128 system.cpu.decode.DECODE:BlockedCycles 11824495 # Number of cycles decode is blocked
129 system.cpu.decode.DECODE:BranchMispred 95570 # Number of times decode detected a branch misprediction
130 system.cpu.decode.DECODE:BranchResolved 3548160 # Number of times decode resolved a branch
131 system.cpu.decode.DECODE:DecodedInsts 129766996 # Number of instructions handled by decode
132 system.cpu.decode.DECODE:IdleCycles 51039022 # Number of cycles decode is idle
133 system.cpu.decode.DECODE:RunCycles 25179247 # Number of cycles decode is running
134 system.cpu.decode.DECODE:SquashCycles 4520828 # Number of cycles decode is squashing
135 system.cpu.decode.DECODE:SquashedInsts 280755 # Number of squashed instructions handled by decode
136 system.cpu.decode.DECODE:UnblockCycles 396764 # Number of cycles decode is unblocking
137 system.cpu.fetch.Branches 26797394 # Number of branches that fetch encountered
138 system.cpu.fetch.CacheLines 22435045 # Number of cache lines fetched
139 system.cpu.fetch.Cycles 50869599 # Number of cycles fetch has run and was not squashing or blocked
140 system.cpu.fetch.IcacheSquashes 152238 # Number of outstanding Icache misses that were squashed
141 system.cpu.fetch.Insts 146401648 # Number of instructions fetch has processed
142 system.cpu.fetch.SquashCycles 3850495 # Number of cycles fetch has spent squashing
143 system.cpu.fetch.branchRate 0.288267 # Number of branch fetches per cycle
144 system.cpu.fetch.icacheStallCycles 22435045 # Number of cycles fetch is stalled on an Icache miss
145 system.cpu.fetch.predictedBranches 18003008 # Number of branches that fetch has predicted taken
146 system.cpu.fetch.rate 1.574883 # Number of inst fetches per cycle
147 system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
148 system.cpu.fetch.rateDist.samples 92960356
149 system.cpu.fetch.rateDist.min_value 0
159 system.cpu.fetch.rateDist.max_value 8
160 system.cpu.fetch.rateDist.end_dist
162 system.cpu.icache.ReadReq_accesses 22435044 # number of ReadReq accesses(hits+misses)
163 system.cpu.icache.ReadReq_avg_miss_latency 3343.146524 # average ReadReq miss latency
164 system.cpu.icache.ReadReq_avg_mshr_miss_latency 2355.643274 # average ReadReq mshr miss latency
165 system.cpu.icache.ReadReq_hits 22333491 # number of ReadReq hits
166 system.cpu.icache.ReadReq_miss_latency 339506559 # number of ReadReq miss cycles
167 system.cpu.icache.ReadReq_miss_rate 0.004527 # miss rate for ReadReq accesses
168 system.cpu.icache.ReadReq_misses 101553 # number of ReadReq misses
169 system.cpu.icache.ReadReq_mshr_hits 13791 # number of ReadReq MSHR hits
170 system.cpu.icache.ReadReq_mshr_miss_latency 206735965 # number of ReadReq MSHR miss cycles
171 system.cpu.icache.ReadReq_mshr_miss_rate 0.003912 # mshr miss rate for ReadReq accesses
172 system.cpu.icache.ReadReq_mshr_misses 87762 # number of ReadReq MSHR misses
173 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
174 system.cpu.icache.avg_blocked_cycles_no_targets 3964.923913 # average number of cycles each access was blocked
175 system.cpu.icache.avg_refs 254.480817 # Average number of references to valid blocks.
176 system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
177 system.cpu.icache.blocked_no_targets 92 # number of cycles access was blocked
178 system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
179 system.cpu.icache.blocked_cycles_no_targets 364773 # number of cycles access was blocked
180 system.cpu.icache.cache_copies 0 # number of cache copies performed
181 system.cpu.icache.demand_accesses 22435044 # number of demand (read+write) accesses
182 system.cpu.icache.demand_avg_miss_latency 3343.146524 # average overall miss latency
183 system.cpu.icache.demand_avg_mshr_miss_latency 2355.643274 # average overall mshr miss latency
184 system.cpu.icache.demand_hits 22333491 # number of demand (read+write) hits
185 system.cpu.icache.demand_miss_latency 339506559 # number of demand (read+write) miss cycles
186 system.cpu.icache.demand_miss_rate 0.004527 # miss rate for demand accesses
187 system.cpu.icache.demand_misses 101553 # number of demand (read+write) misses
188 system.cpu.icache.demand_mshr_hits 13791 # number of demand (read+write) MSHR hits
189 system.cpu.icache.demand_mshr_miss_latency 206735965 # number of demand (read+write) MSHR miss cycles
190 system.cpu.icache.demand_mshr_miss_rate 0.003912 # mshr miss rate for demand accesses
191 system.cpu.icache.demand_mshr_misses 87762 # number of demand (read+write) MSHR misses
192 system.cpu.icache.fast_writes 0 # number of fast writes performed
193 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
194 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
195 system.cpu.icache.overall_accesses 22435044 # number of overall (read+write) accesses
196 system.cpu.icache.overall_avg_miss_latency 3343.146524 # average overall miss latency
197 system.cpu.icache.overall_avg_mshr_miss_latency 2355.643274 # average overall mshr miss latency
198 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
199 system.cpu.icache.overall_hits 22333491 # number of overall hits
200 system.cpu.icache.overall_miss_latency 339506559 # number of overall miss cycles
201 system.cpu.icache.overall_miss_rate 0.004527 # miss rate for overall accesses
202 system.cpu.icache.overall_misses 101553 # number of overall misses
203 system.cpu.icache.overall_mshr_hits 13791 # number of overall MSHR hits
204 system.cpu.icache.overall_mshr_miss_latency 206735965 # number of overall MSHR miss cycles
205 system.cpu.icache.overall_mshr_miss_rate 0.003912 # mshr miss rate for overall accesses
206 system.cpu.icache.overall_mshr_misses 87762 # number of overall MSHR misses
207 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
208 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
209 system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
210 system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
211 system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
212 system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
213 system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
214 system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
215 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
216 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
217 system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
218 system.cpu.icache.replacements 85714 # number of replacements
219 system.cpu.icache.sampled_refs 87761 # Sample count of references to valid blocks.
220 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
221 system.cpu.icache.tagsinuse 1835.660061 # Cycle average of tags in use
222 system.cpu.icache.total_refs 22333491 # Total number of references to valid blocks.
223 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
224 system.cpu.icache.writebacks 0 # number of writebacks
225 system.cpu.idleCycles 1028044659 # Total number of cycles that the CPU has spent unscheduled due to idling
226 system.cpu.iew.EXEC:branches 14368697 # Number of branches executed
227 system.cpu.iew.EXEC:nop 9207761 # number of nop insts executed
228 system.cpu.iew.EXEC:rate 0.998957 # Inst execution rate
229 system.cpu.iew.EXEC:refs 42889191 # number of memory reference insts executed
230 system.cpu.iew.EXEC:stores 15296362 # Number of stores executed
231 system.cpu.iew.EXEC:swp 0 # number of swp insts executed
232 system.cpu.iew.WB:consumers 46149810 # num instructions consuming a value
233 system.cpu.iew.WB:count 85978243 # cumulative count of insts written-back
234 system.cpu.iew.WB:fanout 0.741638 # average fanout of values written-back
235 system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
236 system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
237 system.cpu.iew.WB:producers 34226464 # num instructions producing a value
238 system.cpu.iew.WB:rate 0.924891 # insts written-back per cycle
239 system.cpu.iew.WB:sent 86043563 # cumulative count of insts sent to commit
240 system.cpu.iew.branchMispredicts 388948 # Number of branch mispredicts detected at execute
241 system.cpu.iew.iewBlockCycles 3476074 # Number of cycles IEW is blocking
242 system.cpu.iew.iewDispLoadInsts 28503669 # Number of dispatched load instructions
243 system.cpu.iew.iewDispNonSpecInsts 5221 # Number of dispatched non-speculative instructions
244 system.cpu.iew.iewDispSquashedInsts 1221579 # Number of squashed instructions skipped by dispatch
245 system.cpu.iew.iewDispStoreInsts 16218894 # Number of dispatched store instructions
246 system.cpu.iew.iewDispatchedInsts 109084579 # Number of instructions dispatched to IQ
247 system.cpu.iew.iewExecLoadInsts 27592829 # Number of load instructions executed
248 system.cpu.iew.iewExecSquashedInsts 454683 # Number of squashed instructions skipped in execute
249 system.cpu.iew.iewExecutedInsts 92863355 # Number of executed instructions
250 system.cpu.iew.iewIQFullEvents 28537 # Number of times the IQ has become full, causing a stall
251 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
252 system.cpu.iew.iewLSQFullEvents 13436 # Number of times the LSQ has become full, causing a stall
253 system.cpu.iew.iewSquashCycles 4520828 # Number of cycles IEW is squashing
254 system.cpu.iew.iewUnblockCycles 193035 # Number of cycles IEW is unblocking
255 system.cpu.iew.lsq.thread.0.blockedLoads 1537 # Number of blocked loads due to partial load-store forwarding
256 system.cpu.iew.lsq.thread.0.cacheBlocked 6697780 # Number of times an access to memory failed due to the cache being blocked
257 system.cpu.iew.lsq.thread.0.forwLoads 1365345 # Number of loads that had data forwarded from stores
258 system.cpu.iew.lsq.thread.0.ignoredResponses 4018 # Number of memory responses ignored because the instruction is squashed
259 system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
260 system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
261 system.cpu.iew.lsq.thread.0.memOrderViolation 3952 # Number of memory ordering violations
262 system.cpu.iew.lsq.thread.0.rescheduledLoads 1537 # Number of loads that were rescheduled
263 system.cpu.iew.lsq.thread.0.squashedLoads 8120624 # Number of loads squashed
264 system.cpu.iew.lsq.thread.0.squashedStores 1372564 # Number of stores squashed
265 system.cpu.iew.memOrderViolationEvents 3952 # Number of memory order violations
266 system.cpu.iew.predictedNotTakenIncorrect 217352 # Number of branches that were predicted not taken incorrectly
267 system.cpu.iew.predictedTakenIncorrect 171596 # Number of branches that were predicted taken incorrectly
268 system.cpu.ipc 0.071020 # IPC: Instructions Per Cycle
269 system.cpu.ipc_total 0.071020 # IPC: Total IPC of All Threads
270 system.cpu.iq.ISSUE:FU_type_0 93318038 # Type of FU issued
271 system.cpu.iq.ISSUE:FU_type_0.start_dist
272 (null) 0 0.00% # Type of FU issued
273 IntAlu 49917747 53.49% # Type of FU issued
274 IntMult 43212 0.05% # Type of FU issued
275 IntDiv 0 0.00% # Type of FU issued
276 FloatAdd 123778 0.13% # Type of FU issued
277 FloatCmp 88 0.00% # Type of FU issued
278 FloatCvt 122460 0.13% # Type of FU issued
279 FloatMult 54 0.00% # Type of FU issued
280 FloatDiv 37863 0.04% # Type of FU issued
281 FloatSqrt 0 0.00% # Type of FU issued
282 MemRead 27694961 29.68% # Type of FU issued
283 MemWrite 15377875 16.48% # Type of FU issued
284 IprAccess 0 0.00% # Type of FU issued
285 InstPrefetch 0 0.00% # Type of FU issued
286 system.cpu.iq.ISSUE:FU_type_0.end_dist
287 system.cpu.iq.ISSUE:fu_busy_cnt 1239796 # FU busy when requested
288 system.cpu.iq.ISSUE:fu_busy_rate 0.013286 # FU busy rate (busy events/executed inst)
289 system.cpu.iq.ISSUE:fu_full.start_dist
290 (null) 0 0.00% # attempts to use FU when none available
291 IntAlu 81158 6.55% # attempts to use FU when none available
292 IntMult 0 0.00% # attempts to use FU when none available
293 IntDiv 0 0.00% # attempts to use FU when none available
294 FloatAdd 0 0.00% # attempts to use FU when none available
295 FloatCmp 0 0.00% # attempts to use FU when none available
296 FloatCvt 0 0.00% # attempts to use FU when none available
297 FloatMult 0 0.00% # attempts to use FU when none available
298 FloatDiv 0 0.00% # attempts to use FU when none available
299 FloatSqrt 0 0.00% # attempts to use FU when none available
300 MemRead 587235 47.37% # attempts to use FU when none available
301 MemWrite 571403 46.09% # attempts to use FU when none available
302 IprAccess 0 0.00% # attempts to use FU when none available
303 InstPrefetch 0 0.00% # attempts to use FU when none available
304 system.cpu.iq.ISSUE:fu_full.end_dist
305 system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
306 system.cpu.iq.ISSUE:issued_per_cycle.samples 92960356
307 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
317 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
318 system.cpu.iq.ISSUE:issued_per_cycle.end_dist
320 system.cpu.iq.ISSUE:rate 1.003848 # Inst issue rate
321 system.cpu.iq.iqInstsAdded 99871597 # Number of instructions added to the IQ (excludes non-spec)
322 system.cpu.iq.iqInstsIssued 93318038 # Number of instructions issued
323 system.cpu.iq.iqNonSpecInstsAdded 5221 # Number of non-speculative instructions added to the IQ
324 system.cpu.iq.iqSquashedInstsExamined 20057396 # Number of squashed instructions iterated over during squash; mainly for profiling
325 system.cpu.iq.iqSquashedInstsIssued 77651 # Number of squashed instructions issued
326 system.cpu.iq.iqSquashedNonSpecRemoved 515 # Number of squashed non-spec instructions that were removed
327 system.cpu.iq.iqSquashedOperandsExamined 15480029 # Number of squashed operands that are examined and possibly removed from graph
328 system.cpu.l2cache.ReadReq_accesses 288801 # number of ReadReq accesses(hits+misses)
329 system.cpu.l2cache.ReadReq_avg_miss_latency 3932.513738 # average ReadReq miss latency
330 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2042.965502 # average ReadReq mshr miss latency
331 system.cpu.l2cache.ReadReq_hits 119343 # number of ReadReq hits
332 system.cpu.l2cache.ReadReq_miss_latency 666395913 # number of ReadReq miss cycles
333 system.cpu.l2cache.ReadReq_miss_rate 0.586764 # miss rate for ReadReq accesses
334 system.cpu.l2cache.ReadReq_misses 169458 # number of ReadReq misses
335 system.cpu.l2cache.ReadReq_mshr_miss_latency 346196848 # number of ReadReq MSHR miss cycles
336 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.586764 # mshr miss rate for ReadReq accesses
337 system.cpu.l2cache.ReadReq_mshr_misses 169458 # number of ReadReq MSHR misses
338 system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 147199 # number of WriteReqNoAck|Writeback accesses(hits+misses)
339 system.cpu.l2cache.WriteReqNoAck|Writeback_hits 146588 # number of WriteReqNoAck|Writeback hits
340 system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.004151 # miss rate for WriteReqNoAck|Writeback accesses
341 system.cpu.l2cache.WriteReqNoAck|Writeback_misses 611 # number of WriteReqNoAck|Writeback misses
342 system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.004151 # mshr miss rate for WriteReqNoAck|Writeback accesses
343 system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 611 # number of WriteReqNoAck|Writeback MSHR misses
344 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
345 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
346 system.cpu.l2cache.avg_refs 1.569313 # Average number of references to valid blocks.
347 system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
348 system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
349 system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
350 system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
351 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
352 system.cpu.l2cache.demand_accesses 288801 # number of demand (read+write) accesses
353 system.cpu.l2cache.demand_avg_miss_latency 3932.513738 # average overall miss latency
354 system.cpu.l2cache.demand_avg_mshr_miss_latency 2042.965502 # average overall mshr miss latency
355 system.cpu.l2cache.demand_hits 119343 # number of demand (read+write) hits
356 system.cpu.l2cache.demand_miss_latency 666395913 # number of demand (read+write) miss cycles
357 system.cpu.l2cache.demand_miss_rate 0.586764 # miss rate for demand accesses
358 system.cpu.l2cache.demand_misses 169458 # number of demand (read+write) misses
359 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
360 system.cpu.l2cache.demand_mshr_miss_latency 346196848 # number of demand (read+write) MSHR miss cycles
361 system.cpu.l2cache.demand_mshr_miss_rate 0.586764 # mshr miss rate for demand accesses
362 system.cpu.l2cache.demand_mshr_misses 169458 # number of demand (read+write) MSHR misses
363 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
364 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
365 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
366 system.cpu.l2cache.overall_accesses 436000 # number of overall (read+write) accesses
367 system.cpu.l2cache.overall_avg_miss_latency 3918.385555 # average overall miss latency
368 system.cpu.l2cache.overall_avg_mshr_miss_latency 2042.965502 # average overall mshr miss latency
369 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
370 system.cpu.l2cache.overall_hits 265931 # number of overall hits
371 system.cpu.l2cache.overall_miss_latency 666395913 # number of overall miss cycles
372 system.cpu.l2cache.overall_miss_rate 0.390067 # miss rate for overall accesses
373 system.cpu.l2cache.overall_misses 170069 # number of overall misses
374 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
375 system.cpu.l2cache.overall_mshr_miss_latency 346196848 # number of overall MSHR miss cycles
376 system.cpu.l2cache.overall_mshr_miss_rate 0.388665 # mshr miss rate for overall accesses
377 system.cpu.l2cache.overall_mshr_misses 169458 # number of overall MSHR misses
378 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
379 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
380 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
381 system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
382 system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
383 system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
384 system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
385 system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
386 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
387 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
388 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
389 system.cpu.l2cache.replacements 136689 # number of replacements
390 system.cpu.l2cache.sampled_refs 169457 # Sample count of references to valid blocks.
391 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
392 system.cpu.l2cache.tagsinuse 30306.924097 # Cycle average of tags in use
393 system.cpu.l2cache.total_refs 265931 # Total number of references to valid blocks.
394 system.cpu.l2cache.warmup_cycle 442261000 # Cycle when the warmup percentage was hit.
395 system.cpu.l2cache.writebacks 115687 # number of writebacks
396 system.cpu.numCycles 92960356 # number of cpu cycles simulated
397 system.cpu.rename.RENAME:BlockCycles 7634208 # Number of cycles rename is blocking
398 system.cpu.rename.RENAME:CommittedMaps 52562815 # Number of HB maps that are committed
399 system.cpu.rename.RENAME:IQFullEvents 86713 # Number of times rename has blocked due to IQ full
400 system.cpu.rename.RENAME:IdleCycles 51709233 # Number of cycles rename is idle
401 system.cpu.rename.RENAME:LSQFullEvents 3226687 # Number of times rename has blocked due to LSQ full
402 system.cpu.rename.RENAME:ROBFullEvents 2442 # Number of times rename has blocked due to ROB full
403 system.cpu.rename.RENAME:RenameLookups 152860701 # Number of register rename lookups that rename has made
404 system.cpu.rename.RENAME:RenamedInsts 128373944 # Number of instructions processed by rename
405 system.cpu.rename.RENAME:RenamedOperands 81757058 # Number of destination operands rename has renamed
406 system.cpu.rename.RENAME:RunCycles 24895195 # Number of cycles rename is running
407 system.cpu.rename.RENAME:SquashCycles 4520828 # Number of cycles rename is squashing
408 system.cpu.rename.RENAME:UnblockCycles 3457989 # Number of cycles rename is unblocking
409 system.cpu.rename.RENAME:UndoneMaps 29194243 # Number of HB maps that are undone due to squashing
410 system.cpu.rename.RENAME:serializeStallCycles 742903 # count of cycles rename stalled for serializing inst
411 system.cpu.rename.RENAME:serializingInsts 5237 # count of serializing insts renamed
412 system.cpu.rename.RENAME:skidInsts 6117149 # count of insts added to the skid buffer
413 system.cpu.rename.RENAME:tempSerializingInsts 5235 # count of temporary serializing insts renamed
414 system.cpu.timesIdled 271656 # Number of times that the entire CPU went into an idle state and unscheduled itself
415 system.cpu.workload.PROG:num_syscalls 4706 # Number of system calls
417 ---------- End Simulation Statistics ----------
projects / gem5.git / blob